/*
 * $Id: hl65.h,v 1.20.72.1 Broadcom SDK $
 * $Copyright: Copyright 2011 Broadcom Corporation.
 * This program is the proprietary software of Broadcom Corporation
 * and/or its licensors, and may only be used, duplicated, modified
 * or distributed pursuant to the terms and conditions of a separate,
 * written license agreement executed between you and Broadcom
 * (an "Authorized License").  Except as set forth in an Authorized
 * License, Broadcom grants no license (express or implied), right
 * to use, or waiver of any kind with respect to the Software, and
 * Broadcom expressly reserves all rights in and to the Software
 * and all intellectual property rights therein.  IF YOU HAVE
 * NO AUTHORIZED LICENSE, THEN YOU HAVE NO RIGHT TO USE THIS SOFTWARE
 * IN ANY WAY, AND SHOULD IMMEDIATELY NOTIFY BROADCOM AND DISCONTINUE
 * ALL USE OF THE SOFTWARE.  
 *  
 * Except as expressly set forth in the Authorized License,
 *  
 * 1.     This program, including its structure, sequence and organization,
 * constitutes the valuable trade secrets of Broadcom, and you shall use
 * all reasonable efforts to protect the confidentiality thereof,
 * and to use this information only in connection with your use of
 * Broadcom integrated circuit products.
 *  
 * 2.     TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS
 * PROVIDED "AS IS" AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES,
 * REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY,
 * OR OTHERWISE, WITH RESPECT TO THE SOFTWARE.  BROADCOM SPECIFICALLY
 * DISCLAIMS ANY AND ALL IMPLIED WARRANTIES OF TITLE, MERCHANTABILITY,
 * NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES,
 * ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
 * CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING
 * OUT OF USE OR PERFORMANCE OF THE SOFTWARE.
 * 
 * 3.     TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL
 * BROADCOM OR ITS LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL,
 * INCIDENTAL, SPECIAL, INDIRECT, OR EXEMPLARY DAMAGES WHATSOEVER
 * ARISING OUT OF OR IN ANY WAY RELATING TO YOUR USE OF OR INABILITY
 * TO USE THE SOFTWARE EVEN IF BROADCOM HAS BEEN ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN EXCESS OF
 * THE AMOUNT ACTUALLY PAID FOR THE SOFTWARE ITSELF OR USD 1.00,
 * WHICHEVER IS GREATER. THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING
 * ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.$
 *
 * File:        hl65.h
 * Purpose:     Hyperlite/Hypercore driver header file, auto-generated.
 */

/***************************************************************************
 *     Copyright (c) 1999-2008, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *
 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * $brcm_Workfile: $
 * $brcm_Revision: $
 * $brcm_Date: $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Mon Sep 22 12:04:36 2008
 *                 MD5 Checksum         70565ec876bdd0354d6a4398fcc61be3
 *
 * Compiled with:  RDB Utility          5.0
 *                 RDB Parser           3.0
 *                 rdb2macro.pm         4.0
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Spec Versions:  aer                  1
 *                 combo                1
 *                 dsc_1                1
 *                 dsc_2                1
 *                 dsc_3                1
 *                 dsc_4                1
 *                 ieee                 1
 *                 rx66                 1
 *                 tx66                 1
 *                 xgxs                 1
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef HC65_H__
#define HC65_H__

/**
 * m = memory, c = core, r = register, f = field, d = data.
 */
#if !defined(GET_FIELD) && !defined(SET_FIELD)
#define BRCM_ALIGN(c,r,f)   c##_##r##_##f##_ALIGN
#define BRCM_BITS(c,r,f)    c##_##r##_##f##_BITS
#define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
#define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT

#define GET_FIELD(m,c,r,f) \
	((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f))

#define SET_FIELD(m,c,r,f,d) \
	((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \
	 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \
	)

#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)

#endif /* GET & SET */

/****************************************************************************
 * Core Enums.
 ***************************************************************************/
/****************************************************************************
 * Enums: combo_operationModes
 ***************************************************************************/
#define combo_operationModes_XGXS                          0
#define combo_operationModes_XGXG_nCC                      1
#define combo_operationModes_IndLane_OS5                   5
#define combo_operationModes_Indlanes                      6
#define combo_operationModes_PCI                           7
#define combo_operationModes_XGXS_nLQ                      8
#define combo_operationModes_XGXS_nLQnCC                   9
#define combo_operationModes_PBypass                       10
#define combo_operationModes_PBypass_nDSK                  11
#define combo_operationModes_ComboCoreMode                 12
#define combo_operationModes_Clocks_off                    15

/****************************************************************************
 * Enums: combo_actualSpeeds4
 ***************************************************************************/
#define combo_actualSpeeds4_dr_10M                         0
#define combo_actualSpeeds4_dr_100M                        1
#define combo_actualSpeeds4_dr_1G                          2
#define combo_actualSpeeds4_dr_2p5G                        3
#define combo_actualSpeeds4_dr_5G_X4                       4
#define combo_actualSpeeds4_dr_6G_X4                       5
#define combo_actualSpeeds4_dr_10G_HiG                     6
#define combo_actualSpeeds4_dr_10G_CX4                     7
#define combo_actualSpeeds4_dr_12G_HiG                     8
#define combo_actualSpeeds4_dr_12p5G_X4                    9
#define combo_actualSpeeds4_dr_13G_X4                      10
#define combo_actualSpeeds4_dr_15G_X4                      11
#define combo_actualSpeeds4_dr_16G_X4                      12

/****************************************************************************
 * Enums: combo_actualSpeeds5
 ***************************************************************************/
#define combo_actualSpeeds5_dr_10M                         0
#define combo_actualSpeeds5_dr_100M                        1
#define combo_actualSpeeds5_dr_1G                          2
#define combo_actualSpeeds5_dr_2p5G                        3
#define combo_actualSpeeds5_dr_5G_X4                       4
#define combo_actualSpeeds5_dr_6G_X4                       5
#define combo_actualSpeeds5_dr_10G_HiG                     6
#define combo_actualSpeeds5_dr_10G_CX4                     7
#define combo_actualSpeeds5_dr_12G_HiG                     8
#define combo_actualSpeeds5_dr_12p5G_X4                    9
#define combo_actualSpeeds5_dr_13G_X4                      10
#define combo_actualSpeeds5_dr_15G_X4                      11
#define combo_actualSpeeds5_dr_16G_X4                      12
#define combo_actualSpeeds5_dr_5G                          16
#define combo_actualSpeeds5_dr_6p4G                        17
#define combo_actualSpeeds5_dr_20G_X4                      18
#define combo_actualSpeeds5_dr_21G_X4                      19
#define combo_actualSpeeds5_dr_25G_X4                      20

/****************************************************************************
 * Enums: combo_actualSpeedsMisc1
 ***************************************************************************/
#define combo_actualSpeedsMisc1_dr_2500BRCM_X1             16
#define combo_actualSpeedsMisc1_dr_5000BRCM_X4             17
#define combo_actualSpeedsMisc1_dr_6000BRCM_X4             18
#define combo_actualSpeedsMisc1_dr_10GHiGig_X4             19
#define combo_actualSpeedsMisc1_dr_10GBASE_CX4             20
#define combo_actualSpeedsMisc1_dr_12GHiGig_X4             21
#define combo_actualSpeedsMisc1_dr_12p5GHiGig_X4           22
#define combo_actualSpeedsMisc1_dr_13GHiGig_X4             23
#define combo_actualSpeedsMisc1_dr_15GHiGig_X4             24
#define combo_actualSpeedsMisc1_dr_16GHiGig_X4             25
#define combo_actualSpeedsMisc1_dr_5000BRCM_X1             26
#define combo_actualSpeedsMisc1_dr_6363BRCM_X1             27
#define combo_actualSpeedsMisc1_dr_20GHiGig_X4             28
#define combo_actualSpeedsMisc1_dr_21GHiGig_X4             29
#define combo_actualSpeedsMisc1_dr_25p45GHiGig_X4          30

/****************************************************************************
 * Enums: combo_IndLaneModes
 ***************************************************************************/
#define combo_IndLaneModes_SWSDR_div2                      0
#define combo_IndLaneModes_SWSDR_div1                      1
#define combo_IndLaneModes_DWSDR_div2                      2
#define combo_IndLaneModes_DWSDR_div1                      3

/****************************************************************************
 * Enums: combo_prbsSelect
 ***************************************************************************/
#define combo_prbsSelect_prbs7                             0
#define combo_prbsSelect_prbs15                            1
#define combo_prbsSelect_prbs23                            2
#define combo_prbsSelect_prbs31                            3

/****************************************************************************
 * Enums: combo_vcoDivider
 ***************************************************************************/
#define combo_vcoDivider_div16                             0
#define combo_vcoDivider_div20                             1
#define combo_vcoDivider_div24                             2
#define combo_vcoDivider_div26                             3
#define combo_vcoDivider_div30                             4
#define combo_vcoDivider_div32                             5
#define combo_vcoDivider_div36                             6
#define combo_vcoDivider_div40                             7
#define combo_vcoDivider_div42                             8
#define combo_vcoDivider_div48                             9
#define combo_vcoDivider_div50                             10
#define combo_vcoDivider_div52                             11
#define combo_vcoDivider_div60                             12
#define combo_vcoDivider_div64                             13

/****************************************************************************
 * Enums: combo_refClkSelect
 ***************************************************************************/
#define combo_refClkSelect_clk_25MHz                       0
#define combo_refClkSelect_clk_100MHz                      1
#define combo_refClkSelect_clk_125MHz                      2
#define combo_refClkSelect_clk_156p25MHz                   3
#define combo_refClkSelect_clk_187p5MHz                    4

/****************************************************************************
 * Enums: ieee_operationModes
 ***************************************************************************/
#define ieee_operationModes_XGXS                           0
#define ieee_operationModes_XGXG_nCC                       1
#define ieee_operationModes_IndLane_OS5                    5
#define ieee_operationModes_Indlanes                       6
#define ieee_operationModes_PCI                            7
#define ieee_operationModes_XGXS_nLQ                       8
#define ieee_operationModes_XGXS_nLQnCC                    9
#define ieee_operationModes_PBypass                        10
#define ieee_operationModes_PBypass_nDSK                   11
#define ieee_operationModes_ComboCoreMode                  12
#define ieee_operationModes_Clocks_off                     15

/****************************************************************************
 * Enums: ieee_actualSpeeds4
 ***************************************************************************/
#define ieee_actualSpeeds4_dr_10M                          0
#define ieee_actualSpeeds4_dr_100M                         1
#define ieee_actualSpeeds4_dr_1G                           2
#define ieee_actualSpeeds4_dr_2p5G                         3
#define ieee_actualSpeeds4_dr_5G_X4                        4
#define ieee_actualSpeeds4_dr_6G_X4                        5
#define ieee_actualSpeeds4_dr_10G_HiG                      6
#define ieee_actualSpeeds4_dr_10G_CX4                      7
#define ieee_actualSpeeds4_dr_12G_HiG                      8
#define ieee_actualSpeeds4_dr_12p5G_X4                     9
#define ieee_actualSpeeds4_dr_13G_X4                       10
#define ieee_actualSpeeds4_dr_15G_X4                       11
#define ieee_actualSpeeds4_dr_16G_X4                       12

/****************************************************************************
 * Enums: ieee_actualSpeeds5
 ***************************************************************************/
#define ieee_actualSpeeds5_dr_10M                          0
#define ieee_actualSpeeds5_dr_100M                         1
#define ieee_actualSpeeds5_dr_1G                           2
#define ieee_actualSpeeds5_dr_2p5G                         3
#define ieee_actualSpeeds5_dr_5G_X4                        4
#define ieee_actualSpeeds5_dr_6G_X4                        5
#define ieee_actualSpeeds5_dr_10G_HiG                      6
#define ieee_actualSpeeds5_dr_10G_CX4                      7
#define ieee_actualSpeeds5_dr_12G_HiG                      8
#define ieee_actualSpeeds5_dr_12p5G_X4                     9
#define ieee_actualSpeeds5_dr_13G_X4                       10
#define ieee_actualSpeeds5_dr_15G_X4                       11
#define ieee_actualSpeeds5_dr_16G_X4                       12
#define ieee_actualSpeeds5_dr_5G                           16
#define ieee_actualSpeeds5_dr_6p4G                         17
#define ieee_actualSpeeds5_dr_20G_X4                       18
#define ieee_actualSpeeds5_dr_21G_X4                       19
#define ieee_actualSpeeds5_dr_25G_X4                       20

/****************************************************************************
 * Enums: ieee_actualSpeedsMisc1
 ***************************************************************************/
#define ieee_actualSpeedsMisc1_dr_2500BRCM_X1              16
#define ieee_actualSpeedsMisc1_dr_5000BRCM_X4              17
#define ieee_actualSpeedsMisc1_dr_6000BRCM_X4              18
#define ieee_actualSpeedsMisc1_dr_10GHiGig_X4              19
#define ieee_actualSpeedsMisc1_dr_10GBASE_CX4              20
#define ieee_actualSpeedsMisc1_dr_12GHiGig_X4              21
#define ieee_actualSpeedsMisc1_dr_12p5GHiGig_X4            22
#define ieee_actualSpeedsMisc1_dr_13GHiGig_X4              23
#define ieee_actualSpeedsMisc1_dr_15GHiGig_X4              24
#define ieee_actualSpeedsMisc1_dr_16GHiGig_X4              25
#define ieee_actualSpeedsMisc1_dr_5000BRCM_X1              26
#define ieee_actualSpeedsMisc1_dr_6363BRCM_X1              27
#define ieee_actualSpeedsMisc1_dr_20GHiGig_X4              28
#define ieee_actualSpeedsMisc1_dr_21GHiGig_X4              29
#define ieee_actualSpeedsMisc1_dr_25p45GHiGig_X4           30

/****************************************************************************
 * Enums: ieee_IndLaneModes
 ***************************************************************************/
#define ieee_IndLaneModes_SWSDR_div2                       0
#define ieee_IndLaneModes_SWSDR_div1                       1
#define ieee_IndLaneModes_DWSDR_div2                       2
#define ieee_IndLaneModes_DWSDR_div1                       3

/****************************************************************************
 * Enums: ieee_prbsSelect
 ***************************************************************************/
#define ieee_prbsSelect_prbs7                              0
#define ieee_prbsSelect_prbs15                             1
#define ieee_prbsSelect_prbs23                             2
#define ieee_prbsSelect_prbs31                             3

/****************************************************************************
 * Enums: ieee_vcoDivider
 ***************************************************************************/
#define ieee_vcoDivider_div16                              0
#define ieee_vcoDivider_div20                              1
#define ieee_vcoDivider_div24                              2
#define ieee_vcoDivider_div26                              3
#define ieee_vcoDivider_div30                              4
#define ieee_vcoDivider_div32                              5
#define ieee_vcoDivider_div36                              6
#define ieee_vcoDivider_div40                              7
#define ieee_vcoDivider_div42                              8
#define ieee_vcoDivider_div48                              9
#define ieee_vcoDivider_div50                              10
#define ieee_vcoDivider_div52                              11
#define ieee_vcoDivider_div60                              12
#define ieee_vcoDivider_div64                              13

/****************************************************************************
 * Enums: ieee_refClkSelect
 ***************************************************************************/
#define ieee_refClkSelect_clk_25MHz                        0
#define ieee_refClkSelect_clk_100MHz                       1
#define ieee_refClkSelect_clk_125MHz                       2
#define ieee_refClkSelect_clk_156p25MHz                    3
#define ieee_refClkSelect_clk_187p5MHz                     4

/****************************************************************************
 * Enums: xgxs_operationModes
 ***************************************************************************/
#define xgxs_operationModes_XGXS                           0
#define xgxs_operationModes_XGXG_nCC                       1
#define xgxs_operationModes_IndLane_OS5                    5
#define xgxs_operationModes_Indlanes                       6
#define xgxs_operationModes_PCI                            7
#define xgxs_operationModes_XGXS_nLQ                       8
#define xgxs_operationModes_XGXS_nLQnCC                    9
#define xgxs_operationModes_PBypass                        10
#define xgxs_operationModes_PBypass_nDSK                   11
#define xgxs_operationModes_ComboCoreMode                  12
#define xgxs_operationModes_Clocks_off                     15

/****************************************************************************
 * Enums: xgxs_actualSpeeds4
 ***************************************************************************/
#define xgxs_actualSpeeds4_dr_10M                          0
#define xgxs_actualSpeeds4_dr_100M                         1
#define xgxs_actualSpeeds4_dr_1G                           2
#define xgxs_actualSpeeds4_dr_2p5G                         3
#define xgxs_actualSpeeds4_dr_5G_X4                        4
#define xgxs_actualSpeeds4_dr_6G_X4                        5
#define xgxs_actualSpeeds4_dr_10G_HiG                      6
#define xgxs_actualSpeeds4_dr_10G_CX4                      7
#define xgxs_actualSpeeds4_dr_12G_HiG                      8
#define xgxs_actualSpeeds4_dr_12p5G_X4                     9
#define xgxs_actualSpeeds4_dr_13G_X4                       10
#define xgxs_actualSpeeds4_dr_15G_X4                       11
#define xgxs_actualSpeeds4_dr_16G_X4                       12

/****************************************************************************
 * Enums: xgxs_actualSpeeds5
 ***************************************************************************/
#define xgxs_actualSpeeds5_dr_10M                          0
#define xgxs_actualSpeeds5_dr_100M                         1
#define xgxs_actualSpeeds5_dr_1G                           2
#define xgxs_actualSpeeds5_dr_2p5G                         3
#define xgxs_actualSpeeds5_dr_5G_X4                        4
#define xgxs_actualSpeeds5_dr_6G_X4                        5
#define xgxs_actualSpeeds5_dr_10G_HiG                      6
#define xgxs_actualSpeeds5_dr_10G_CX4                      7
#define xgxs_actualSpeeds5_dr_12G_HiG                      8
#define xgxs_actualSpeeds5_dr_12p5G_X4                     9
#define xgxs_actualSpeeds5_dr_13G_X4                       10
#define xgxs_actualSpeeds5_dr_15G_X4                       11
#define xgxs_actualSpeeds5_dr_16G_X4                       12
#define xgxs_actualSpeeds5_dr_5G                           16
#define xgxs_actualSpeeds5_dr_6p4G                         17
#define xgxs_actualSpeeds5_dr_20G_X4                       18
#define xgxs_actualSpeeds5_dr_21G_X4                       19
#define xgxs_actualSpeeds5_dr_25G_X4                       20

/****************************************************************************
 * Enums: xgxs_actualSpeedsMisc1
 ***************************************************************************/
#define xgxs_actualSpeedsMisc1_dr_2500BRCM_X1              16
#define xgxs_actualSpeedsMisc1_dr_5000BRCM_X4              17
#define xgxs_actualSpeedsMisc1_dr_6000BRCM_X4              18
#define xgxs_actualSpeedsMisc1_dr_10GHiGig_X4              19
#define xgxs_actualSpeedsMisc1_dr_10GBASE_CX4              20
#define xgxs_actualSpeedsMisc1_dr_12GHiGig_X4              21
#define xgxs_actualSpeedsMisc1_dr_12p5GHiGig_X4            22
#define xgxs_actualSpeedsMisc1_dr_13GHiGig_X4              23
#define xgxs_actualSpeedsMisc1_dr_15GHiGig_X4              24
#define xgxs_actualSpeedsMisc1_dr_16GHiGig_X4              25
#define xgxs_actualSpeedsMisc1_dr_5000BRCM_X1              26
#define xgxs_actualSpeedsMisc1_dr_6363BRCM_X1              27
#define xgxs_actualSpeedsMisc1_dr_20GHiGig_X4              28
#define xgxs_actualSpeedsMisc1_dr_21GHiGig_X4              29
#define xgxs_actualSpeedsMisc1_dr_25p45GHiGig_X4           30

/****************************************************************************
 * Enums: xgxs_IndLaneModes
 ***************************************************************************/
#define xgxs_IndLaneModes_SWSDR_div2                       0
#define xgxs_IndLaneModes_SWSDR_div1                       1
#define xgxs_IndLaneModes_DWSDR_div2                       2
#define xgxs_IndLaneModes_DWSDR_div1                       3

/****************************************************************************
 * Enums: xgxs_prbsSelect
 ***************************************************************************/
#define xgxs_prbsSelect_prbs7                              0
#define xgxs_prbsSelect_prbs15                             1
#define xgxs_prbsSelect_prbs23                             2
#define xgxs_prbsSelect_prbs31                             3

/****************************************************************************
 * Enums: xgxs_vcoDivider
 ***************************************************************************/
#define xgxs_vcoDivider_div16                              0
#define xgxs_vcoDivider_div20                              1
#define xgxs_vcoDivider_div24                              2
#define xgxs_vcoDivider_div26                              3
#define xgxs_vcoDivider_div30                              4
#define xgxs_vcoDivider_div32                              5
#define xgxs_vcoDivider_div36                              6
#define xgxs_vcoDivider_div40                              7
#define xgxs_vcoDivider_div42                              8
#define xgxs_vcoDivider_div48                              9
#define xgxs_vcoDivider_div50                              10
#define xgxs_vcoDivider_div52                              11
#define xgxs_vcoDivider_div60                              12
#define xgxs_vcoDivider_div64                              13

/****************************************************************************
 * Enums: xgxs_refClkSelect
 ***************************************************************************/
#define xgxs_refClkSelect_clk_25MHz                        0
#define xgxs_refClkSelect_clk_100MHz                       1
#define xgxs_refClkSelect_clk_125MHz                       2
#define xgxs_refClkSelect_clk_156p25MHz                    3
#define xgxs_refClkSelect_clk_187p5MHz                     4

/****************************************************************************
 * Hypercore_IEEE_CL22_ieee0Blk
 ***************************************************************************/

/* IEEE MII control register */
#define READ_HL65_IEEE0BLK_MIICNTLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00000000, (_val))
#define WRITE_HL65_IEEE0BLK_MIICNTLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000000, (_val))
#define MODIFY_HL65_IEEE0BLK_MIICNTLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000000, (_val), (_mask))

/* IEEE MII status register */
#define READ_HL65_IEEE0BLK_MIISTATr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00000001, (_val))
#define WRITE_HL65_IEEE0BLK_MIISTATr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000001, (_val))
#define MODIFY_HL65_IEEE0BLK_MIISTATr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000001, (_val), (_mask))

/* IEEE phy ID LSByte register */
#define READ_HL65_IEEE0BLK_ID1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00000002, (_val))
#define WRITE_HL65_IEEE0BLK_ID1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000002, (_val))
#define MODIFY_HL65_IEEE0BLK_ID1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000002, (_val), (_mask))

/* IEEE phy ID MSByte register */
#define READ_HL65_IEEE0BLK_ID2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00000003, (_val))
#define WRITE_HL65_IEEE0BLK_ID2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000003, (_val))
#define MODIFY_HL65_IEEE0BLK_ID2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000003, (_val), (_mask))

/* IEEE auto-negotiation advertised abilities register */
#define READ_HL65_IEEE0BLK_AUTONEGADVr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00000004, (_val))
#define WRITE_HL65_IEEE0BLK_AUTONEGADVr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000004, (_val))
#define MODIFY_HL65_IEEE0BLK_AUTONEGADVr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000004, (_val), (_mask))

/* IEEE auto-negotiation link partner abilities register */
#define READ_HL65_IEEE0BLK_AUTONEGLPABILr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00000005, (_val))
#define WRITE_HL65_IEEE0BLK_AUTONEGLPABILr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000005, (_val))
#define MODIFY_HL65_IEEE0BLK_AUTONEGLPABILr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000005, (_val), (_mask))

/* IEEE auto-negotiation expansion register */
#define READ_HL65_IEEE0BLK_AUTONEGEXPr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00000006, (_val))
#define WRITE_HL65_IEEE0BLK_AUTONEGEXPr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000006, (_val))
#define MODIFY_HL65_IEEE0BLK_AUTONEGEXPr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000006, (_val), (_mask))

/* IEEE auto-negotiation next page register */
#define READ_HL65_IEEE0BLK_AUTONEGNPr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00000007, (_val))
#define WRITE_HL65_IEEE0BLK_AUTONEGNPr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000007, (_val))
#define MODIFY_HL65_IEEE0BLK_AUTONEGNPr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000007, (_val), (_mask))

/* IEEE auto-negotiation link partner next page register */
#define READ_HL65_IEEE0BLK_AUTONEGLPABIL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00000008, (_val))
#define WRITE_HL65_IEEE0BLK_AUTONEGLPABIL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000008, (_val))
#define MODIFY_HL65_IEEE0BLK_AUTONEGLPABIL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000008, (_val), (_mask))

/* IEEE MII extended status register */
#define READ_HL65_IEEE0BLK_MIIEXTSTATr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000000f, (_val))
#define WRITE_HL65_IEEE0BLK_MIIEXTSTATr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000000f, (_val))
#define MODIFY_HL65_IEEE0BLK_MIIEXTSTATr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000000f, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_XgxsBlk0
 ***************************************************************************/

/* XGXS control register */
#define READ_HL65_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008000, (_val))
#define WRITE_HL65_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008000, (_val))
#define MODIFY_HL65_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008000, (_val), (_mask))

/* XGXS status register */
#define READ_HL65_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008001, (_val))
#define WRITE_HL65_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008001, (_val))
#define MODIFY_HL65_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008001, (_val), (_mask))

/* XGMII idle control character register */
#define READ_HL65_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008002, (_val))
#define WRITE_HL65_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008002, (_val))
#define MODIFY_HL65_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008002, (_val), (_mask))

/* XGMII sync control character register */
#define READ_HL65_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008003, (_val))
#define WRITE_HL65_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008003, (_val))
#define MODIFY_HL65_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008003, (_val), (_mask))

/* XGMII skip control character register */
#define READ_HL65_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008004, (_val))
#define WRITE_HL65_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008004, (_val))
#define MODIFY_HL65_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008004, (_val), (_mask))

/* XGMII sop & eop control character register */
#define READ_HL65_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008005, (_val))
#define WRITE_HL65_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008005, (_val))
#define MODIFY_HL65_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008005, (_val), (_mask))

/* XGMII alignment & eror control character register */
#define READ_HL65_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008006, (_val))
#define WRITE_HL65_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008006, (_val))
#define MODIFY_HL65_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008006, (_val), (_mask))

/* XGMII receive control register */
#define READ_HL65_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008007, (_val))
#define WRITE_HL65_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008007, (_val))
#define MODIFY_HL65_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008007, (_val), (_mask))

/* XGMII transmit control register */
#define READ_HL65_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008008, (_val))
#define WRITE_HL65_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008008, (_val))
#define MODIFY_HL65_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008008, (_val), (_mask))

/* XGMII ||A|| minimum swap spacing */
#define READ_HL65_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008009, (_val))
#define WRITE_HL65_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008009, (_val))
#define MODIFY_HL65_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008009, (_val), (_mask))

/* LSS information byte register */
#define READ_HL65_XGXSBLK0_LSSLSIDr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000800a, (_val))
#define WRITE_HL65_XGXSBLK0_LSSLSIDr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000800a, (_val))
#define MODIFY_HL65_XGXSBLK0_LSSLSIDr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800a, (_val), (_mask))

/* LSS transmit information byte register */
#define READ_HL65_XGXSBLK0_LSSTINFOr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000800b, (_val))
#define WRITE_HL65_XGXSBLK0_LSSTINFOr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000800b, (_val))
#define MODIFY_HL65_XGXSBLK0_LSSTINFOr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800b, (_val), (_mask))

/* LSS receive information byte register */
#define READ_HL65_XGXSBLK0_LSSRINFOr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000800c, (_val))
#define WRITE_HL65_XGXSBLK0_LSSRINFOr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000800c, (_val))
#define MODIFY_HL65_XGXSBLK0_LSSRINFOr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800c, (_val), (_mask))

/* MMD select register */
#define READ_HL65_XGXSBLK0_MMDSELECTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000800d, (_val))
#define WRITE_HL65_XGXSBLK0_MMDSELECTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000800d, (_val))
#define MODIFY_HL65_XGXSBLK0_MMDSELECTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800d, (_val), (_mask))

/* Miscellaneous control 1 register */
#define READ_HL65_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000800e, (_val))
#define WRITE_HL65_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000800e, (_val))
#define MODIFY_HL65_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800e, (_val), (_mask))

/* Block Address register */
#define READ_HL65_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000800f, (_val))
#define WRITE_HL65_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000800f, (_val))
#define MODIFY_HL65_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800f, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_XgxsBlk1
 ***************************************************************************/

/* Lane deskew register */
#define READ_HL65_XGXSBLK1_DESKEWr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008010, (_val))
#define WRITE_HL65_XGXSBLK1_DESKEWr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008010, (_val))
#define MODIFY_HL65_XGXSBLK1_DESKEWr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008010, (_val), (_mask))

/* Link ||A|| column timeout value register */
#define READ_HL65_XGXSBLK1_LINKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008011, (_val))
#define WRITE_HL65_XGXSBLK1_LINKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008011, (_val))
#define MODIFY_HL65_XGXSBLK1_LINKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008011, (_val), (_mask))

/* Receive test control register */
#define READ_HL65_XGXSBLK1_TESTRXr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008012, (_val))
#define WRITE_HL65_XGXSBLK1_TESTRXr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008012, (_val))
#define MODIFY_HL65_XGXSBLK1_TESTRXr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008012, (_val), (_mask))

/* Transmit test control register */
#define READ_HL65_XGXSBLK1_TESTTXr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008013, (_val))
#define WRITE_HL65_XGXSBLK1_TESTTXr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008013, (_val))
#define MODIFY_HL65_XGXSBLK1_TESTTXr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008013, (_val), (_mask))

/* XGXS test control register */
#define READ_HL65_XGXSBLK1_TESTXGr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008014, (_val))
#define WRITE_HL65_XGXSBLK1_TESTXGr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008014, (_val))
#define MODIFY_HL65_XGXSBLK1_TESTXGr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008014, (_val), (_mask))

/* Lane control 0 register */
#define READ_HL65_XGXSBLK1_LANECTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008015, (_val))
#define WRITE_HL65_XGXSBLK1_LANECTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008015, (_val))
#define MODIFY_HL65_XGXSBLK1_LANECTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008015, (_val), (_mask))

/* Lane control 1 register */
#define READ_HL65_XGXSBLK1_LANECTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008016, (_val))
#define WRITE_HL65_XGXSBLK1_LANECTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008016, (_val))
#define MODIFY_HL65_XGXSBLK1_LANECTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008016, (_val), (_mask))

/* Lane control 2 register */
#define READ_HL65_XGXSBLK1_LANECTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008017, (_val))
#define WRITE_HL65_XGXSBLK1_LANECTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008017, (_val))
#define MODIFY_HL65_XGXSBLK1_LANECTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008017, (_val), (_mask))

/* Lane control 3 register */
#define READ_HL65_XGXSBLK1_LANECTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008018, (_val))
#define WRITE_HL65_XGXSBLK1_LANECTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008018, (_val))
#define MODIFY_HL65_XGXSBLK1_LANECTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008018, (_val), (_mask))

/* Lane PRBS control register */
#define READ_HL65_XGXSBLK1_LANEPRBSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008019, (_val))
#define WRITE_HL65_XGXSBLK1_LANEPRBSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008019, (_val))
#define MODIFY_HL65_XGXSBLK1_LANEPRBSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008019, (_val), (_mask))

/* Lane test control register */
#define READ_HL65_XGXSBLK1_LANETESTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000801a, (_val))
#define WRITE_HL65_XGXSBLK1_LANETESTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000801a, (_val))
#define MODIFY_HL65_XGXSBLK1_LANETESTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801a, (_val), (_mask))

/* LSS, ||Q|| column count register */
#define READ_HL65_XGXSBLK1_LSSREVNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000801b, (_val))
#define WRITE_HL65_XGXSBLK1_LSSREVNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000801b, (_val))
#define MODIFY_HL65_XGXSBLK1_LSSREVNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801b, (_val), (_mask))

/* Lane deskew event count register */
#define READ_HL65_XGXSBLK1_DSKEVNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000801c, (_val))
#define WRITE_HL65_XGXSBLK1_DSKEVNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000801c, (_val))
#define MODIFY_HL65_XGXSBLK1_DSKEVNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801c, (_val), (_mask))

/* Bad ||A|| column count register */
#define READ_HL65_XGXSBLK1_AERREVNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000801d, (_val))
#define WRITE_HL65_XGXSBLK1_AERREVNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000801d, (_val))
#define MODIFY_HL65_XGXSBLK1_AERREVNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801d, (_val), (_mask))

/* Clock compensation event count register */
#define READ_HL65_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000801e, (_val))
#define WRITE_HL65_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000801e, (_val))
#define MODIFY_HL65_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_TxBert
 ***************************************************************************/

/* Tx Bert control register */
#define READ_HL65_TXBERT_TXBERTCTRLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008020, (_val))
#define WRITE_HL65_TXBERT_TXBERTCTRLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008020, (_val))
#define MODIFY_HL65_TXBERT_TXBERTCTRLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008020, (_val), (_mask))

/* Tx Bert SOP, EOP definition register */
#define READ_HL65_TXBERT_TXBERTSOPEOPr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008021, (_val))
#define WRITE_HL65_TXBERT_TXBERTSOPEOPr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008021, (_val))
#define MODIFY_HL65_TXBERT_TXBERTSOPEOPr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008021, (_val), (_mask))

/* Packet size configuration 0 register */
#define READ_HL65_TXBERT_TXBERTSIZE0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008022, (_val))
#define WRITE_HL65_TXBERT_TXBERTSIZE0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008022, (_val))
#define MODIFY_HL65_TXBERT_TXBERTSIZE0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008022, (_val), (_mask))

/* Packet size configuration 1 register */
#define READ_HL65_TXBERT_TXBERTSIZE1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008023, (_val))
#define WRITE_HL65_TXBERT_TXBERTSIZE1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008023, (_val))
#define MODIFY_HL65_TXBERT_TXBERTSIZE1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008023, (_val), (_mask))

/* Packet size configuration 2 register */
#define READ_HL65_TXBERT_TXBERTSIZE2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008024, (_val))
#define WRITE_HL65_TXBERT_TXBERTSIZE2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008024, (_val))
#define MODIFY_HL65_TXBERT_TXBERTSIZE2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008024, (_val), (_mask))

/* IPG 0 definition register */
#define READ_HL65_TXBERT_TXBERTIPG0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008025, (_val))
#define WRITE_HL65_TXBERT_TXBERTIPG0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008025, (_val))
#define MODIFY_HL65_TXBERT_TXBERTIPG0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008025, (_val), (_mask))

/* IPG 1 definition register */
#define READ_HL65_TXBERT_TXBERTIPG1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008026, (_val))
#define WRITE_HL65_TXBERT_TXBERTIPG1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008026, (_val))
#define MODIFY_HL65_TXBERT_TXBERTIPG1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008026, (_val), (_mask))

/* Transmitted byte count upper 16 bits register */
#define READ_HL65_TXBERT_TXBERTBYTEUr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008027, (_val))
#define WRITE_HL65_TXBERT_TXBERTBYTEUr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008027, (_val))
#define MODIFY_HL65_TXBERT_TXBERTBYTEUr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008027, (_val), (_mask))

/* Transmitted byte count lower 16 bits register */
#define READ_HL65_TXBERT_TXBERTBYTELr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008028, (_val))
#define WRITE_HL65_TXBERT_TXBERTBYTELr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008028, (_val))
#define MODIFY_HL65_TXBERT_TXBERTBYTELr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008028, (_val), (_mask))

/* Transmitted packet count upper 16 bits register */
#define READ_HL65_TXBERT_TXBERTPACKETUr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008029, (_val))
#define WRITE_HL65_TXBERT_TXBERTPACKETUr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008029, (_val))
#define MODIFY_HL65_TXBERT_TXBERTPACKETUr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008029, (_val), (_mask))

/* Transmitted packet count lower 16 bits register */
#define READ_HL65_TXBERT_TXBERTPACKETLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000802a, (_val))
#define WRITE_HL65_TXBERT_TXBERTPACKETLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000802a, (_val))
#define MODIFY_HL65_TXBERT_TXBERTPACKETLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000802a, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_RxBert
 ***************************************************************************/

/* Rx Bert control register */
#define READ_HL65_RXBERT_RXBERTCTRLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008030, (_val))
#define WRITE_HL65_RXBERT_RXBERTCTRLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008030, (_val))
#define MODIFY_HL65_RXBERT_RXBERTCTRLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008030, (_val), (_mask))

/* Rx Bert SOP, EOP definition register */
#define READ_HL65_RXBERT_RXBERTSOPEOPr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008031, (_val))
#define WRITE_HL65_RXBERT_RXBERTSOPEOPr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008031, (_val))
#define MODIFY_HL65_RXBERT_RXBERTSOPEOPr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008031, (_val), (_mask))

/* Received byte count upper 16 bits register */
#define READ_HL65_RXBERT_RXBERTBYTEUr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008037, (_val))
#define WRITE_HL65_RXBERT_RXBERTBYTEUr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008037, (_val))
#define MODIFY_HL65_RXBERT_RXBERTBYTEUr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008037, (_val), (_mask))

/* Received bytes count lower 16 bits register */
#define READ_HL65_RXBERT_RXBERTBYTELr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008038, (_val))
#define WRITE_HL65_RXBERT_RXBERTBYTELr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008038, (_val))
#define MODIFY_HL65_RXBERT_RXBERTBYTELr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008038, (_val), (_mask))

/* Received packet count upper 16 bits register */
#define READ_HL65_RXBERT_RXBERTPACKETUr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008039, (_val))
#define WRITE_HL65_RXBERT_RXBERTPACKETUr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008039, (_val))
#define MODIFY_HL65_RXBERT_RXBERTPACKETUr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008039, (_val), (_mask))

/* Received packet count lower 16 bits register */
#define READ_HL65_RXBERT_RXBERTPACKETLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000803a, (_val))
#define WRITE_HL65_RXBERT_RXBERTPACKETLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000803a, (_val))
#define MODIFY_HL65_RXBERT_RXBERTPACKETLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803a, (_val), (_mask))

/* Received bits error count */
#define READ_HL65_RXBERT_RXBERTBITERRr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000803b, (_val))
#define WRITE_HL65_RXBERT_RXBERTBITERRr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000803b, (_val))
#define MODIFY_HL65_RXBERT_RXBERTBITERRr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803b, (_val), (_mask))

/* Received bytes error count */
#define READ_HL65_RXBERT_RXBERTBYTEERRr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000803c, (_val))
#define WRITE_HL65_RXBERT_RXBERTBYTEERRr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000803c, (_val))
#define MODIFY_HL65_RXBERT_RXBERTBYTEERRr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803c, (_val), (_mask))

/* Received packets error count */
#define READ_HL65_RXBERT_RXBERTPKTERRr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000803d, (_val))
#define WRITE_HL65_RXBERT_RXBERTPKTERRr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000803d, (_val))
#define MODIFY_HL65_RXBERT_RXBERTPKTERRr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803d, (_val), (_mask))

/* Receive Status */
#define READ_HL65_RXBERT_RXBERTSTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000803e, (_val))
#define WRITE_HL65_RXBERT_RXBERTSTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000803e, (_val))
#define MODIFY_HL65_RXBERT_RXBERTSTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_TxPll
 ***************************************************************************/

/* PLL status register */
#define READ_HL65_TXPLL_ANAPLLSTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008050, (_val))
#define WRITE_HL65_TXPLL_ANAPLLSTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008050, (_val))
#define MODIFY_HL65_TXPLL_ANAPLLSTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008050, (_val), (_mask))

/* PLL control register */
#define READ_HL65_TXPLL_ANAPLLCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008051, (_val))
#define WRITE_HL65_TXPLL_ANAPLLCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008051, (_val))
#define MODIFY_HL65_TXPLL_ANAPLLCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008051, (_val), (_mask))

/* PLL start up state machine vco timers */
#define READ_HL65_TXPLL_ANAPLLTIMER1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008052, (_val))
#define WRITE_HL65_TXPLL_ANAPLLTIMER1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008052, (_val))
#define MODIFY_HL65_TXPLL_ANAPLLTIMER1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008052, (_val), (_mask))

/* PLL start up state machine retry timer */
#define READ_HL65_TXPLL_ANAPLLTIMER2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008053, (_val))
#define WRITE_HL65_TXPLL_ANAPLLTIMER2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008053, (_val))
#define MODIFY_HL65_TXPLL_ANAPLLTIMER2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008053, (_val), (_mask))

/* PLL start up state machine freq. detect timer */
#define READ_HL65_TXPLL_ANAPLLTIMER3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008054, (_val))
#define WRITE_HL65_TXPLL_ANAPLLTIMER3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008054, (_val))
#define MODIFY_HL65_TXPLL_ANAPLLTIMER3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008054, (_val), (_mask))

/* PLL vco range control state machine */
#define READ_HL65_TXPLL_ANACAPCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008055, (_val))
#define WRITE_HL65_TXPLL_ANACAPCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008055, (_val))
#define MODIFY_HL65_TXPLL_ANACAPCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008055, (_val), (_mask))

/* Frequency detector control */
#define READ_HL65_TXPLL_ANAFREQDETCNTRr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008057, (_val))
#define WRITE_HL65_TXPLL_ANAFREQDETCNTRr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008057, (_val))
#define MODIFY_HL65_TXPLL_ANAFREQDETCNTRr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008057, (_val), (_mask))

/* PLL analog status */
#define READ_HL65_TXPLL_ANAPLLASTATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008058, (_val))
#define WRITE_HL65_TXPLL_ANAPLLASTATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008058, (_val))
#define MODIFY_HL65_TXPLL_ANAPLLASTATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008058, (_val), (_mask))

/* PLL analog controls */
#define READ_HL65_TXPLL_ANAPLLACONTROL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000805a, (_val))
#define WRITE_HL65_TXPLL_ANAPLLACONTROL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000805a, (_val))
#define MODIFY_HL65_TXPLL_ANAPLLACONTROL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805a, (_val), (_mask))

/* PLL analog controls */
#define READ_HL65_TXPLL_ANAPLLACONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000805b, (_val))
#define WRITE_HL65_TXPLL_ANAPLLACONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000805b, (_val))
#define MODIFY_HL65_TXPLL_ANAPLLACONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805b, (_val), (_mask))

/* PLL analog controls */
#define READ_HL65_TXPLL_ANAPLLACONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000805c, (_val))
#define WRITE_HL65_TXPLL_ANAPLLACONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000805c, (_val))
#define MODIFY_HL65_TXPLL_ANAPLLACONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805c, (_val), (_mask))

/* PLL analog controls */
#define READ_HL65_TXPLL_ANAPLLACONTROL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000805d, (_val))
#define WRITE_HL65_TXPLL_ANAPLLACONTROL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000805d, (_val))
#define MODIFY_HL65_TXPLL_ANAPLLACONTROL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805d, (_val), (_mask))

/* PLL analog controls */
#define READ_HL65_TXPLL_ANAPLLACONTROL4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000805e, (_val))
#define WRITE_HL65_TXPLL_ANAPLLACONTROL4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000805e, (_val))
#define MODIFY_HL65_TXPLL_ANAPLLACONTROL4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Tx0
 ***************************************************************************/

/* Tx analog status 0 register */
#define READ_HL65_TX0_ANATXASTATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008060, (_val))
#define WRITE_HL65_TX0_ANATXASTATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008060, (_val))
#define MODIFY_HL65_TX0_ANATXASTATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008060, (_val), (_mask))

/* Tx analog control 0 register */
#define READ_HL65_TX0_ANATXACONTROL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008061, (_val))
#define WRITE_HL65_TX0_ANATXACONTROL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008061, (_val))
#define MODIFY_HL65_TX0_ANATXACONTROL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008061, (_val), (_mask))

/* Tx test mux data 0 register */
#define READ_HL65_TX0_ANATXMDATA0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008062, (_val))
#define WRITE_HL65_TX0_ANATXMDATA0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008062, (_val))
#define MODIFY_HL65_TX0_ANATXMDATA0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008062, (_val), (_mask))

/* Tx test mux data 1 register */
#define READ_HL65_TX0_ANATXMDATA1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008063, (_val))
#define WRITE_HL65_TX0_ANATXMDATA1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008063, (_val))
#define MODIFY_HL65_TX0_ANATXMDATA1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008063, (_val), (_mask))

/* Tx analog status 1 register */
#define READ_HL65_TX0_ANATXASTATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008064, (_val))
#define WRITE_HL65_TX0_ANATXASTATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008064, (_val))
#define MODIFY_HL65_TX0_ANATXASTATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008064, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_HL65_TX0_ANATXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008065, (_val))
#define WRITE_HL65_TX0_ANATXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008065, (_val))
#define MODIFY_HL65_TX0_ANATXACONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008065, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_HL65_TX0_ANATXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008066, (_val))
#define WRITE_HL65_TX0_ANATXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008066, (_val))
#define MODIFY_HL65_TX0_ANATXACONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008066, (_val), (_mask))

/* Tx reserved OS analog control register */
#define READ_HL65_TX0_TX_OS_DRIVERr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008067, (_val))
#define WRITE_HL65_TX0_TX_OS_DRIVERr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008067, (_val))
#define MODIFY_HL65_TX0_TX_OS_DRIVERr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008067, (_val), (_mask))

/* Tx reserved BR analog control register */
#define READ_HL65_TX0_TX_BR_DRIVERr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008068, (_val))
#define WRITE_HL65_TX0_TX_BR_DRIVERr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008068, (_val))
#define MODIFY_HL65_TX0_TX_BR_DRIVERr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008068, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Tx1
 ***************************************************************************/

/* Tx analog status 0 register */
#define READ_HL65_TX1_ANATXASTATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008070, (_val))
#define WRITE_HL65_TX1_ANATXASTATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008070, (_val))
#define MODIFY_HL65_TX1_ANATXASTATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008070, (_val), (_mask))

/* Tx analog control 0 register */
#define READ_HL65_TX1_ANATXACONTROL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008071, (_val))
#define WRITE_HL65_TX1_ANATXACONTROL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008071, (_val))
#define MODIFY_HL65_TX1_ANATXACONTROL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008071, (_val), (_mask))

/* Tx test mux data 0 register */
#define READ_HL65_TX1_ANATXMDATA0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008072, (_val))
#define WRITE_HL65_TX1_ANATXMDATA0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008072, (_val))
#define MODIFY_HL65_TX1_ANATXMDATA0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008072, (_val), (_mask))

/* Tx test mux data 1 register */
#define READ_HL65_TX1_ANATXMDATA1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008073, (_val))
#define WRITE_HL65_TX1_ANATXMDATA1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008073, (_val))
#define MODIFY_HL65_TX1_ANATXMDATA1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008073, (_val), (_mask))

/* Tx analog status 1 register */
#define READ_HL65_TX1_ANATXASTATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008074, (_val))
#define WRITE_HL65_TX1_ANATXASTATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008074, (_val))
#define MODIFY_HL65_TX1_ANATXASTATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008074, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_HL65_TX1_ANATXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008075, (_val))
#define WRITE_HL65_TX1_ANATXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008075, (_val))
#define MODIFY_HL65_TX1_ANATXACONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008075, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_HL65_TX1_ANATXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008076, (_val))
#define WRITE_HL65_TX1_ANATXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008076, (_val))
#define MODIFY_HL65_TX1_ANATXACONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008076, (_val), (_mask))

/* Tx reserved OS analog control register */
#define READ_HL65_TX1_TX_OS_DRIVERr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008077, (_val))
#define WRITE_HL65_TX1_TX_OS_DRIVERr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008077, (_val))
#define MODIFY_HL65_TX1_TX_OS_DRIVERr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008077, (_val), (_mask))

/* Tx reserved BR analog control register */
#define READ_HL65_TX1_TX_BR_DRIVERr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008078, (_val))
#define WRITE_HL65_TX1_TX_BR_DRIVERr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008078, (_val))
#define MODIFY_HL65_TX1_TX_BR_DRIVERr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008078, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Tx2
 ***************************************************************************/

/* Tx analog status 0 register */
#define READ_HL65_TX2_ANATXASTATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008080, (_val))
#define WRITE_HL65_TX2_ANATXASTATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008080, (_val))
#define MODIFY_HL65_TX2_ANATXASTATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008080, (_val), (_mask))

/* Tx analog control 0 register */
#define READ_HL65_TX2_ANATXACONTROL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008081, (_val))
#define WRITE_HL65_TX2_ANATXACONTROL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008081, (_val))
#define MODIFY_HL65_TX2_ANATXACONTROL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008081, (_val), (_mask))

/* Tx test mux data 0 register */
#define READ_HL65_TX2_ANATXMDATA0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008082, (_val))
#define WRITE_HL65_TX2_ANATXMDATA0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008082, (_val))
#define MODIFY_HL65_TX2_ANATXMDATA0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008082, (_val), (_mask))

/* Tx test mux data 1 register */
#define READ_HL65_TX2_ANATXMDATA1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008083, (_val))
#define WRITE_HL65_TX2_ANATXMDATA1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008083, (_val))
#define MODIFY_HL65_TX2_ANATXMDATA1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008083, (_val), (_mask))

/* Tx analog status 1 register */
#define READ_HL65_TX2_ANATXASTATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008084, (_val))
#define WRITE_HL65_TX2_ANATXASTATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008084, (_val))
#define MODIFY_HL65_TX2_ANATXASTATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008084, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_HL65_TX2_ANATXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008085, (_val))
#define WRITE_HL65_TX2_ANATXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008085, (_val))
#define MODIFY_HL65_TX2_ANATXACONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008085, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_HL65_TX2_ANATXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008086, (_val))
#define WRITE_HL65_TX2_ANATXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008086, (_val))
#define MODIFY_HL65_TX2_ANATXACONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008086, (_val), (_mask))

/* Tx reserved OS analog control register */
#define READ_HL65_TX2_TX_OS_DRIVERr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008087, (_val))
#define WRITE_HL65_TX2_TX_OS_DRIVERr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008087, (_val))
#define MODIFY_HL65_TX2_TX_OS_DRIVERr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008087, (_val), (_mask))

/* Tx reserved BR analog control register */
#define READ_HL65_TX2_TX_BR_DRIVERr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008088, (_val))
#define WRITE_HL65_TX2_TX_BR_DRIVERr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008088, (_val))
#define MODIFY_HL65_TX2_TX_BR_DRIVERr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008088, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Tx3
 ***************************************************************************/

/* Tx analog status 0 register */
#define READ_HL65_TX3_ANATXASTATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008090, (_val))
#define WRITE_HL65_TX3_ANATXASTATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008090, (_val))
#define MODIFY_HL65_TX3_ANATXASTATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008090, (_val), (_mask))

/* Tx analog control 0 register */
#define READ_HL65_TX3_ANATXACONTROL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008091, (_val))
#define WRITE_HL65_TX3_ANATXACONTROL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008091, (_val))
#define MODIFY_HL65_TX3_ANATXACONTROL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008091, (_val), (_mask))

/* Tx test mux data 0 register */
#define READ_HL65_TX3_ANATXMDATA0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008092, (_val))
#define WRITE_HL65_TX3_ANATXMDATA0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008092, (_val))
#define MODIFY_HL65_TX3_ANATXMDATA0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008092, (_val), (_mask))

/* Tx test mux data 1 register */
#define READ_HL65_TX3_ANATXMDATA1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008093, (_val))
#define WRITE_HL65_TX3_ANATXMDATA1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008093, (_val))
#define MODIFY_HL65_TX3_ANATXMDATA1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008093, (_val), (_mask))

/* Tx analog status 1 register */
#define READ_HL65_TX3_ANATXASTATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008094, (_val))
#define WRITE_HL65_TX3_ANATXASTATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008094, (_val))
#define MODIFY_HL65_TX3_ANATXASTATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008094, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_HL65_TX3_ANATXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008095, (_val))
#define WRITE_HL65_TX3_ANATXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008095, (_val))
#define MODIFY_HL65_TX3_ANATXACONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008095, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_HL65_TX3_ANATXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008096, (_val))
#define WRITE_HL65_TX3_ANATXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008096, (_val))
#define MODIFY_HL65_TX3_ANATXACONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008096, (_val), (_mask))

/* Tx reserved OS analog control register */
#define READ_HL65_TX3_TX_OS_DRIVERr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008097, (_val))
#define WRITE_HL65_TX3_TX_OS_DRIVERr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008097, (_val))
#define MODIFY_HL65_TX3_TX_OS_DRIVERr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008097, (_val), (_mask))

/* Tx reserved BR analog control register */
#define READ_HL65_TX3_TX_BR_DRIVERr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008098, (_val))
#define WRITE_HL65_TX3_TX_BR_DRIVERr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008098, (_val))
#define MODIFY_HL65_TX3_TX_BR_DRIVERr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008098, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_TxB
 ***************************************************************************/

/* Tx analog status 0 register */
#define READ_HL65_TXB_ANATXASTATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a0, (_val))
#define WRITE_HL65_TXB_ANATXASTATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a0, (_val))
#define MODIFY_HL65_TXB_ANATXASTATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a0, (_val), (_mask))

/* Tx analog control 0 register */
#define READ_HL65_TXB_ANATXACONTROL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a1, (_val))
#define WRITE_HL65_TXB_ANATXACONTROL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a1, (_val))
#define MODIFY_HL65_TXB_ANATXACONTROL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a1, (_val), (_mask))

/* Tx test mux data 0 register */
#define READ_HL65_TXB_ANATXMDATA0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a2, (_val))
#define WRITE_HL65_TXB_ANATXMDATA0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a2, (_val))
#define MODIFY_HL65_TXB_ANATXMDATA0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a2, (_val), (_mask))

/* Tx test mux data 1 register */
#define READ_HL65_TXB_ANATXMDATA1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a3, (_val))
#define WRITE_HL65_TXB_ANATXMDATA1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a3, (_val))
#define MODIFY_HL65_TXB_ANATXMDATA1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a3, (_val), (_mask))

/* Tx analog status 1 register */
#define READ_HL65_TXB_ANATXASTATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a4, (_val))
#define WRITE_HL65_TXB_ANATXASTATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a4, (_val))
#define MODIFY_HL65_TXB_ANATXASTATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a4, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_HL65_TXB_ANATXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a5, (_val))
#define WRITE_HL65_TXB_ANATXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a5, (_val))
#define MODIFY_HL65_TXB_ANATXACONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a5, (_val), (_mask))

/* Tx reserved analog control register */
#define READ_HL65_TXB_ANATXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a6, (_val))
#define WRITE_HL65_TXB_ANATXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a6, (_val))
#define MODIFY_HL65_TXB_ANATXACONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a6, (_val), (_mask))

/* Tx reserved OS analog control register */
#define READ_HL65_TXB_TX_OS_DRIVERr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a7, (_val))
#define WRITE_HL65_TXB_TX_OS_DRIVERr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a7, (_val))
#define MODIFY_HL65_TXB_TX_OS_DRIVERr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a7, (_val), (_mask))

/* Tx reserved BR analog control register */
#define READ_HL65_TXB_TX_BR_DRIVERr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a8, (_val))
#define WRITE_HL65_TXB_TX_BR_DRIVERr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a8, (_val))
#define MODIFY_HL65_TXB_TX_BR_DRIVERr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a8, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Rx0
 ***************************************************************************/

/* Rx lane status register */
#define READ_HL65_RX0_ANARXSTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080b0, (_val))
#define WRITE_HL65_RX0_ANARXSTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080b0, (_val))
#define MODIFY_HL65_RX0_ANARXSTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b0, (_val), (_mask))

/* Rx lane control register */
#define READ_HL65_RX0_ANARXCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080b1, (_val))
#define WRITE_HL65_RX0_ANARXCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080b1, (_val))
#define MODIFY_HL65_RX0_ANARXCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b1, (_val), (_mask))

/* Rx lane control register */
#define READ_HL65_RX0_ANARXTESTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080b8, (_val))
#define WRITE_HL65_RX0_ANARXTESTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080b8, (_val))
#define MODIFY_HL65_RX0_ANARXTESTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b8, (_val), (_mask))

/* Rx 1G Control register */
#define READ_HL65_RX0_ANARXCONTROL1Gr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080b9, (_val))
#define WRITE_HL65_RX0_ANARXCONTROL1Gr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080b9, (_val))
#define MODIFY_HL65_RX0_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b9, (_val), (_mask))

/* Rx PCI Control register */
#define READ_HL65_RX0_ANARXCONTROLPCIr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080ba, (_val))
#define WRITE_HL65_RX0_ANARXCONTROLPCIr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080ba, (_val))
#define MODIFY_HL65_RX0_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ba, (_val), (_mask))

/* Rx analog status register */
#define READ_HL65_RX0_ANARXASTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080bb, (_val))
#define WRITE_HL65_RX0_ANARXASTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080bb, (_val))
#define MODIFY_HL65_RX0_ANARXASTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bb, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RX0_ANARXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080bc, (_val))
#define WRITE_HL65_RX0_ANARXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080bc, (_val))
#define MODIFY_HL65_RX0_ANARXACONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bc, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RX0_ANARXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080bd, (_val))
#define WRITE_HL65_RX0_ANARXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080bd, (_val))
#define MODIFY_HL65_RX0_ANARXACONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bd, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RX0_ANARXACONTROL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080be, (_val))
#define WRITE_HL65_RX0_ANARXACONTROL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080be, (_val))
#define MODIFY_HL65_RX0_ANARXACONTROL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080be, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Rx1
 ***************************************************************************/

/* Rx lane status register */
#define READ_HL65_RX1_ANARXSTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080c0, (_val))
#define WRITE_HL65_RX1_ANARXSTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080c0, (_val))
#define MODIFY_HL65_RX1_ANARXSTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c0, (_val), (_mask))

/* Rx lane control register */
#define READ_HL65_RX1_ANARXCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080c1, (_val))
#define WRITE_HL65_RX1_ANARXCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080c1, (_val))
#define MODIFY_HL65_RX1_ANARXCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c1, (_val), (_mask))

/* Rx lane control register */
#define READ_HL65_RX1_ANARXTESTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080c8, (_val))
#define WRITE_HL65_RX1_ANARXTESTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080c8, (_val))
#define MODIFY_HL65_RX1_ANARXTESTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c8, (_val), (_mask))

/* Rx 1G Control register */
#define READ_HL65_RX1_ANARXCONTROL1Gr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080c9, (_val))
#define WRITE_HL65_RX1_ANARXCONTROL1Gr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080c9, (_val))
#define MODIFY_HL65_RX1_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c9, (_val), (_mask))

/* Rx PCI Control register */
#define READ_HL65_RX1_ANARXCONTROLPCIr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080ca, (_val))
#define WRITE_HL65_RX1_ANARXCONTROLPCIr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080ca, (_val))
#define MODIFY_HL65_RX1_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ca, (_val), (_mask))

/* Rx analog status register */
#define READ_HL65_RX1_ANARXASTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080cb, (_val))
#define WRITE_HL65_RX1_ANARXASTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080cb, (_val))
#define MODIFY_HL65_RX1_ANARXASTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cb, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RX1_ANARXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080cc, (_val))
#define WRITE_HL65_RX1_ANARXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080cc, (_val))
#define MODIFY_HL65_RX1_ANARXACONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cc, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RX1_ANARXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080cd, (_val))
#define WRITE_HL65_RX1_ANARXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080cd, (_val))
#define MODIFY_HL65_RX1_ANARXACONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cd, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RX1_ANARXACONTROL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080ce, (_val))
#define WRITE_HL65_RX1_ANARXACONTROL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080ce, (_val))
#define MODIFY_HL65_RX1_ANARXACONTROL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ce, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Rx2
 ***************************************************************************/

/* Rx lane status register */
#define READ_HL65_RX2_ANARXSTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080d0, (_val))
#define WRITE_HL65_RX2_ANARXSTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080d0, (_val))
#define MODIFY_HL65_RX2_ANARXSTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d0, (_val), (_mask))

/* Rx lane control register */
#define READ_HL65_RX2_ANARXCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080d1, (_val))
#define WRITE_HL65_RX2_ANARXCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080d1, (_val))
#define MODIFY_HL65_RX2_ANARXCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d1, (_val), (_mask))

/* Rx lane control register */
#define READ_HL65_RX2_ANARXTESTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080d8, (_val))
#define WRITE_HL65_RX2_ANARXTESTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080d8, (_val))
#define MODIFY_HL65_RX2_ANARXTESTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d8, (_val), (_mask))

/* Rx 1G Control register */
#define READ_HL65_RX2_ANARXCONTROL1Gr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080d9, (_val))
#define WRITE_HL65_RX2_ANARXCONTROL1Gr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080d9, (_val))
#define MODIFY_HL65_RX2_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d9, (_val), (_mask))

/* Rx PCI Control register */
#define READ_HL65_RX2_ANARXCONTROLPCIr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080da, (_val))
#define WRITE_HL65_RX2_ANARXCONTROLPCIr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080da, (_val))
#define MODIFY_HL65_RX2_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080da, (_val), (_mask))

/* Rx analog status register */
#define READ_HL65_RX2_ANARXASTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080db, (_val))
#define WRITE_HL65_RX2_ANARXASTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080db, (_val))
#define MODIFY_HL65_RX2_ANARXASTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080db, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RX2_ANARXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080dc, (_val))
#define WRITE_HL65_RX2_ANARXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080dc, (_val))
#define MODIFY_HL65_RX2_ANARXACONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080dc, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RX2_ANARXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080dd, (_val))
#define WRITE_HL65_RX2_ANARXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080dd, (_val))
#define MODIFY_HL65_RX2_ANARXACONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080dd, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RX2_ANARXACONTROL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080de, (_val))
#define WRITE_HL65_RX2_ANARXACONTROL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080de, (_val))
#define MODIFY_HL65_RX2_ANARXACONTROL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080de, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Rx3
 ***************************************************************************/

/* Rx lane status register */
#define READ_HL65_RX3_ANARXSTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080e0, (_val))
#define WRITE_HL65_RX3_ANARXSTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080e0, (_val))
#define MODIFY_HL65_RX3_ANARXSTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e0, (_val), (_mask))

/* Rx lane control register */
#define READ_HL65_RX3_ANARXCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080e1, (_val))
#define WRITE_HL65_RX3_ANARXCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080e1, (_val))
#define MODIFY_HL65_RX3_ANARXCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e1, (_val), (_mask))

/* Rx lane control register */
#define READ_HL65_RX3_ANARXTESTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080e8, (_val))
#define WRITE_HL65_RX3_ANARXTESTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080e8, (_val))
#define MODIFY_HL65_RX3_ANARXTESTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e8, (_val), (_mask))

/* Rx 1G Control register */
#define READ_HL65_RX3_ANARXCONTROL1Gr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080e9, (_val))
#define WRITE_HL65_RX3_ANARXCONTROL1Gr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080e9, (_val))
#define MODIFY_HL65_RX3_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e9, (_val), (_mask))

/* Rx PCI Control register */
#define READ_HL65_RX3_ANARXCONTROLPCIr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080ea, (_val))
#define WRITE_HL65_RX3_ANARXCONTROLPCIr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080ea, (_val))
#define MODIFY_HL65_RX3_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ea, (_val), (_mask))

/* Rx analog status register */
#define READ_HL65_RX3_ANARXASTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080eb, (_val))
#define WRITE_HL65_RX3_ANARXASTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080eb, (_val))
#define MODIFY_HL65_RX3_ANARXASTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080eb, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RX3_ANARXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080ec, (_val))
#define WRITE_HL65_RX3_ANARXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080ec, (_val))
#define MODIFY_HL65_RX3_ANARXACONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ec, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RX3_ANARXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080ed, (_val))
#define WRITE_HL65_RX3_ANARXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080ed, (_val))
#define MODIFY_HL65_RX3_ANARXACONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ed, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RX3_ANARXACONTROL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080ee, (_val))
#define WRITE_HL65_RX3_ANARXACONTROL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080ee, (_val))
#define MODIFY_HL65_RX3_ANARXACONTROL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ee, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_RxB
 ***************************************************************************/

/* Rx lane status register */
#define READ_HL65_RXB_ANARXSTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080f0, (_val))
#define WRITE_HL65_RXB_ANARXSTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080f0, (_val))
#define MODIFY_HL65_RXB_ANARXSTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f0, (_val), (_mask))

/* Rx lane control register */
#define READ_HL65_RXB_ANARXCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080f1, (_val))
#define WRITE_HL65_RXB_ANARXCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080f1, (_val))
#define MODIFY_HL65_RXB_ANARXCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f1, (_val), (_mask))

/* Rx lane control register */
#define READ_HL65_RXB_ANARXTESTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080f8, (_val))
#define WRITE_HL65_RXB_ANARXTESTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080f8, (_val))
#define MODIFY_HL65_RXB_ANARXTESTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f8, (_val), (_mask))

/* Rx 1G Control register */
#define READ_HL65_RXB_ANARXCONTROL1Gr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080f9, (_val))
#define WRITE_HL65_RXB_ANARXCONTROL1Gr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080f9, (_val))
#define MODIFY_HL65_RXB_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f9, (_val), (_mask))

/* Rx PCI Control register */
#define READ_HL65_RXB_ANARXCONTROLPCIr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080fa, (_val))
#define WRITE_HL65_RXB_ANARXCONTROLPCIr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080fa, (_val))
#define MODIFY_HL65_RXB_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fa, (_val), (_mask))

/* Rx analog status register */
#define READ_HL65_RXB_ANARXASTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080fb, (_val))
#define WRITE_HL65_RXB_ANARXASTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080fb, (_val))
#define MODIFY_HL65_RXB_ANARXASTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fb, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RXB_ANARXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080fc, (_val))
#define WRITE_HL65_RXB_ANARXACONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080fc, (_val))
#define MODIFY_HL65_RXB_ANARXACONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fc, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RXB_ANARXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080fd, (_val))
#define WRITE_HL65_RXB_ANARXACONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080fd, (_val))
#define MODIFY_HL65_RXB_ANARXACONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fd, (_val), (_mask))

/* Rx reserved analog control register */
#define READ_HL65_RXB_ANARXACONTROL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000080fe, (_val))
#define WRITE_HL65_RXB_ANARXACONTROL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080fe, (_val))
#define MODIFY_HL65_RXB_ANARXACONTROL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fe, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_XgxsBlk2
 ***************************************************************************/

/* Receiver lane swap control register */
#define READ_HL65_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008100, (_val))
#define WRITE_HL65_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008100, (_val))
#define MODIFY_HL65_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008100, (_val), (_mask))

/* Transmit lane swap control register */
#define READ_HL65_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008101, (_val))
#define WRITE_HL65_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008101, (_val))
#define MODIFY_HL65_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008101, (_val), (_mask))

/* ||Q|| ordered set, lanes 0 & 1 register */
#define READ_HL65_XGXSBLK2_QSETLNS01r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008102, (_val))
#define WRITE_HL65_XGXSBLK2_QSETLNS01r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008102, (_val))
#define MODIFY_HL65_XGXSBLK2_QSETLNS01r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008102, (_val), (_mask))

/* ||Q|| ordered set, lanes 2 & 3 register */
#define READ_HL65_XGXSBLK2_QSETLNS23r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008103, (_val))
#define WRITE_HL65_XGXSBLK2_QSETLNS23r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008103, (_val))
#define MODIFY_HL65_XGXSBLK2_QSETLNS23r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008103, (_val), (_mask))

/* AN 10G resolution mode control register */
#define READ_HL65_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008104, (_val))
#define WRITE_HL65_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008104, (_val))
#define MODIFY_HL65_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008104, (_val), (_mask))

/* Independent Combo Control register */
#define READ_HL65_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008105, (_val))
#define WRITE_HL65_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008105, (_val))
#define MODIFY_HL65_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008105, (_val), (_mask))

/* Test mode lane select register */
#define READ_HL65_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008106, (_val))
#define WRITE_HL65_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008106, (_val))
#define MODIFY_HL65_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008106, (_val), (_mask))

/* Test mode monitor control register */
#define READ_HL65_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008107, (_val))
#define WRITE_HL65_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008107, (_val))
#define MODIFY_HL65_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008107, (_val), (_mask))

/* Test mode mux control register */
#define READ_HL65_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008108, (_val))
#define WRITE_HL65_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008108, (_val))
#define MODIFY_HL65_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008108, (_val), (_mask))

/* 10GBASE-CX4 signal detect timeout value */
#define READ_HL65_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008109, (_val))
#define WRITE_HL65_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008109, (_val))
#define MODIFY_HL65_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008109, (_val), (_mask))

/* Lane reset register */
#define READ_HL65_XGXSBLK2_LANERESETr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000810a, (_val))
#define WRITE_HL65_XGXSBLK2_LANERESETr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000810a, (_val))
#define MODIFY_HL65_XGXSBLK2_LANERESETr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000810a, (_val), (_mask))

/* XGXS Status 6 register */
#define READ_HL65_XGXSBLK2_XGXSSTATUS6r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000810b, (_val))
#define WRITE_HL65_XGXSBLK2_XGXSSTATUS6r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000810b, (_val))
#define MODIFY_HL65_XGXSBLK2_XGXSSTATUS6r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000810b, (_val), (_mask))

/* Clause 73 control 7 register */
#define READ_HL65_XGXSBLK2_CL73CONTROL7r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000810d, (_val))
#define WRITE_HL65_XGXSBLK2_CL73CONTROL7r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000810d, (_val))
#define MODIFY_HL65_XGXSBLK2_CL73CONTROL7r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000810d, (_val), (_mask))

/* Clause 73 control 8 register */
#define READ_HL65_XGXSBLK2_CL73CONTROL8r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000810e, (_val))
#define WRITE_HL65_XGXSBLK2_CL73CONTROL8r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000810e, (_val))
#define MODIFY_HL65_XGXSBLK2_CL73CONTROL8r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000810e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_XgxsBlk3
 ***************************************************************************/

/* In Band MDIO - local status register */
#define READ_HL65_XGXSBLK3_LOCALSTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008110, (_val))
#define WRITE_HL65_XGXSBLK3_LOCALSTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008110, (_val))
#define MODIFY_HL65_XGXSBLK3_LOCALSTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008110, (_val), (_mask))

/* In Band MDIO - local control 0 register */
#define READ_HL65_XGXSBLK3_LOCALCONTROL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008111, (_val))
#define WRITE_HL65_XGXSBLK3_LOCALCONTROL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008111, (_val))
#define MODIFY_HL65_XGXSBLK3_LOCALCONTROL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008111, (_val), (_mask))

/* In Band MDIO - local control 1 register */
#define READ_HL65_XGXSBLK3_LOCALCONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008112, (_val))
#define WRITE_HL65_XGXSBLK3_LOCALCONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008112, (_val))
#define MODIFY_HL65_XGXSBLK3_LOCALCONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008112, (_val), (_mask))

/* In Band MDIO - remote write ln 0 & 3 register */
#define READ_HL65_XGXSBLK3_REMOTEWRITE03r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008113, (_val))
#define WRITE_HL65_XGXSBLK3_REMOTEWRITE03r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008113, (_val))
#define MODIFY_HL65_XGXSBLK3_REMOTEWRITE03r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008113, (_val), (_mask))

/* In Band MDIO - remote write ln 1 & 2 register */
#define READ_HL65_XGXSBLK3_REMOTEWRITE12r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008114, (_val))
#define WRITE_HL65_XGXSBLK3_REMOTEWRITE12r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008114, (_val))
#define MODIFY_HL65_XGXSBLK3_REMOTEWRITE12r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008114, (_val), (_mask))

/* In Band MDIO - remote read ln 1 & 2 register */
#define READ_HL65_XGXSBLK3_REMOTEREAD12r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008115, (_val))
#define WRITE_HL65_XGXSBLK3_REMOTEREAD12r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008115, (_val))
#define MODIFY_HL65_XGXSBLK3_REMOTEREAD12r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008115, (_val), (_mask))

/* In Band MDIO - remote read ln 0 & 3 register */
#define READ_HL65_XGXSBLK3_REMOTEREADX3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008116, (_val))
#define WRITE_HL65_XGXSBLK3_REMOTEREADX3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008116, (_val))
#define MODIFY_HL65_XGXSBLK3_REMOTEREADX3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008116, (_val), (_mask))

/* In Band MDIO - status register */
#define READ_HL65_XGXSBLK3_RX_INBANDMDIOSTATr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008117, (_val))
#define WRITE_HL65_XGXSBLK3_RX_INBANDMDIOSTATr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008117, (_val))
#define MODIFY_HL65_XGXSBLK3_RX_INBANDMDIOSTATr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008117, (_val), (_mask))

/* In Band MDIO - local IAC register */
#define READ_HL65_XGXSBLK3_LOCALIACr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008118, (_val))
#define WRITE_HL65_XGXSBLK3_LOCALIACr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008118, (_val))
#define MODIFY_HL65_XGXSBLK3_LOCALIACr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008118, (_val), (_mask))

/* In Band MDIO - remote IAC register */
#define READ_HL65_XGXSBLK3_REMOTEIACNr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008119, (_val))
#define WRITE_HL65_XGXSBLK3_REMOTEIACNr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008119, (_val))
#define MODIFY_HL65_XGXSBLK3_REMOTEIACNr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008119, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_GP_Status
 ***************************************************************************/

/* Miscellaneous Rx status register */
#define READ_HL65_GP_STATUS_MISCRXSTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008120, (_val))
#define WRITE_HL65_GP_STATUS_MISCRXSTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008120, (_val))
#define MODIFY_HL65_GP_STATUS_MISCRXSTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008120, (_val), (_mask))

/* XGXS status register */
#define READ_HL65_GP_STATUS_XGXSSTATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008121, (_val))
#define WRITE_HL65_GP_STATUS_XGXSSTATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008121, (_val))
#define MODIFY_HL65_GP_STATUS_XGXSSTATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008121, (_val), (_mask))

/* XGXS status 1 register */
#define READ_HL65_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008122, (_val))
#define WRITE_HL65_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008122, (_val))
#define MODIFY_HL65_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008122, (_val), (_mask))

/* XGXS status 2 register */
#define READ_HL65_GP_STATUS_XGXSSTATUS2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008123, (_val))
#define WRITE_HL65_GP_STATUS_XGXSSTATUS2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008123, (_val))
#define MODIFY_HL65_GP_STATUS_XGXSSTATUS2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008123, (_val), (_mask))

/* 1000X status 1 register */
#define READ_HL65_GP_STATUS_STATUS1000X1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008124, (_val))
#define WRITE_HL65_GP_STATUS_STATUS1000X1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008124, (_val))
#define MODIFY_HL65_GP_STATUS_STATUS1000X1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008124, (_val), (_mask))

/* 1000X status 2 register */
#define READ_HL65_GP_STATUS_STATUS1000X2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008125, (_val))
#define WRITE_HL65_GP_STATUS_STATUS1000X2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008125, (_val))
#define MODIFY_HL65_GP_STATUS_STATUS1000X2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008125, (_val), (_mask))

/* 1000X status 3 register */
#define READ_HL65_GP_STATUS_STATUS1000X3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008126, (_val))
#define WRITE_HL65_GP_STATUS_STATUS1000X3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008126, (_val))
#define MODIFY_HL65_GP_STATUS_STATUS1000X3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008126, (_val), (_mask))

/* Test port out bits 15:0, tpout[15:0] */
#define READ_HL65_GP_STATUS_TPOUT_1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008127, (_val))
#define WRITE_HL65_GP_STATUS_TPOUT_1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008127, (_val))
#define MODIFY_HL65_GP_STATUS_TPOUT_1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008127, (_val), (_mask))

/* Test port out bits 23:8, tpout[23:8] */
#define READ_HL65_GP_STATUS_TPOUT_2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008128, (_val))
#define WRITE_HL65_GP_STATUS_TPOUT_2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008128, (_val))
#define MODIFY_HL65_GP_STATUS_TPOUT_2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008128, (_val), (_mask))

/* XGXS status 3 register */
#define READ_HL65_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008129, (_val))
#define WRITE_HL65_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008129, (_val))
#define MODIFY_HL65_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008129, (_val), (_mask))

/* 2500X status register */
#define READ_HL65_GP_STATUS_X2500STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000812a, (_val))
#define WRITE_HL65_GP_STATUS_X2500STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000812a, (_val))
#define MODIFY_HL65_GP_STATUS_X2500STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812a, (_val), (_mask))

/* CL73 AN status 1 register */
#define READ_HL65_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000812b, (_val))
#define WRITE_HL65_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000812b, (_val))
#define MODIFY_HL65_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812b, (_val), (_mask))

/* AN link partner user page 1 */
#define READ_HL65_GP_STATUS_LP_UP1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000812c, (_val))
#define WRITE_HL65_GP_STATUS_LP_UP1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000812c, (_val))
#define MODIFY_HL65_GP_STATUS_LP_UP1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812c, (_val), (_mask))

/* AN link partner user page 2 */
#define READ_HL65_GP_STATUS_LP_UP2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000812d, (_val))
#define WRITE_HL65_GP_STATUS_LP_UP2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000812d, (_val))
#define MODIFY_HL65_GP_STATUS_LP_UP2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812d, (_val), (_mask))

/* AN link partner user page 3 */
#define READ_HL65_GP_STATUS_LP_UP3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000812e, (_val))
#define WRITE_HL65_GP_STATUS_LP_UP3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000812e, (_val))
#define MODIFY_HL65_GP_STATUS_LP_UP3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_AN73_pdet
 ***************************************************************************/

/* 10G parallel detect status register */
#define READ_HL65_AN73_PDET_PARDET10GSTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008130, (_val))
#define WRITE_HL65_AN73_PDET_PARDET10GSTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008130, (_val))
#define MODIFY_HL65_AN73_PDET_PARDET10GSTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008130, (_val), (_mask))

/* 10G parallel detect control register */
#define READ_HL65_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008131, (_val))
#define WRITE_HL65_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008131, (_val))
#define MODIFY_HL65_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008131, (_val), (_mask))

/* 10G parallel detect signal detect register */
#define READ_HL65_AN73_PDET_PARDET10GSIGDETr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008132, (_val))
#define WRITE_HL65_AN73_PDET_PARDET10GSIGDETr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008132, (_val))
#define MODIFY_HL65_AN73_PDET_PARDET10GSIGDETr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008132, (_val), (_mask))

/* 10G parallel detect link register */
#define READ_HL65_AN73_PDET_PARDET10GLINKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008133, (_val))
#define WRITE_HL65_AN73_PDET_PARDET10GLINKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008133, (_val))
#define MODIFY_HL65_AN73_PDET_PARDET10GLINKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008133, (_val), (_mask))

/* 10G parallel detect lost link register */
#define READ_HL65_AN73_PDET_PARDET10GLOSTLINKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008134, (_val))
#define WRITE_HL65_AN73_PDET_PARDET10GLOSTLINKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008134, (_val))
#define MODIFY_HL65_AN73_PDET_PARDET10GLOSTLINKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008134, (_val), (_mask))

/* Clause 73 auto-negotiation control register 1 */
#define READ_HL65_AN73_PDET_CL73CONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008135, (_val))
#define WRITE_HL65_AN73_PDET_CL73CONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008135, (_val))
#define MODIFY_HL65_AN73_PDET_CL73CONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008135, (_val), (_mask))

/* Clause 73 auto-negotiation control register 2 */
#define READ_HL65_AN73_PDET_CL73CONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008136, (_val))
#define WRITE_HL65_AN73_PDET_CL73CONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008136, (_val))
#define MODIFY_HL65_AN73_PDET_CL73CONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008136, (_val), (_mask))

/* Clause 73 auto-negotiation control register 3 */
#define READ_HL65_AN73_PDET_CL73CONTROL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008137, (_val))
#define WRITE_HL65_AN73_PDET_CL73CONTROL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008137, (_val))
#define MODIFY_HL65_AN73_PDET_CL73CONTROL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008137, (_val), (_mask))

/* Clause 73 auto-negotiation control register 4 */
#define READ_HL65_AN73_PDET_CL73CONTROL4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008138, (_val))
#define WRITE_HL65_AN73_PDET_CL73CONTROL4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008138, (_val))
#define MODIFY_HL65_AN73_PDET_CL73CONTROL4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008138, (_val), (_mask))

/* Clause 73 auto-negotiation control register 5 */
#define READ_HL65_AN73_PDET_CL73CONTROL5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008139, (_val))
#define WRITE_HL65_AN73_PDET_CL73CONTROL5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008139, (_val))
#define MODIFY_HL65_AN73_PDET_CL73CONTROL5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008139, (_val), (_mask))

/* Clause 73 auto-negotiation control register 6 */
#define READ_HL65_AN73_PDET_CL73CONTROL6r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000813a, (_val))
#define WRITE_HL65_AN73_PDET_CL73CONTROL6r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000813a, (_val))
#define MODIFY_HL65_AN73_PDET_CL73CONTROL6r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813a, (_val), (_mask))

/* Clause 73 auto-negotiation DME Timers Register */
#define READ_HL65_AN73_PDET_CL73DMETMRSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000813b, (_val))
#define WRITE_HL65_AN73_PDET_CL73DMETMRSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000813b, (_val))
#define MODIFY_HL65_AN73_PDET_CL73DMETMRSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813b, (_val), (_mask))

/* XGXS Status 4 Register */
#define READ_HL65_AN73_PDET_XGXSSTATUS4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000813c, (_val))
#define WRITE_HL65_AN73_PDET_XGXSSTATUS4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000813c, (_val))
#define MODIFY_HL65_AN73_PDET_XGXSSTATUS4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813c, (_val), (_mask))

/* XGXS Status 5 Register */
#define READ_HL65_AN73_PDET_XGXSSTATUS5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000813d, (_val))
#define WRITE_HL65_AN73_PDET_XGXSSTATUS5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000813d, (_val))
#define MODIFY_HL65_AN73_PDET_XGXSSTATUS5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813d, (_val), (_mask))

/* 10G parallel detect control 2 register */
#define READ_HL65_AN73_PDET_PARDET10GCONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000813e, (_val))
#define WRITE_HL65_AN73_PDET_PARDET10GCONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000813e, (_val))
#define MODIFY_HL65_AN73_PDET_PARDET10GCONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_tx66_0
 ***************************************************************************/

/* 64/66 Encoder Control Register */
#define READ_HL65_TX66_0_CONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008160, (_val))
#define WRITE_HL65_TX66_0_CONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008160, (_val))
#define MODIFY_HL65_TX66_0_CONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008160, (_val), (_mask))

/* 64/66 Encoder Status Register */
#define READ_HL65_TX66_0_STATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008161, (_val))
#define WRITE_HL65_TX66_0_STATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008161, (_val))
#define MODIFY_HL65_TX66_0_STATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008161, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_tx66_1
 ***************************************************************************/

/* 64/66 Encoder Control Register */
#define READ_HL65_TX66_1_CONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008170, (_val))
#define WRITE_HL65_TX66_1_CONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008170, (_val))
#define MODIFY_HL65_TX66_1_CONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008170, (_val), (_mask))

/* 64/66 Encoder Status Register */
#define READ_HL65_TX66_1_STATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008171, (_val))
#define WRITE_HL65_TX66_1_STATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008171, (_val))
#define MODIFY_HL65_TX66_1_STATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008171, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_tx66_2
 ***************************************************************************/

/* 64/66 Encoder Control Register */
#define READ_HL65_TX66_2_CONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008180, (_val))
#define WRITE_HL65_TX66_2_CONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008180, (_val))
#define MODIFY_HL65_TX66_2_CONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008180, (_val), (_mask))

/* 64/66 Encoder Status Register */
#define READ_HL65_TX66_2_STATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008181, (_val))
#define WRITE_HL65_TX66_2_STATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008181, (_val))
#define MODIFY_HL65_TX66_2_STATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008181, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_tx66_3
 ***************************************************************************/

/* 64/66 Encoder Control Register */
#define READ_HL65_TX66_3_CONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008190, (_val))
#define WRITE_HL65_TX66_3_CONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008190, (_val))
#define MODIFY_HL65_TX66_3_CONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008190, (_val), (_mask))

/* 64/66 Encoder Status Register */
#define READ_HL65_TX66_3_STATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008191, (_val))
#define WRITE_HL65_TX66_3_STATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008191, (_val))
#define MODIFY_HL65_TX66_3_STATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008191, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_tx66_A
 ***************************************************************************/

/* 64/66 Encoder Control Register */
#define READ_HL65_TX66_A_CONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081a0, (_val))
#define WRITE_HL65_TX66_A_CONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081a0, (_val))
#define MODIFY_HL65_TX66_A_CONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081a0, (_val), (_mask))

/* 64/66 Encoder Status Register */
#define READ_HL65_TX66_A_STATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081a1, (_val))
#define WRITE_HL65_TX66_A_STATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081a1, (_val))
#define MODIFY_HL65_TX66_A_STATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081a1, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_rx66_0
 ***************************************************************************/

/* 64/66 Decoder control register */
#define READ_HL65_RX66_0_CONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b0, (_val))
#define WRITE_HL65_RX66_0_CONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b0, (_val))
#define MODIFY_HL65_RX66_0_CONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b0, (_val), (_mask))

/* 64/66 Decoder status register */
#define READ_HL65_RX66_0_STATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b1, (_val))
#define WRITE_HL65_RX66_0_STATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b1, (_val))
#define MODIFY_HL65_RX66_0_STATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b1, (_val), (_mask))

/* Sync code word bits 15:0 */
#define READ_HL65_RX66_0_SCW0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b2, (_val))
#define WRITE_HL65_RX66_0_SCW0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b2, (_val))
#define MODIFY_HL65_RX66_0_SCW0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b2, (_val), (_mask))

/* Sync code word bits 31;16 */
#define READ_HL65_RX66_0_SCW1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b3, (_val))
#define WRITE_HL65_RX66_0_SCW1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b3, (_val))
#define MODIFY_HL65_RX66_0_SCW1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b3, (_val), (_mask))

/* Sync code word bits 47:32 */
#define READ_HL65_RX66_0_SCW2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b4, (_val))
#define WRITE_HL65_RX66_0_SCW2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b4, (_val))
#define MODIFY_HL65_RX66_0_SCW2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b4, (_val), (_mask))

/* Sync code word bits 63:48 */
#define READ_HL65_RX66_0_SCW3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b5, (_val))
#define WRITE_HL65_RX66_0_SCW3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b5, (_val))
#define MODIFY_HL65_RX66_0_SCW3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b5, (_val), (_mask))

/* Sync code word mask bits 15:0 */
#define READ_HL65_RX66_0_SCW0_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b6, (_val))
#define WRITE_HL65_RX66_0_SCW0_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b6, (_val))
#define MODIFY_HL65_RX66_0_SCW0_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b6, (_val), (_mask))

/* Sync code word mask bits 31;16 */
#define READ_HL65_RX66_0_SCW1_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b7, (_val))
#define WRITE_HL65_RX66_0_SCW1_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b7, (_val))
#define MODIFY_HL65_RX66_0_SCW1_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b7, (_val), (_mask))

/* Sync code word mask bits 47:32 */
#define READ_HL65_RX66_0_SCW2_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b8, (_val))
#define WRITE_HL65_RX66_0_SCW2_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b8, (_val))
#define MODIFY_HL65_RX66_0_SCW2_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b8, (_val), (_mask))

/* Sync code word mask bits 63:48 */
#define READ_HL65_RX66_0_SCW3_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b9, (_val))
#define WRITE_HL65_RX66_0_SCW3_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b9, (_val))
#define MODIFY_HL65_RX66_0_SCW3_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b9, (_val), (_mask))

/* Sync bits and sync mask bits */
#define READ_HL65_RX66_0_SYNCBITSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081ba, (_val))
#define WRITE_HL65_RX66_0_SYNCBITSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081ba, (_val))
#define MODIFY_HL65_RX66_0_SYNCBITSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ba, (_val), (_mask))

/* Sync code word statemachine control register */
#define READ_HL65_RX66_0_SCWCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081bb, (_val))
#define WRITE_HL65_RX66_0_SCWCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081bb, (_val))
#define MODIFY_HL65_RX66_0_SCWCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081bb, (_val), (_mask))

/* CW=SCW counter & skew position */
#define READ_HL65_RX66_0_SCWCOUNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081bd, (_val))
#define WRITE_HL65_RX66_0_SCWCOUNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081bd, (_val))
#define MODIFY_HL65_RX66_0_SCWCOUNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081bd, (_val), (_mask))

/* scw & K-code group error counters */
#define READ_HL65_RX66_0_ERRCOUNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081be, (_val))
#define WRITE_HL65_RX66_0_ERRCOUNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081be, (_val))
#define MODIFY_HL65_RX66_0_ERRCOUNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081be, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_rx66_1
 ***************************************************************************/

/* 64/66 Decoder control register */
#define READ_HL65_RX66_1_CONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c0, (_val))
#define WRITE_HL65_RX66_1_CONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c0, (_val))
#define MODIFY_HL65_RX66_1_CONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c0, (_val), (_mask))

/* 64/66 Decoder status register */
#define READ_HL65_RX66_1_STATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c1, (_val))
#define WRITE_HL65_RX66_1_STATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c1, (_val))
#define MODIFY_HL65_RX66_1_STATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c1, (_val), (_mask))

/* Sync code word bits 15:0 */
#define READ_HL65_RX66_1_SCW0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c2, (_val))
#define WRITE_HL65_RX66_1_SCW0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c2, (_val))
#define MODIFY_HL65_RX66_1_SCW0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c2, (_val), (_mask))

/* Sync code word bits 31;16 */
#define READ_HL65_RX66_1_SCW1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c3, (_val))
#define WRITE_HL65_RX66_1_SCW1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c3, (_val))
#define MODIFY_HL65_RX66_1_SCW1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c3, (_val), (_mask))

/* Sync code word bits 47:32 */
#define READ_HL65_RX66_1_SCW2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c4, (_val))
#define WRITE_HL65_RX66_1_SCW2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c4, (_val))
#define MODIFY_HL65_RX66_1_SCW2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c4, (_val), (_mask))

/* Sync code word bits 63:48 */
#define READ_HL65_RX66_1_SCW3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c5, (_val))
#define WRITE_HL65_RX66_1_SCW3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c5, (_val))
#define MODIFY_HL65_RX66_1_SCW3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c5, (_val), (_mask))

/* Sync code word mask bits 15:0 */
#define READ_HL65_RX66_1_SCW0_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c6, (_val))
#define WRITE_HL65_RX66_1_SCW0_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c6, (_val))
#define MODIFY_HL65_RX66_1_SCW0_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c6, (_val), (_mask))

/* Sync code word mask bits 31;16 */
#define READ_HL65_RX66_1_SCW1_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c7, (_val))
#define WRITE_HL65_RX66_1_SCW1_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c7, (_val))
#define MODIFY_HL65_RX66_1_SCW1_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c7, (_val), (_mask))

/* Sync code word mask bits 47:32 */
#define READ_HL65_RX66_1_SCW2_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c8, (_val))
#define WRITE_HL65_RX66_1_SCW2_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c8, (_val))
#define MODIFY_HL65_RX66_1_SCW2_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c8, (_val), (_mask))

/* Sync code word mask bits 63:48 */
#define READ_HL65_RX66_1_SCW3_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c9, (_val))
#define WRITE_HL65_RX66_1_SCW3_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c9, (_val))
#define MODIFY_HL65_RX66_1_SCW3_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c9, (_val), (_mask))

/* Sync bits and sync mask bits */
#define READ_HL65_RX66_1_SYNCBITSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081ca, (_val))
#define WRITE_HL65_RX66_1_SYNCBITSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081ca, (_val))
#define MODIFY_HL65_RX66_1_SYNCBITSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ca, (_val), (_mask))

/* Sync code word statemachine control register */
#define READ_HL65_RX66_1_SCWCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081cb, (_val))
#define WRITE_HL65_RX66_1_SCWCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081cb, (_val))
#define MODIFY_HL65_RX66_1_SCWCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081cb, (_val), (_mask))

/* CW=SCW counter & skew position */
#define READ_HL65_RX66_1_SCWCOUNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081cd, (_val))
#define WRITE_HL65_RX66_1_SCWCOUNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081cd, (_val))
#define MODIFY_HL65_RX66_1_SCWCOUNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081cd, (_val), (_mask))

/* scw & K-code group error counters */
#define READ_HL65_RX66_1_ERRCOUNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081ce, (_val))
#define WRITE_HL65_RX66_1_ERRCOUNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081ce, (_val))
#define MODIFY_HL65_RX66_1_ERRCOUNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ce, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_rx66_2
 ***************************************************************************/

/* 64/66 Decoder control register */
#define READ_HL65_RX66_2_CONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d0, (_val))
#define WRITE_HL65_RX66_2_CONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d0, (_val))
#define MODIFY_HL65_RX66_2_CONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d0, (_val), (_mask))

/* 64/66 Decoder status register */
#define READ_HL65_RX66_2_STATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d1, (_val))
#define WRITE_HL65_RX66_2_STATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d1, (_val))
#define MODIFY_HL65_RX66_2_STATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d1, (_val), (_mask))

/* Sync code word bits 15:0 */
#define READ_HL65_RX66_2_SCW0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d2, (_val))
#define WRITE_HL65_RX66_2_SCW0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d2, (_val))
#define MODIFY_HL65_RX66_2_SCW0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d2, (_val), (_mask))

/* Sync code word bits 31;16 */
#define READ_HL65_RX66_2_SCW1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d3, (_val))
#define WRITE_HL65_RX66_2_SCW1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d3, (_val))
#define MODIFY_HL65_RX66_2_SCW1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d3, (_val), (_mask))

/* Sync code word bits 47:32 */
#define READ_HL65_RX66_2_SCW2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d4, (_val))
#define WRITE_HL65_RX66_2_SCW2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d4, (_val))
#define MODIFY_HL65_RX66_2_SCW2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d4, (_val), (_mask))

/* Sync code word bits 63:48 */
#define READ_HL65_RX66_2_SCW3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d5, (_val))
#define WRITE_HL65_RX66_2_SCW3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d5, (_val))
#define MODIFY_HL65_RX66_2_SCW3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d5, (_val), (_mask))

/* Sync code word mask bits 15:0 */
#define READ_HL65_RX66_2_SCW0_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d6, (_val))
#define WRITE_HL65_RX66_2_SCW0_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d6, (_val))
#define MODIFY_HL65_RX66_2_SCW0_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d6, (_val), (_mask))

/* Sync code word mask bits 31;16 */
#define READ_HL65_RX66_2_SCW1_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d7, (_val))
#define WRITE_HL65_RX66_2_SCW1_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d7, (_val))
#define MODIFY_HL65_RX66_2_SCW1_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d7, (_val), (_mask))

/* Sync code word mask bits 47:32 */
#define READ_HL65_RX66_2_SCW2_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d8, (_val))
#define WRITE_HL65_RX66_2_SCW2_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d8, (_val))
#define MODIFY_HL65_RX66_2_SCW2_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d8, (_val), (_mask))

/* Sync code word mask bits 63:48 */
#define READ_HL65_RX66_2_SCW3_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d9, (_val))
#define WRITE_HL65_RX66_2_SCW3_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d9, (_val))
#define MODIFY_HL65_RX66_2_SCW3_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d9, (_val), (_mask))

/* Sync bits and sync mask bits */
#define READ_HL65_RX66_2_SYNCBITSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081da, (_val))
#define WRITE_HL65_RX66_2_SYNCBITSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081da, (_val))
#define MODIFY_HL65_RX66_2_SYNCBITSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081da, (_val), (_mask))

/* Sync code word statemachine control register */
#define READ_HL65_RX66_2_SCWCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081db, (_val))
#define WRITE_HL65_RX66_2_SCWCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081db, (_val))
#define MODIFY_HL65_RX66_2_SCWCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081db, (_val), (_mask))

/* CW=SCW counter & skew position */
#define READ_HL65_RX66_2_SCWCOUNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081dd, (_val))
#define WRITE_HL65_RX66_2_SCWCOUNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081dd, (_val))
#define MODIFY_HL65_RX66_2_SCWCOUNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081dd, (_val), (_mask))

/* scw & K-code group error counters */
#define READ_HL65_RX66_2_ERRCOUNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081de, (_val))
#define WRITE_HL65_RX66_2_ERRCOUNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081de, (_val))
#define MODIFY_HL65_RX66_2_ERRCOUNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081de, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_rx66_3
 ***************************************************************************/

/* 64/66 Decoder control register */
#define READ_HL65_RX66_3_CONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e0, (_val))
#define WRITE_HL65_RX66_3_CONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e0, (_val))
#define MODIFY_HL65_RX66_3_CONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e0, (_val), (_mask))

/* 64/66 Decoder status register */
#define READ_HL65_RX66_3_STATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e1, (_val))
#define WRITE_HL65_RX66_3_STATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e1, (_val))
#define MODIFY_HL65_RX66_3_STATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e1, (_val), (_mask))

/* Sync code word bits 15:0 */
#define READ_HL65_RX66_3_SCW0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e2, (_val))
#define WRITE_HL65_RX66_3_SCW0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e2, (_val))
#define MODIFY_HL65_RX66_3_SCW0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e2, (_val), (_mask))

/* Sync code word bits 31;16 */
#define READ_HL65_RX66_3_SCW1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e3, (_val))
#define WRITE_HL65_RX66_3_SCW1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e3, (_val))
#define MODIFY_HL65_RX66_3_SCW1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e3, (_val), (_mask))

/* Sync code word bits 47:32 */
#define READ_HL65_RX66_3_SCW2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e4, (_val))
#define WRITE_HL65_RX66_3_SCW2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e4, (_val))
#define MODIFY_HL65_RX66_3_SCW2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e4, (_val), (_mask))

/* Sync code word bits 63:48 */
#define READ_HL65_RX66_3_SCW3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e5, (_val))
#define WRITE_HL65_RX66_3_SCW3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e5, (_val))
#define MODIFY_HL65_RX66_3_SCW3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e5, (_val), (_mask))

/* Sync code word mask bits 15:0 */
#define READ_HL65_RX66_3_SCW0_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e6, (_val))
#define WRITE_HL65_RX66_3_SCW0_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e6, (_val))
#define MODIFY_HL65_RX66_3_SCW0_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e6, (_val), (_mask))

/* Sync code word mask bits 31;16 */
#define READ_HL65_RX66_3_SCW1_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e7, (_val))
#define WRITE_HL65_RX66_3_SCW1_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e7, (_val))
#define MODIFY_HL65_RX66_3_SCW1_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e7, (_val), (_mask))

/* Sync code word mask bits 47:32 */
#define READ_HL65_RX66_3_SCW2_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e8, (_val))
#define WRITE_HL65_RX66_3_SCW2_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e8, (_val))
#define MODIFY_HL65_RX66_3_SCW2_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e8, (_val), (_mask))

/* Sync code word mask bits 63:48 */
#define READ_HL65_RX66_3_SCW3_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e9, (_val))
#define WRITE_HL65_RX66_3_SCW3_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e9, (_val))
#define MODIFY_HL65_RX66_3_SCW3_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e9, (_val), (_mask))

/* Sync bits and sync mask bits */
#define READ_HL65_RX66_3_SYNCBITSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081ea, (_val))
#define WRITE_HL65_RX66_3_SYNCBITSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081ea, (_val))
#define MODIFY_HL65_RX66_3_SYNCBITSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ea, (_val), (_mask))

/* Sync code word statemachine control register */
#define READ_HL65_RX66_3_SCWCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081eb, (_val))
#define WRITE_HL65_RX66_3_SCWCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081eb, (_val))
#define MODIFY_HL65_RX66_3_SCWCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081eb, (_val), (_mask))

/* CW=SCW counter & skew position */
#define READ_HL65_RX66_3_SCWCOUNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081ed, (_val))
#define WRITE_HL65_RX66_3_SCWCOUNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081ed, (_val))
#define MODIFY_HL65_RX66_3_SCWCOUNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ed, (_val), (_mask))

/* scw & K-code group error counters */
#define READ_HL65_RX66_3_ERRCOUNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081ee, (_val))
#define WRITE_HL65_RX66_3_ERRCOUNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081ee, (_val))
#define MODIFY_HL65_RX66_3_ERRCOUNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ee, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_rx66_A
 ***************************************************************************/

/* 64/66 Decoder control register */
#define READ_HL65_RX66_A_CONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f0, (_val))
#define WRITE_HL65_RX66_A_CONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f0, (_val))
#define MODIFY_HL65_RX66_A_CONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f0, (_val), (_mask))

/* 64/66 Decoder status register */
#define READ_HL65_RX66_A_STATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f1, (_val))
#define WRITE_HL65_RX66_A_STATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f1, (_val))
#define MODIFY_HL65_RX66_A_STATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f1, (_val), (_mask))

/* Sync code word bits 15:0 */
#define READ_HL65_RX66_A_SCW0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f2, (_val))
#define WRITE_HL65_RX66_A_SCW0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f2, (_val))
#define MODIFY_HL65_RX66_A_SCW0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f2, (_val), (_mask))

/* Sync code word bits 31;16 */
#define READ_HL65_RX66_A_SCW1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f3, (_val))
#define WRITE_HL65_RX66_A_SCW1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f3, (_val))
#define MODIFY_HL65_RX66_A_SCW1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f3, (_val), (_mask))

/* Sync code word bits 47:32 */
#define READ_HL65_RX66_A_SCW2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f4, (_val))
#define WRITE_HL65_RX66_A_SCW2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f4, (_val))
#define MODIFY_HL65_RX66_A_SCW2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f4, (_val), (_mask))

/* Sync code word bits 63:48 */
#define READ_HL65_RX66_A_SCW3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f5, (_val))
#define WRITE_HL65_RX66_A_SCW3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f5, (_val))
#define MODIFY_HL65_RX66_A_SCW3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f5, (_val), (_mask))

/* Sync code word mask bits 15:0 */
#define READ_HL65_RX66_A_SCW0_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f6, (_val))
#define WRITE_HL65_RX66_A_SCW0_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f6, (_val))
#define MODIFY_HL65_RX66_A_SCW0_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f6, (_val), (_mask))

/* Sync code word mask bits 31;16 */
#define READ_HL65_RX66_A_SCW1_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f7, (_val))
#define WRITE_HL65_RX66_A_SCW1_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f7, (_val))
#define MODIFY_HL65_RX66_A_SCW1_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f7, (_val), (_mask))

/* Sync code word mask bits 47:32 */
#define READ_HL65_RX66_A_SCW2_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f8, (_val))
#define WRITE_HL65_RX66_A_SCW2_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f8, (_val))
#define MODIFY_HL65_RX66_A_SCW2_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f8, (_val), (_mask))

/* Sync code word mask bits 63:48 */
#define READ_HL65_RX66_A_SCW3_MASKr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f9, (_val))
#define WRITE_HL65_RX66_A_SCW3_MASKr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f9, (_val))
#define MODIFY_HL65_RX66_A_SCW3_MASKr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f9, (_val), (_mask))

/* Sync bits and sync mask bits */
#define READ_HL65_RX66_A_SYNCBITSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081fa, (_val))
#define WRITE_HL65_RX66_A_SYNCBITSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081fa, (_val))
#define MODIFY_HL65_RX66_A_SYNCBITSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081fa, (_val), (_mask))

/* Sync code word statemachine control register */
#define READ_HL65_RX66_A_SCWCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081fb, (_val))
#define WRITE_HL65_RX66_A_SCWCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081fb, (_val))
#define MODIFY_HL65_RX66_A_SCWCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081fb, (_val), (_mask))

/* CW=SCW counter & skew position */
#define READ_HL65_RX66_A_SCWCOUNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081fd, (_val))
#define WRITE_HL65_RX66_A_SCWCOUNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081fd, (_val))
#define MODIFY_HL65_RX66_A_SCWCOUNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081fd, (_val), (_mask))

/* scw & K-code group error counters */
#define READ_HL65_RX66_A_ERRCOUNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000081fe, (_val))
#define WRITE_HL65_RX66_A_ERRCOUNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081fe, (_val))
#define MODIFY_HL65_RX66_A_ERRCOUNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081fe, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc1b0
 ***************************************************************************/

/* CDR Control 0 Register */
#define READ_HL65_DSC1B0_CDR_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008210, (_val))
#define WRITE_HL65_DSC1B0_CDR_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008210, (_val))
#define MODIFY_HL65_DSC1B0_CDR_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008210, (_val), (_mask))

/* CDR Control 1 Register */
#define READ_HL65_DSC1B0_CDR_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008211, (_val))
#define WRITE_HL65_DSC1B0_CDR_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008211, (_val))
#define MODIFY_HL65_DSC1B0_CDR_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008211, (_val), (_mask))

/* CDR Control 2 Register */
#define READ_HL65_DSC1B0_CDR_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008212, (_val))
#define WRITE_HL65_DSC1B0_CDR_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008212, (_val))
#define MODIFY_HL65_DSC1B0_CDR_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008212, (_val), (_mask))

/* Phase Interpolator  Control 0 Register */
#define READ_HL65_DSC1B0_PI_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008213, (_val))
#define WRITE_HL65_DSC1B0_PI_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008213, (_val))
#define MODIFY_HL65_DSC1B0_PI_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008213, (_val), (_mask))

/* DFE VGA Control 0 Register */
#define READ_HL65_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008214, (_val))
#define WRITE_HL65_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008214, (_val))
#define MODIFY_HL65_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008214, (_val), (_mask))

/* DFE VGA Control 1 Register */
#define READ_HL65_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008215, (_val))
#define WRITE_HL65_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008215, (_val))
#define MODIFY_HL65_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008215, (_val), (_mask))

/* DFE VGA Control 2 Register */
#define READ_HL65_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008216, (_val))
#define WRITE_HL65_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008216, (_val))
#define MODIFY_HL65_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008216, (_val), (_mask))

/* DFE VGA Control 3 Register */
#define READ_HL65_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008217, (_val))
#define WRITE_HL65_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008217, (_val))
#define MODIFY_HL65_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008217, (_val), (_mask))

/* DFE VGA Control 4 Register */
#define READ_HL65_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008218, (_val))
#define WRITE_HL65_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008218, (_val))
#define MODIFY_HL65_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008218, (_val), (_mask))

/* DFE VGA Control 5 Register */
#define READ_HL65_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008219, (_val))
#define WRITE_HL65_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008219, (_val))
#define MODIFY_HL65_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008219, (_val), (_mask))

/* DSC Analog Control 0 Register */
#define READ_HL65_DSC1B0_DSC_ANA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000821a, (_val))
#define WRITE_HL65_DSC1B0_DSC_ANA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000821a, (_val))
#define MODIFY_HL65_DSC1B0_DSC_ANA_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821a, (_val), (_mask))

/* DSC Analog Control 1 Register */
#define READ_HL65_DSC1B0_DSC_ANA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000821b, (_val))
#define WRITE_HL65_DSC1B0_DSC_ANA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000821b, (_val))
#define MODIFY_HL65_DSC1B0_DSC_ANA_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821b, (_val), (_mask))

/* DSC Analog Control 2 Register */
#define READ_HL65_DSC1B0_DSC_ANA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000821c, (_val))
#define WRITE_HL65_DSC1B0_DSC_ANA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000821c, (_val))
#define MODIFY_HL65_DSC1B0_DSC_ANA_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821c, (_val), (_mask))

/* DSC 100FX Control Register */
#define READ_HL65_DSC1B0_DSC_100FX_CTRLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000821d, (_val))
#define WRITE_HL65_DSC1B0_DSC_100FX_CTRLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000821d, (_val))
#define MODIFY_HL65_DSC1B0_DSC_100FX_CTRLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821d, (_val), (_mask))

/* DSC Analog Control 3 Register */
#define READ_HL65_DSC1B0_DSC_ANA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000821e, (_val))
#define WRITE_HL65_DSC1B0_DSC_ANA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000821e, (_val))
#define MODIFY_HL65_DSC1B0_DSC_ANA_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc1b1
 ***************************************************************************/

/* CDR Control 0 Register */
#define READ_HL65_DSC1B1_CDR_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008220, (_val))
#define WRITE_HL65_DSC1B1_CDR_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008220, (_val))
#define MODIFY_HL65_DSC1B1_CDR_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008220, (_val), (_mask))

/* CDR Control 1 Register */
#define READ_HL65_DSC1B1_CDR_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008221, (_val))
#define WRITE_HL65_DSC1B1_CDR_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008221, (_val))
#define MODIFY_HL65_DSC1B1_CDR_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008221, (_val), (_mask))

/* CDR Control 2 Register */
#define READ_HL65_DSC1B1_CDR_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008222, (_val))
#define WRITE_HL65_DSC1B1_CDR_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008222, (_val))
#define MODIFY_HL65_DSC1B1_CDR_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008222, (_val), (_mask))

/* Phase Interpolator  Control 0 Register */
#define READ_HL65_DSC1B1_PI_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008223, (_val))
#define WRITE_HL65_DSC1B1_PI_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008223, (_val))
#define MODIFY_HL65_DSC1B1_PI_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008223, (_val), (_mask))

/* DFE VGA Control 0 Register */
#define READ_HL65_DSC1B1_DFE_VGA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008224, (_val))
#define WRITE_HL65_DSC1B1_DFE_VGA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008224, (_val))
#define MODIFY_HL65_DSC1B1_DFE_VGA_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008224, (_val), (_mask))

/* DFE VGA Control 1 Register */
#define READ_HL65_DSC1B1_DFE_VGA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008225, (_val))
#define WRITE_HL65_DSC1B1_DFE_VGA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008225, (_val))
#define MODIFY_HL65_DSC1B1_DFE_VGA_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008225, (_val), (_mask))

/* DFE VGA Control 2 Register */
#define READ_HL65_DSC1B1_DFE_VGA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008226, (_val))
#define WRITE_HL65_DSC1B1_DFE_VGA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008226, (_val))
#define MODIFY_HL65_DSC1B1_DFE_VGA_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008226, (_val), (_mask))

/* DFE VGA Control 3 Register */
#define READ_HL65_DSC1B1_DFE_VGA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008227, (_val))
#define WRITE_HL65_DSC1B1_DFE_VGA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008227, (_val))
#define MODIFY_HL65_DSC1B1_DFE_VGA_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008227, (_val), (_mask))

/* DFE VGA Control 4 Register */
#define READ_HL65_DSC1B1_DFE_VGA_CTRL4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008228, (_val))
#define WRITE_HL65_DSC1B1_DFE_VGA_CTRL4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008228, (_val))
#define MODIFY_HL65_DSC1B1_DFE_VGA_CTRL4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008228, (_val), (_mask))

/* DFE VGA Control 5 Register */
#define READ_HL65_DSC1B1_DFE_VGA_CTRL5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008229, (_val))
#define WRITE_HL65_DSC1B1_DFE_VGA_CTRL5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008229, (_val))
#define MODIFY_HL65_DSC1B1_DFE_VGA_CTRL5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008229, (_val), (_mask))

/* DSC Analog Control 0 Register */
#define READ_HL65_DSC1B1_DSC_ANA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000822a, (_val))
#define WRITE_HL65_DSC1B1_DSC_ANA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000822a, (_val))
#define MODIFY_HL65_DSC1B1_DSC_ANA_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822a, (_val), (_mask))

/* DSC Analog Control 1 Register */
#define READ_HL65_DSC1B1_DSC_ANA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000822b, (_val))
#define WRITE_HL65_DSC1B1_DSC_ANA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000822b, (_val))
#define MODIFY_HL65_DSC1B1_DSC_ANA_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822b, (_val), (_mask))

/* DSC Analog Control 2 Register */
#define READ_HL65_DSC1B1_DSC_ANA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000822c, (_val))
#define WRITE_HL65_DSC1B1_DSC_ANA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000822c, (_val))
#define MODIFY_HL65_DSC1B1_DSC_ANA_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822c, (_val), (_mask))

/* DSC 100FX Control Register */
#define READ_HL65_DSC1B1_DSC_100FX_CTRLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000822d, (_val))
#define WRITE_HL65_DSC1B1_DSC_100FX_CTRLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000822d, (_val))
#define MODIFY_HL65_DSC1B1_DSC_100FX_CTRLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822d, (_val), (_mask))

/* DSC Analog Control 3 Register */
#define READ_HL65_DSC1B1_DSC_ANA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000822e, (_val))
#define WRITE_HL65_DSC1B1_DSC_ANA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000822e, (_val))
#define MODIFY_HL65_DSC1B1_DSC_ANA_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc1b2
 ***************************************************************************/

/* CDR Control 0 Register */
#define READ_HL65_DSC1B2_CDR_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008230, (_val))
#define WRITE_HL65_DSC1B2_CDR_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008230, (_val))
#define MODIFY_HL65_DSC1B2_CDR_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008230, (_val), (_mask))

/* CDR Control 1 Register */
#define READ_HL65_DSC1B2_CDR_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008231, (_val))
#define WRITE_HL65_DSC1B2_CDR_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008231, (_val))
#define MODIFY_HL65_DSC1B2_CDR_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008231, (_val), (_mask))

/* CDR Control 2 Register */
#define READ_HL65_DSC1B2_CDR_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008232, (_val))
#define WRITE_HL65_DSC1B2_CDR_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008232, (_val))
#define MODIFY_HL65_DSC1B2_CDR_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008232, (_val), (_mask))

/* Phase Interpolator  Control 0 Register */
#define READ_HL65_DSC1B2_PI_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008233, (_val))
#define WRITE_HL65_DSC1B2_PI_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008233, (_val))
#define MODIFY_HL65_DSC1B2_PI_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008233, (_val), (_mask))

/* DFE VGA Control 0 Register */
#define READ_HL65_DSC1B2_DFE_VGA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008234, (_val))
#define WRITE_HL65_DSC1B2_DFE_VGA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008234, (_val))
#define MODIFY_HL65_DSC1B2_DFE_VGA_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008234, (_val), (_mask))

/* DFE VGA Control 1 Register */
#define READ_HL65_DSC1B2_DFE_VGA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008235, (_val))
#define WRITE_HL65_DSC1B2_DFE_VGA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008235, (_val))
#define MODIFY_HL65_DSC1B2_DFE_VGA_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008235, (_val), (_mask))

/* DFE VGA Control 2 Register */
#define READ_HL65_DSC1B2_DFE_VGA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008236, (_val))
#define WRITE_HL65_DSC1B2_DFE_VGA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008236, (_val))
#define MODIFY_HL65_DSC1B2_DFE_VGA_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008236, (_val), (_mask))

/* DFE VGA Control 3 Register */
#define READ_HL65_DSC1B2_DFE_VGA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008237, (_val))
#define WRITE_HL65_DSC1B2_DFE_VGA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008237, (_val))
#define MODIFY_HL65_DSC1B2_DFE_VGA_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008237, (_val), (_mask))

/* DFE VGA Control 4 Register */
#define READ_HL65_DSC1B2_DFE_VGA_CTRL4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008238, (_val))
#define WRITE_HL65_DSC1B2_DFE_VGA_CTRL4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008238, (_val))
#define MODIFY_HL65_DSC1B2_DFE_VGA_CTRL4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008238, (_val), (_mask))

/* DFE VGA Control 5 Register */
#define READ_HL65_DSC1B2_DFE_VGA_CTRL5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008239, (_val))
#define WRITE_HL65_DSC1B2_DFE_VGA_CTRL5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008239, (_val))
#define MODIFY_HL65_DSC1B2_DFE_VGA_CTRL5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008239, (_val), (_mask))

/* DSC Analog Control 0 Register */
#define READ_HL65_DSC1B2_DSC_ANA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000823a, (_val))
#define WRITE_HL65_DSC1B2_DSC_ANA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000823a, (_val))
#define MODIFY_HL65_DSC1B2_DSC_ANA_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823a, (_val), (_mask))

/* DSC Analog Control 1 Register */
#define READ_HL65_DSC1B2_DSC_ANA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000823b, (_val))
#define WRITE_HL65_DSC1B2_DSC_ANA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000823b, (_val))
#define MODIFY_HL65_DSC1B2_DSC_ANA_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823b, (_val), (_mask))

/* DSC Analog Control 2 Register */
#define READ_HL65_DSC1B2_DSC_ANA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000823c, (_val))
#define WRITE_HL65_DSC1B2_DSC_ANA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000823c, (_val))
#define MODIFY_HL65_DSC1B2_DSC_ANA_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823c, (_val), (_mask))

/* DSC 100FX Control Register */
#define READ_HL65_DSC1B2_DSC_100FX_CTRLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000823d, (_val))
#define WRITE_HL65_DSC1B2_DSC_100FX_CTRLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000823d, (_val))
#define MODIFY_HL65_DSC1B2_DSC_100FX_CTRLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823d, (_val), (_mask))

/* DSC Analog Control 3 Register */
#define READ_HL65_DSC1B2_DSC_ANA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000823e, (_val))
#define WRITE_HL65_DSC1B2_DSC_ANA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000823e, (_val))
#define MODIFY_HL65_DSC1B2_DSC_ANA_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc1b3
 ***************************************************************************/

/* CDR Control 0 Register */
#define READ_HL65_DSC1B3_CDR_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008240, (_val))
#define WRITE_HL65_DSC1B3_CDR_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008240, (_val))
#define MODIFY_HL65_DSC1B3_CDR_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008240, (_val), (_mask))

/* CDR Control 1 Register */
#define READ_HL65_DSC1B3_CDR_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008241, (_val))
#define WRITE_HL65_DSC1B3_CDR_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008241, (_val))
#define MODIFY_HL65_DSC1B3_CDR_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008241, (_val), (_mask))

/* CDR Control 2 Register */
#define READ_HL65_DSC1B3_CDR_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008242, (_val))
#define WRITE_HL65_DSC1B3_CDR_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008242, (_val))
#define MODIFY_HL65_DSC1B3_CDR_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008242, (_val), (_mask))

/* Phase Interpolator  Control 0 Register */
#define READ_HL65_DSC1B3_PI_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008243, (_val))
#define WRITE_HL65_DSC1B3_PI_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008243, (_val))
#define MODIFY_HL65_DSC1B3_PI_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008243, (_val), (_mask))

/* DFE VGA Control 0 Register */
#define READ_HL65_DSC1B3_DFE_VGA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008244, (_val))
#define WRITE_HL65_DSC1B3_DFE_VGA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008244, (_val))
#define MODIFY_HL65_DSC1B3_DFE_VGA_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008244, (_val), (_mask))

/* DFE VGA Control 1 Register */
#define READ_HL65_DSC1B3_DFE_VGA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008245, (_val))
#define WRITE_HL65_DSC1B3_DFE_VGA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008245, (_val))
#define MODIFY_HL65_DSC1B3_DFE_VGA_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008245, (_val), (_mask))

/* DFE VGA Control 2 Register */
#define READ_HL65_DSC1B3_DFE_VGA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008246, (_val))
#define WRITE_HL65_DSC1B3_DFE_VGA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008246, (_val))
#define MODIFY_HL65_DSC1B3_DFE_VGA_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008246, (_val), (_mask))

/* DFE VGA Control 3 Register */
#define READ_HL65_DSC1B3_DFE_VGA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008247, (_val))
#define WRITE_HL65_DSC1B3_DFE_VGA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008247, (_val))
#define MODIFY_HL65_DSC1B3_DFE_VGA_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008247, (_val), (_mask))

/* DFE VGA Control 4 Register */
#define READ_HL65_DSC1B3_DFE_VGA_CTRL4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008248, (_val))
#define WRITE_HL65_DSC1B3_DFE_VGA_CTRL4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008248, (_val))
#define MODIFY_HL65_DSC1B3_DFE_VGA_CTRL4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008248, (_val), (_mask))

/* DFE VGA Control 5 Register */
#define READ_HL65_DSC1B3_DFE_VGA_CTRL5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008249, (_val))
#define WRITE_HL65_DSC1B3_DFE_VGA_CTRL5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008249, (_val))
#define MODIFY_HL65_DSC1B3_DFE_VGA_CTRL5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008249, (_val), (_mask))

/* DSC Analog Control 0 Register */
#define READ_HL65_DSC1B3_DSC_ANA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000824a, (_val))
#define WRITE_HL65_DSC1B3_DSC_ANA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000824a, (_val))
#define MODIFY_HL65_DSC1B3_DSC_ANA_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000824a, (_val), (_mask))

/* DSC Analog Control 1 Register */
#define READ_HL65_DSC1B3_DSC_ANA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000824b, (_val))
#define WRITE_HL65_DSC1B3_DSC_ANA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000824b, (_val))
#define MODIFY_HL65_DSC1B3_DSC_ANA_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000824b, (_val), (_mask))

/* DSC Analog Control 2 Register */
#define READ_HL65_DSC1B3_DSC_ANA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000824c, (_val))
#define WRITE_HL65_DSC1B3_DSC_ANA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000824c, (_val))
#define MODIFY_HL65_DSC1B3_DSC_ANA_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000824c, (_val), (_mask))

/* DSC 100FX Control Register */
#define READ_HL65_DSC1B3_DSC_100FX_CTRLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000824d, (_val))
#define WRITE_HL65_DSC1B3_DSC_100FX_CTRLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000824d, (_val))
#define MODIFY_HL65_DSC1B3_DSC_100FX_CTRLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000824d, (_val), (_mask))

/* DSC Analog Control 3 Register */
#define READ_HL65_DSC1B3_DSC_ANA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000824e, (_val))
#define WRITE_HL65_DSC1B3_DSC_ANA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000824e, (_val))
#define MODIFY_HL65_DSC1B3_DSC_ANA_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000824e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc1bB
 ***************************************************************************/

/* CDR Control 0 Register */
#define READ_HL65_DSC1BB_CDR_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008250, (_val))
#define WRITE_HL65_DSC1BB_CDR_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008250, (_val))
#define MODIFY_HL65_DSC1BB_CDR_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008250, (_val), (_mask))

/* CDR Control 1 Register */
#define READ_HL65_DSC1BB_CDR_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008251, (_val))
#define WRITE_HL65_DSC1BB_CDR_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008251, (_val))
#define MODIFY_HL65_DSC1BB_CDR_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008251, (_val), (_mask))

/* CDR Control 2 Register */
#define READ_HL65_DSC1BB_CDR_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008252, (_val))
#define WRITE_HL65_DSC1BB_CDR_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008252, (_val))
#define MODIFY_HL65_DSC1BB_CDR_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008252, (_val), (_mask))

/* Phase Interpolator  Control 0 Register */
#define READ_HL65_DSC1BB_PI_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008253, (_val))
#define WRITE_HL65_DSC1BB_PI_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008253, (_val))
#define MODIFY_HL65_DSC1BB_PI_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008253, (_val), (_mask))

/* DFE VGA Control 0 Register */
#define READ_HL65_DSC1BB_DFE_VGA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008254, (_val))
#define WRITE_HL65_DSC1BB_DFE_VGA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008254, (_val))
#define MODIFY_HL65_DSC1BB_DFE_VGA_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008254, (_val), (_mask))

/* DFE VGA Control 1 Register */
#define READ_HL65_DSC1BB_DFE_VGA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008255, (_val))
#define WRITE_HL65_DSC1BB_DFE_VGA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008255, (_val))
#define MODIFY_HL65_DSC1BB_DFE_VGA_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008255, (_val), (_mask))

/* DFE VGA Control 2 Register */
#define READ_HL65_DSC1BB_DFE_VGA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008256, (_val))
#define WRITE_HL65_DSC1BB_DFE_VGA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008256, (_val))
#define MODIFY_HL65_DSC1BB_DFE_VGA_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008256, (_val), (_mask))

/* DFE VGA Control 3 Register */
#define READ_HL65_DSC1BB_DFE_VGA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008257, (_val))
#define WRITE_HL65_DSC1BB_DFE_VGA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008257, (_val))
#define MODIFY_HL65_DSC1BB_DFE_VGA_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008257, (_val), (_mask))

/* DFE VGA Control 4 Register */
#define READ_HL65_DSC1BB_DFE_VGA_CTRL4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008258, (_val))
#define WRITE_HL65_DSC1BB_DFE_VGA_CTRL4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008258, (_val))
#define MODIFY_HL65_DSC1BB_DFE_VGA_CTRL4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008258, (_val), (_mask))

/* DFE VGA Control 5 Register */
#define READ_HL65_DSC1BB_DFE_VGA_CTRL5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008259, (_val))
#define WRITE_HL65_DSC1BB_DFE_VGA_CTRL5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008259, (_val))
#define MODIFY_HL65_DSC1BB_DFE_VGA_CTRL5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008259, (_val), (_mask))

/* DSC Analog Control 0 Register */
#define READ_HL65_DSC1BB_DSC_ANA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000825a, (_val))
#define WRITE_HL65_DSC1BB_DSC_ANA_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000825a, (_val))
#define MODIFY_HL65_DSC1BB_DSC_ANA_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000825a, (_val), (_mask))

/* DSC Analog Control 1 Register */
#define READ_HL65_DSC1BB_DSC_ANA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000825b, (_val))
#define WRITE_HL65_DSC1BB_DSC_ANA_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000825b, (_val))
#define MODIFY_HL65_DSC1BB_DSC_ANA_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000825b, (_val), (_mask))

/* DSC Analog Control 2 Register */
#define READ_HL65_DSC1BB_DSC_ANA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000825c, (_val))
#define WRITE_HL65_DSC1BB_DSC_ANA_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000825c, (_val))
#define MODIFY_HL65_DSC1BB_DSC_ANA_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000825c, (_val), (_mask))

/* DSC 100FX Control Register */
#define READ_HL65_DSC1BB_DSC_100FX_CTRLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000825d, (_val))
#define WRITE_HL65_DSC1BB_DSC_100FX_CTRLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000825d, (_val))
#define MODIFY_HL65_DSC1BB_DSC_100FX_CTRLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000825d, (_val), (_mask))

/* DSC Analog Control 3 Register */
#define READ_HL65_DSC1BB_DSC_ANA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000825e, (_val))
#define WRITE_HL65_DSC1BB_DSC_ANA_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000825e, (_val))
#define MODIFY_HL65_DSC1BB_DSC_ANA_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000825e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc2b0
 ***************************************************************************/

/* State Machine Control 0 Register */
#define READ_HL65_DSC2B0_SM_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008260, (_val))
#define WRITE_HL65_DSC2B0_SM_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008260, (_val))
#define MODIFY_HL65_DSC2B0_SM_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008260, (_val), (_mask))

/* State Machine Control 1 Register */
#define READ_HL65_DSC2B0_SM_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008261, (_val))
#define WRITE_HL65_DSC2B0_SM_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008261, (_val))
#define MODIFY_HL65_DSC2B0_SM_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008261, (_val), (_mask))

/* State Machine Control 2 Register */
#define READ_HL65_DSC2B0_SM_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008262, (_val))
#define WRITE_HL65_DSC2B0_SM_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008262, (_val))
#define MODIFY_HL65_DSC2B0_SM_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008262, (_val), (_mask))

/* State Machine Control 3 Register */
#define READ_HL65_DSC2B0_SM_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008263, (_val))
#define WRITE_HL65_DSC2B0_SM_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008263, (_val))
#define MODIFY_HL65_DSC2B0_SM_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008263, (_val), (_mask))

/* State Machine Control 4 Register */
#define READ_HL65_DSC2B0_SM_CTRL4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008264, (_val))
#define WRITE_HL65_DSC2B0_SM_CTRL4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008264, (_val))
#define MODIFY_HL65_DSC2B0_SM_CTRL4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008264, (_val), (_mask))

/* State Machine Control 5 Register */
#define READ_HL65_DSC2B0_SM_CTRL5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008265, (_val))
#define WRITE_HL65_DSC2B0_SM_CTRL5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008265, (_val))
#define MODIFY_HL65_DSC2B0_SM_CTRL5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008265, (_val), (_mask))

/* State Machine Control 6 Register */
#define READ_HL65_DSC2B0_SM_CTRL6r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008266, (_val))
#define WRITE_HL65_DSC2B0_SM_CTRL6r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008266, (_val))
#define MODIFY_HL65_DSC2B0_SM_CTRL6r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008266, (_val), (_mask))

/* State Machine Control 7 Register */
#define READ_HL65_DSC2B0_SM_CTRL7r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008267, (_val))
#define WRITE_HL65_DSC2B0_SM_CTRL7r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008267, (_val))
#define MODIFY_HL65_DSC2B0_SM_CTRL7r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008267, (_val), (_mask))

/* State Machine Control 8 Register */
#define READ_HL65_DSC2B0_SM_CTRL8r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008268, (_val))
#define WRITE_HL65_DSC2B0_SM_CTRL8r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008268, (_val))
#define MODIFY_HL65_DSC2B0_SM_CTRL8r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008268, (_val), (_mask))

/* State Machine Control 9 Register */
#define READ_HL65_DSC2B0_SM_CTRL9r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008269, (_val))
#define WRITE_HL65_DSC2B0_SM_CTRL9r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008269, (_val))
#define MODIFY_HL65_DSC2B0_SM_CTRL9r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008269, (_val), (_mask))

/* State Machine Control 10 Register */
#define READ_HL65_DSC2B0_SM_CTRL10r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000826a, (_val))
#define WRITE_HL65_DSC2B0_SM_CTRL10r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000826a, (_val))
#define MODIFY_HL65_DSC2B0_SM_CTRL10r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000826a, (_val), (_mask))

/* State Machine Control 11 Register */
#define READ_HL65_DSC2B0_SM_CTRL11r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000826b, (_val))
#define WRITE_HL65_DSC2B0_SM_CTRL11r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000826b, (_val))
#define MODIFY_HL65_DSC2B0_SM_CTRL11r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000826b, (_val), (_mask))

/* State Machine Control 12 Register */
#define READ_HL65_DSC2B0_SM_CTRL12r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000826c, (_val))
#define WRITE_HL65_DSC2B0_SM_CTRL12r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000826c, (_val))
#define MODIFY_HL65_DSC2B0_SM_CTRL12r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000826c, (_val), (_mask))

/* DSC Diagnostics Control 0 Register */
#define READ_HL65_DSC2B0_DSC_DIAG_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000826d, (_val))
#define WRITE_HL65_DSC2B0_DSC_DIAG_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000826d, (_val))
#define MODIFY_HL65_DSC2B0_DSC_DIAG_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000826d, (_val), (_mask))

/* DSC Misc Control 0 Register */
#define READ_HL65_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000826e, (_val))
#define WRITE_HL65_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000826e, (_val))
#define MODIFY_HL65_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000826e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc2b1
 ***************************************************************************/

/* State Machine Control 0 Register */
#define READ_HL65_DSC2B1_SM_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008270, (_val))
#define WRITE_HL65_DSC2B1_SM_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008270, (_val))
#define MODIFY_HL65_DSC2B1_SM_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008270, (_val), (_mask))

/* State Machine Control 1 Register */
#define READ_HL65_DSC2B1_SM_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008271, (_val))
#define WRITE_HL65_DSC2B1_SM_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008271, (_val))
#define MODIFY_HL65_DSC2B1_SM_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008271, (_val), (_mask))

/* State Machine Control 2 Register */
#define READ_HL65_DSC2B1_SM_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008272, (_val))
#define WRITE_HL65_DSC2B1_SM_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008272, (_val))
#define MODIFY_HL65_DSC2B1_SM_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008272, (_val), (_mask))

/* State Machine Control 3 Register */
#define READ_HL65_DSC2B1_SM_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008273, (_val))
#define WRITE_HL65_DSC2B1_SM_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008273, (_val))
#define MODIFY_HL65_DSC2B1_SM_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008273, (_val), (_mask))

/* State Machine Control 4 Register */
#define READ_HL65_DSC2B1_SM_CTRL4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008274, (_val))
#define WRITE_HL65_DSC2B1_SM_CTRL4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008274, (_val))
#define MODIFY_HL65_DSC2B1_SM_CTRL4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008274, (_val), (_mask))

/* State Machine Control 5 Register */
#define READ_HL65_DSC2B1_SM_CTRL5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008275, (_val))
#define WRITE_HL65_DSC2B1_SM_CTRL5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008275, (_val))
#define MODIFY_HL65_DSC2B1_SM_CTRL5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008275, (_val), (_mask))

/* State Machine Control 6 Register */
#define READ_HL65_DSC2B1_SM_CTRL6r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008276, (_val))
#define WRITE_HL65_DSC2B1_SM_CTRL6r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008276, (_val))
#define MODIFY_HL65_DSC2B1_SM_CTRL6r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008276, (_val), (_mask))

/* State Machine Control 7 Register */
#define READ_HL65_DSC2B1_SM_CTRL7r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008277, (_val))
#define WRITE_HL65_DSC2B1_SM_CTRL7r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008277, (_val))
#define MODIFY_HL65_DSC2B1_SM_CTRL7r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008277, (_val), (_mask))

/* State Machine Control 8 Register */
#define READ_HL65_DSC2B1_SM_CTRL8r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008278, (_val))
#define WRITE_HL65_DSC2B1_SM_CTRL8r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008278, (_val))
#define MODIFY_HL65_DSC2B1_SM_CTRL8r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008278, (_val), (_mask))

/* State Machine Control 9 Register */
#define READ_HL65_DSC2B1_SM_CTRL9r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008279, (_val))
#define WRITE_HL65_DSC2B1_SM_CTRL9r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008279, (_val))
#define MODIFY_HL65_DSC2B1_SM_CTRL9r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008279, (_val), (_mask))

/* State Machine Control 10 Register */
#define READ_HL65_DSC2B1_SM_CTRL10r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000827a, (_val))
#define WRITE_HL65_DSC2B1_SM_CTRL10r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000827a, (_val))
#define MODIFY_HL65_DSC2B1_SM_CTRL10r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000827a, (_val), (_mask))

/* State Machine Control 11 Register */
#define READ_HL65_DSC2B1_SM_CTRL11r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000827b, (_val))
#define WRITE_HL65_DSC2B1_SM_CTRL11r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000827b, (_val))
#define MODIFY_HL65_DSC2B1_SM_CTRL11r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000827b, (_val), (_mask))

/* State Machine Control 12 Register */
#define READ_HL65_DSC2B1_SM_CTRL12r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000827c, (_val))
#define WRITE_HL65_DSC2B1_SM_CTRL12r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000827c, (_val))
#define MODIFY_HL65_DSC2B1_SM_CTRL12r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000827c, (_val), (_mask))

/* DSC Diagnostics Control 0 Register */
#define READ_HL65_DSC2B1_DSC_DIAG_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000827d, (_val))
#define WRITE_HL65_DSC2B1_DSC_DIAG_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000827d, (_val))
#define MODIFY_HL65_DSC2B1_DSC_DIAG_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000827d, (_val), (_mask))

/* DSC Misc Control 0 Register */
#define READ_HL65_DSC2B1_DSC_MISC_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000827e, (_val))
#define WRITE_HL65_DSC2B1_DSC_MISC_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000827e, (_val))
#define MODIFY_HL65_DSC2B1_DSC_MISC_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000827e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc2b2
 ***************************************************************************/

/* State Machine Control 0 Register */
#define READ_HL65_DSC2B2_SM_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008280, (_val))
#define WRITE_HL65_DSC2B2_SM_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008280, (_val))
#define MODIFY_HL65_DSC2B2_SM_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008280, (_val), (_mask))

/* State Machine Control 1 Register */
#define READ_HL65_DSC2B2_SM_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008281, (_val))
#define WRITE_HL65_DSC2B2_SM_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008281, (_val))
#define MODIFY_HL65_DSC2B2_SM_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008281, (_val), (_mask))

/* State Machine Control 2 Register */
#define READ_HL65_DSC2B2_SM_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008282, (_val))
#define WRITE_HL65_DSC2B2_SM_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008282, (_val))
#define MODIFY_HL65_DSC2B2_SM_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008282, (_val), (_mask))

/* State Machine Control 3 Register */
#define READ_HL65_DSC2B2_SM_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008283, (_val))
#define WRITE_HL65_DSC2B2_SM_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008283, (_val))
#define MODIFY_HL65_DSC2B2_SM_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008283, (_val), (_mask))

/* State Machine Control 4 Register */
#define READ_HL65_DSC2B2_SM_CTRL4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008284, (_val))
#define WRITE_HL65_DSC2B2_SM_CTRL4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008284, (_val))
#define MODIFY_HL65_DSC2B2_SM_CTRL4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008284, (_val), (_mask))

/* State Machine Control 5 Register */
#define READ_HL65_DSC2B2_SM_CTRL5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008285, (_val))
#define WRITE_HL65_DSC2B2_SM_CTRL5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008285, (_val))
#define MODIFY_HL65_DSC2B2_SM_CTRL5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008285, (_val), (_mask))

/* State Machine Control 6 Register */
#define READ_HL65_DSC2B2_SM_CTRL6r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008286, (_val))
#define WRITE_HL65_DSC2B2_SM_CTRL6r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008286, (_val))
#define MODIFY_HL65_DSC2B2_SM_CTRL6r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008286, (_val), (_mask))

/* State Machine Control 7 Register */
#define READ_HL65_DSC2B2_SM_CTRL7r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008287, (_val))
#define WRITE_HL65_DSC2B2_SM_CTRL7r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008287, (_val))
#define MODIFY_HL65_DSC2B2_SM_CTRL7r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008287, (_val), (_mask))

/* State Machine Control 8 Register */
#define READ_HL65_DSC2B2_SM_CTRL8r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008288, (_val))
#define WRITE_HL65_DSC2B2_SM_CTRL8r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008288, (_val))
#define MODIFY_HL65_DSC2B2_SM_CTRL8r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008288, (_val), (_mask))

/* State Machine Control 9 Register */
#define READ_HL65_DSC2B2_SM_CTRL9r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008289, (_val))
#define WRITE_HL65_DSC2B2_SM_CTRL9r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008289, (_val))
#define MODIFY_HL65_DSC2B2_SM_CTRL9r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008289, (_val), (_mask))

/* State Machine Control 10 Register */
#define READ_HL65_DSC2B2_SM_CTRL10r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000828a, (_val))
#define WRITE_HL65_DSC2B2_SM_CTRL10r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000828a, (_val))
#define MODIFY_HL65_DSC2B2_SM_CTRL10r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000828a, (_val), (_mask))

/* State Machine Control 11 Register */
#define READ_HL65_DSC2B2_SM_CTRL11r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000828b, (_val))
#define WRITE_HL65_DSC2B2_SM_CTRL11r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000828b, (_val))
#define MODIFY_HL65_DSC2B2_SM_CTRL11r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000828b, (_val), (_mask))

/* State Machine Control 12 Register */
#define READ_HL65_DSC2B2_SM_CTRL12r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000828c, (_val))
#define WRITE_HL65_DSC2B2_SM_CTRL12r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000828c, (_val))
#define MODIFY_HL65_DSC2B2_SM_CTRL12r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000828c, (_val), (_mask))

/* DSC Diagnostics Control 0 Register */
#define READ_HL65_DSC2B2_DSC_DIAG_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000828d, (_val))
#define WRITE_HL65_DSC2B2_DSC_DIAG_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000828d, (_val))
#define MODIFY_HL65_DSC2B2_DSC_DIAG_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000828d, (_val), (_mask))

/* DSC Misc Control 0 Register */
#define READ_HL65_DSC2B2_DSC_MISC_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000828e, (_val))
#define WRITE_HL65_DSC2B2_DSC_MISC_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000828e, (_val))
#define MODIFY_HL65_DSC2B2_DSC_MISC_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000828e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc2b3
 ***************************************************************************/

/* State Machine Control 0 Register */
#define READ_HL65_DSC2B3_SM_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008290, (_val))
#define WRITE_HL65_DSC2B3_SM_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008290, (_val))
#define MODIFY_HL65_DSC2B3_SM_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008290, (_val), (_mask))

/* State Machine Control 1 Register */
#define READ_HL65_DSC2B3_SM_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008291, (_val))
#define WRITE_HL65_DSC2B3_SM_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008291, (_val))
#define MODIFY_HL65_DSC2B3_SM_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008291, (_val), (_mask))

/* State Machine Control 2 Register */
#define READ_HL65_DSC2B3_SM_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008292, (_val))
#define WRITE_HL65_DSC2B3_SM_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008292, (_val))
#define MODIFY_HL65_DSC2B3_SM_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008292, (_val), (_mask))

/* State Machine Control 3 Register */
#define READ_HL65_DSC2B3_SM_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008293, (_val))
#define WRITE_HL65_DSC2B3_SM_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008293, (_val))
#define MODIFY_HL65_DSC2B3_SM_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008293, (_val), (_mask))

/* State Machine Control 4 Register */
#define READ_HL65_DSC2B3_SM_CTRL4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008294, (_val))
#define WRITE_HL65_DSC2B3_SM_CTRL4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008294, (_val))
#define MODIFY_HL65_DSC2B3_SM_CTRL4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008294, (_val), (_mask))

/* State Machine Control 5 Register */
#define READ_HL65_DSC2B3_SM_CTRL5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008295, (_val))
#define WRITE_HL65_DSC2B3_SM_CTRL5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008295, (_val))
#define MODIFY_HL65_DSC2B3_SM_CTRL5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008295, (_val), (_mask))

/* State Machine Control 6 Register */
#define READ_HL65_DSC2B3_SM_CTRL6r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008296, (_val))
#define WRITE_HL65_DSC2B3_SM_CTRL6r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008296, (_val))
#define MODIFY_HL65_DSC2B3_SM_CTRL6r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008296, (_val), (_mask))

/* State Machine Control 7 Register */
#define READ_HL65_DSC2B3_SM_CTRL7r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008297, (_val))
#define WRITE_HL65_DSC2B3_SM_CTRL7r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008297, (_val))
#define MODIFY_HL65_DSC2B3_SM_CTRL7r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008297, (_val), (_mask))

/* State Machine Control 8 Register */
#define READ_HL65_DSC2B3_SM_CTRL8r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008298, (_val))
#define WRITE_HL65_DSC2B3_SM_CTRL8r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008298, (_val))
#define MODIFY_HL65_DSC2B3_SM_CTRL8r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008298, (_val), (_mask))

/* State Machine Control 9 Register */
#define READ_HL65_DSC2B3_SM_CTRL9r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008299, (_val))
#define WRITE_HL65_DSC2B3_SM_CTRL9r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008299, (_val))
#define MODIFY_HL65_DSC2B3_SM_CTRL9r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008299, (_val), (_mask))

/* State Machine Control 10 Register */
#define READ_HL65_DSC2B3_SM_CTRL10r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000829a, (_val))
#define WRITE_HL65_DSC2B3_SM_CTRL10r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000829a, (_val))
#define MODIFY_HL65_DSC2B3_SM_CTRL10r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000829a, (_val), (_mask))

/* State Machine Control 11 Register */
#define READ_HL65_DSC2B3_SM_CTRL11r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000829b, (_val))
#define WRITE_HL65_DSC2B3_SM_CTRL11r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000829b, (_val))
#define MODIFY_HL65_DSC2B3_SM_CTRL11r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000829b, (_val), (_mask))

/* State Machine Control 12 Register */
#define READ_HL65_DSC2B3_SM_CTRL12r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000829c, (_val))
#define WRITE_HL65_DSC2B3_SM_CTRL12r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000829c, (_val))
#define MODIFY_HL65_DSC2B3_SM_CTRL12r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000829c, (_val), (_mask))

/* DSC Diagnostics Control 0 Register */
#define READ_HL65_DSC2B3_DSC_DIAG_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000829d, (_val))
#define WRITE_HL65_DSC2B3_DSC_DIAG_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000829d, (_val))
#define MODIFY_HL65_DSC2B3_DSC_DIAG_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000829d, (_val), (_mask))

/* DSC Misc Control 0 Register */
#define READ_HL65_DSC2B3_DSC_MISC_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000829e, (_val))
#define WRITE_HL65_DSC2B3_DSC_MISC_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000829e, (_val))
#define MODIFY_HL65_DSC2B3_DSC_MISC_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000829e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc2bB
 ***************************************************************************/

/* State Machine Control 0 Register */
#define READ_HL65_DSC2BB_SM_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a0, (_val))
#define WRITE_HL65_DSC2BB_SM_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a0, (_val))
#define MODIFY_HL65_DSC2BB_SM_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a0, (_val), (_mask))

/* State Machine Control 1 Register */
#define READ_HL65_DSC2BB_SM_CTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a1, (_val))
#define WRITE_HL65_DSC2BB_SM_CTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a1, (_val))
#define MODIFY_HL65_DSC2BB_SM_CTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a1, (_val), (_mask))

/* State Machine Control 2 Register */
#define READ_HL65_DSC2BB_SM_CTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a2, (_val))
#define WRITE_HL65_DSC2BB_SM_CTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a2, (_val))
#define MODIFY_HL65_DSC2BB_SM_CTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a2, (_val), (_mask))

/* State Machine Control 3 Register */
#define READ_HL65_DSC2BB_SM_CTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a3, (_val))
#define WRITE_HL65_DSC2BB_SM_CTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a3, (_val))
#define MODIFY_HL65_DSC2BB_SM_CTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a3, (_val), (_mask))

/* State Machine Control 4 Register */
#define READ_HL65_DSC2BB_SM_CTRL4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a4, (_val))
#define WRITE_HL65_DSC2BB_SM_CTRL4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a4, (_val))
#define MODIFY_HL65_DSC2BB_SM_CTRL4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a4, (_val), (_mask))

/* State Machine Control 5 Register */
#define READ_HL65_DSC2BB_SM_CTRL5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a5, (_val))
#define WRITE_HL65_DSC2BB_SM_CTRL5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a5, (_val))
#define MODIFY_HL65_DSC2BB_SM_CTRL5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a5, (_val), (_mask))

/* State Machine Control 6 Register */
#define READ_HL65_DSC2BB_SM_CTRL6r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a6, (_val))
#define WRITE_HL65_DSC2BB_SM_CTRL6r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a6, (_val))
#define MODIFY_HL65_DSC2BB_SM_CTRL6r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a6, (_val), (_mask))

/* State Machine Control 7 Register */
#define READ_HL65_DSC2BB_SM_CTRL7r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a7, (_val))
#define WRITE_HL65_DSC2BB_SM_CTRL7r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a7, (_val))
#define MODIFY_HL65_DSC2BB_SM_CTRL7r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a7, (_val), (_mask))

/* State Machine Control 8 Register */
#define READ_HL65_DSC2BB_SM_CTRL8r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a8, (_val))
#define WRITE_HL65_DSC2BB_SM_CTRL8r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a8, (_val))
#define MODIFY_HL65_DSC2BB_SM_CTRL8r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a8, (_val), (_mask))

/* State Machine Control 9 Register */
#define READ_HL65_DSC2BB_SM_CTRL9r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a9, (_val))
#define WRITE_HL65_DSC2BB_SM_CTRL9r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a9, (_val))
#define MODIFY_HL65_DSC2BB_SM_CTRL9r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a9, (_val), (_mask))

/* State Machine Control 10 Register */
#define READ_HL65_DSC2BB_SM_CTRL10r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082aa, (_val))
#define WRITE_HL65_DSC2BB_SM_CTRL10r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082aa, (_val))
#define MODIFY_HL65_DSC2BB_SM_CTRL10r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082aa, (_val), (_mask))

/* State Machine Control 11 Register */
#define READ_HL65_DSC2BB_SM_CTRL11r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ab, (_val))
#define WRITE_HL65_DSC2BB_SM_CTRL11r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ab, (_val))
#define MODIFY_HL65_DSC2BB_SM_CTRL11r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ab, (_val), (_mask))

/* State Machine Control 12 Register */
#define READ_HL65_DSC2BB_SM_CTRL12r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ac, (_val))
#define WRITE_HL65_DSC2BB_SM_CTRL12r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ac, (_val))
#define MODIFY_HL65_DSC2BB_SM_CTRL12r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ac, (_val), (_mask))

/* DSC Diagnostics Control 0 Register */
#define READ_HL65_DSC2BB_DSC_DIAG_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ad, (_val))
#define WRITE_HL65_DSC2BB_DSC_DIAG_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ad, (_val))
#define MODIFY_HL65_DSC2BB_DSC_DIAG_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ad, (_val), (_mask))

/* DSC Misc Control 0 Register */
#define READ_HL65_DSC2BB_DSC_MISC_CTRL0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ae, (_val))
#define WRITE_HL65_DSC2BB_DSC_MISC_CTRL0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ae, (_val))
#define MODIFY_HL65_DSC2BB_DSC_MISC_CTRL0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ae, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc3b0
 ***************************************************************************/

/* CDR Status 0 Register */
#define READ_HL65_DSC3B0_CDR_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b0, (_val))
#define WRITE_HL65_DSC3B0_CDR_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b0, (_val))
#define MODIFY_HL65_DSC3B0_CDR_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b0, (_val), (_mask))

/* CDR Status 1 Register */
#define READ_HL65_DSC3B0_CDR_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b1, (_val))
#define WRITE_HL65_DSC3B0_CDR_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b1, (_val))
#define MODIFY_HL65_DSC3B0_CDR_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b1, (_val), (_mask))

/* CDR Status 2 Register */
#define READ_HL65_DSC3B0_CDR_STATUS2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b2, (_val))
#define WRITE_HL65_DSC3B0_CDR_STATUS2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b2, (_val))
#define MODIFY_HL65_DSC3B0_CDR_STATUS2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b2, (_val), (_mask))

/* Phase Interpolator Status 0 Register */
#define READ_HL65_DSC3B0_PI_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b3, (_val))
#define WRITE_HL65_DSC3B0_PI_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b3, (_val))
#define MODIFY_HL65_DSC3B0_PI_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b3, (_val), (_mask))

/* Phase Interpolator Status 1 Register */
#define READ_HL65_DSC3B0_PI_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b4, (_val))
#define WRITE_HL65_DSC3B0_PI_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b4, (_val))
#define MODIFY_HL65_DSC3B0_PI_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b4, (_val), (_mask))

/* DFE VGA Status 0 Register */
#define READ_HL65_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b5, (_val))
#define WRITE_HL65_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b5, (_val))
#define MODIFY_HL65_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b5, (_val), (_mask))

/* DFE VGA Status 1 Register */
#define READ_HL65_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b6, (_val))
#define WRITE_HL65_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b6, (_val))
#define MODIFY_HL65_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b6, (_val), (_mask))

/* State Machine Status 0 Register */
#define READ_HL65_DSC3B0_SM_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b7, (_val))
#define WRITE_HL65_DSC3B0_SM_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b7, (_val))
#define MODIFY_HL65_DSC3B0_SM_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b7, (_val), (_mask))

/* State Machine Status 1 Register */
#define READ_HL65_DSC3B0_SM_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b8, (_val))
#define WRITE_HL65_DSC3B0_SM_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b8, (_val))
#define MODIFY_HL65_DSC3B0_SM_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b8, (_val), (_mask))

/* State Machine Status 2 Register */
#define READ_HL65_DSC3B0_SM_STATUS2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b9, (_val))
#define WRITE_HL65_DSC3B0_SM_STATUS2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b9, (_val))
#define MODIFY_HL65_DSC3B0_SM_STATUS2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b9, (_val), (_mask))

/* State Machine Status 3 Register */
#define READ_HL65_DSC3B0_SM_STATUS3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ba, (_val))
#define WRITE_HL65_DSC3B0_SM_STATUS3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ba, (_val))
#define MODIFY_HL65_DSC3B0_SM_STATUS3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ba, (_val), (_mask))

/* State Machine Status 4 Register */
#define READ_HL65_DSC3B0_SM_STATUS4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082bb, (_val))
#define WRITE_HL65_DSC3B0_SM_STATUS4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082bb, (_val))
#define MODIFY_HL65_DSC3B0_SM_STATUS4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082bb, (_val), (_mask))

/* DSC Analog Status 0 Register */
#define READ_HL65_DSC3B0_ANA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082bc, (_val))
#define WRITE_HL65_DSC3B0_ANA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082bc, (_val))
#define MODIFY_HL65_DSC3B0_ANA_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082bc, (_val), (_mask))

/* State Machine Status 5 Register */
#define READ_HL65_DSC3B0_SM_STATUS5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082bd, (_val))
#define WRITE_HL65_DSC3B0_SM_STATUS5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082bd, (_val))
#define MODIFY_HL65_DSC3B0_SM_STATUS5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082bd, (_val), (_mask))

/* State Machine Status 6 Register */
#define READ_HL65_DSC3B0_SM_STATUS6r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082be, (_val))
#define WRITE_HL65_DSC3B0_SM_STATUS6r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082be, (_val))
#define MODIFY_HL65_DSC3B0_SM_STATUS6r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082be, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc3b1
 ***************************************************************************/

/* CDR Status 0 Register */
#define READ_HL65_DSC3B1_CDR_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c0, (_val))
#define WRITE_HL65_DSC3B1_CDR_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c0, (_val))
#define MODIFY_HL65_DSC3B1_CDR_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c0, (_val), (_mask))

/* CDR Status 1 Register */
#define READ_HL65_DSC3B1_CDR_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c1, (_val))
#define WRITE_HL65_DSC3B1_CDR_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c1, (_val))
#define MODIFY_HL65_DSC3B1_CDR_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c1, (_val), (_mask))

/* CDR Status 2 Register */
#define READ_HL65_DSC3B1_CDR_STATUS2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c2, (_val))
#define WRITE_HL65_DSC3B1_CDR_STATUS2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c2, (_val))
#define MODIFY_HL65_DSC3B1_CDR_STATUS2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c2, (_val), (_mask))

/* Phase Interpolator Status 0 Register */
#define READ_HL65_DSC3B1_PI_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c3, (_val))
#define WRITE_HL65_DSC3B1_PI_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c3, (_val))
#define MODIFY_HL65_DSC3B1_PI_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c3, (_val), (_mask))

/* Phase Interpolator Status 1 Register */
#define READ_HL65_DSC3B1_PI_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c4, (_val))
#define WRITE_HL65_DSC3B1_PI_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c4, (_val))
#define MODIFY_HL65_DSC3B1_PI_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c4, (_val), (_mask))

/* DFE VGA Status 0 Register */
#define READ_HL65_DSC3B1_DFE_VGA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c5, (_val))
#define WRITE_HL65_DSC3B1_DFE_VGA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c5, (_val))
#define MODIFY_HL65_DSC3B1_DFE_VGA_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c5, (_val), (_mask))

/* DFE VGA Status 1 Register */
#define READ_HL65_DSC3B1_DFE_VGA_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c6, (_val))
#define WRITE_HL65_DSC3B1_DFE_VGA_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c6, (_val))
#define MODIFY_HL65_DSC3B1_DFE_VGA_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c6, (_val), (_mask))

/* State Machine Status 0 Register */
#define READ_HL65_DSC3B1_SM_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c7, (_val))
#define WRITE_HL65_DSC3B1_SM_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c7, (_val))
#define MODIFY_HL65_DSC3B1_SM_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c7, (_val), (_mask))

/* State Machine Status 1 Register */
#define READ_HL65_DSC3B1_SM_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c8, (_val))
#define WRITE_HL65_DSC3B1_SM_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c8, (_val))
#define MODIFY_HL65_DSC3B1_SM_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c8, (_val), (_mask))

/* State Machine Status 2 Register */
#define READ_HL65_DSC3B1_SM_STATUS2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c9, (_val))
#define WRITE_HL65_DSC3B1_SM_STATUS2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c9, (_val))
#define MODIFY_HL65_DSC3B1_SM_STATUS2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c9, (_val), (_mask))

/* State Machine Status 3 Register */
#define READ_HL65_DSC3B1_SM_STATUS3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ca, (_val))
#define WRITE_HL65_DSC3B1_SM_STATUS3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ca, (_val))
#define MODIFY_HL65_DSC3B1_SM_STATUS3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ca, (_val), (_mask))

/* State Machine Status 4 Register */
#define READ_HL65_DSC3B1_SM_STATUS4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082cb, (_val))
#define WRITE_HL65_DSC3B1_SM_STATUS4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082cb, (_val))
#define MODIFY_HL65_DSC3B1_SM_STATUS4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082cb, (_val), (_mask))

/* DSC Analog Status 0 Register */
#define READ_HL65_DSC3B1_ANA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082cc, (_val))
#define WRITE_HL65_DSC3B1_ANA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082cc, (_val))
#define MODIFY_HL65_DSC3B1_ANA_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082cc, (_val), (_mask))

/* State Machine Status 5 Register */
#define READ_HL65_DSC3B1_SM_STATUS5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082cd, (_val))
#define WRITE_HL65_DSC3B1_SM_STATUS5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082cd, (_val))
#define MODIFY_HL65_DSC3B1_SM_STATUS5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082cd, (_val), (_mask))

/* State Machine Status 6 Register */
#define READ_HL65_DSC3B1_SM_STATUS6r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ce, (_val))
#define WRITE_HL65_DSC3B1_SM_STATUS6r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ce, (_val))
#define MODIFY_HL65_DSC3B1_SM_STATUS6r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ce, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc3b2
 ***************************************************************************/

/* CDR Status 0 Register */
#define READ_HL65_DSC3B2_CDR_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d0, (_val))
#define WRITE_HL65_DSC3B2_CDR_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d0, (_val))
#define MODIFY_HL65_DSC3B2_CDR_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d0, (_val), (_mask))

/* CDR Status 1 Register */
#define READ_HL65_DSC3B2_CDR_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d1, (_val))
#define WRITE_HL65_DSC3B2_CDR_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d1, (_val))
#define MODIFY_HL65_DSC3B2_CDR_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d1, (_val), (_mask))

/* CDR Status 2 Register */
#define READ_HL65_DSC3B2_CDR_STATUS2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d2, (_val))
#define WRITE_HL65_DSC3B2_CDR_STATUS2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d2, (_val))
#define MODIFY_HL65_DSC3B2_CDR_STATUS2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d2, (_val), (_mask))

/* Phase Interpolator Status 0 Register */
#define READ_HL65_DSC3B2_PI_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d3, (_val))
#define WRITE_HL65_DSC3B2_PI_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d3, (_val))
#define MODIFY_HL65_DSC3B2_PI_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d3, (_val), (_mask))

/* Phase Interpolator Status 1 Register */
#define READ_HL65_DSC3B2_PI_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d4, (_val))
#define WRITE_HL65_DSC3B2_PI_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d4, (_val))
#define MODIFY_HL65_DSC3B2_PI_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d4, (_val), (_mask))

/* DFE VGA Status 0 Register */
#define READ_HL65_DSC3B2_DFE_VGA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d5, (_val))
#define WRITE_HL65_DSC3B2_DFE_VGA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d5, (_val))
#define MODIFY_HL65_DSC3B2_DFE_VGA_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d5, (_val), (_mask))

/* DFE VGA Status 1 Register */
#define READ_HL65_DSC3B2_DFE_VGA_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d6, (_val))
#define WRITE_HL65_DSC3B2_DFE_VGA_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d6, (_val))
#define MODIFY_HL65_DSC3B2_DFE_VGA_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d6, (_val), (_mask))

/* State Machine Status 0 Register */
#define READ_HL65_DSC3B2_SM_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d7, (_val))
#define WRITE_HL65_DSC3B2_SM_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d7, (_val))
#define MODIFY_HL65_DSC3B2_SM_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d7, (_val), (_mask))

/* State Machine Status 1 Register */
#define READ_HL65_DSC3B2_SM_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d8, (_val))
#define WRITE_HL65_DSC3B2_SM_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d8, (_val))
#define MODIFY_HL65_DSC3B2_SM_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d8, (_val), (_mask))

/* State Machine Status 2 Register */
#define READ_HL65_DSC3B2_SM_STATUS2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d9, (_val))
#define WRITE_HL65_DSC3B2_SM_STATUS2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d9, (_val))
#define MODIFY_HL65_DSC3B2_SM_STATUS2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d9, (_val), (_mask))

/* State Machine Status 3 Register */
#define READ_HL65_DSC3B2_SM_STATUS3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082da, (_val))
#define WRITE_HL65_DSC3B2_SM_STATUS3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082da, (_val))
#define MODIFY_HL65_DSC3B2_SM_STATUS3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082da, (_val), (_mask))

/* State Machine Status 4 Register */
#define READ_HL65_DSC3B2_SM_STATUS4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082db, (_val))
#define WRITE_HL65_DSC3B2_SM_STATUS4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082db, (_val))
#define MODIFY_HL65_DSC3B2_SM_STATUS4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082db, (_val), (_mask))

/* DSC Analog Status 0 Register */
#define READ_HL65_DSC3B2_ANA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082dc, (_val))
#define WRITE_HL65_DSC3B2_ANA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082dc, (_val))
#define MODIFY_HL65_DSC3B2_ANA_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082dc, (_val), (_mask))

/* State Machine Status 5 Register */
#define READ_HL65_DSC3B2_SM_STATUS5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082dd, (_val))
#define WRITE_HL65_DSC3B2_SM_STATUS5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082dd, (_val))
#define MODIFY_HL65_DSC3B2_SM_STATUS5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082dd, (_val), (_mask))

/* State Machine Status 6 Register */
#define READ_HL65_DSC3B2_SM_STATUS6r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082de, (_val))
#define WRITE_HL65_DSC3B2_SM_STATUS6r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082de, (_val))
#define MODIFY_HL65_DSC3B2_SM_STATUS6r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082de, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc3b3
 ***************************************************************************/

/* CDR Status 0 Register */
#define READ_HL65_DSC3B3_CDR_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e0, (_val))
#define WRITE_HL65_DSC3B3_CDR_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e0, (_val))
#define MODIFY_HL65_DSC3B3_CDR_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e0, (_val), (_mask))

/* CDR Status 1 Register */
#define READ_HL65_DSC3B3_CDR_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e1, (_val))
#define WRITE_HL65_DSC3B3_CDR_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e1, (_val))
#define MODIFY_HL65_DSC3B3_CDR_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e1, (_val), (_mask))

/* CDR Status 2 Register */
#define READ_HL65_DSC3B3_CDR_STATUS2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e2, (_val))
#define WRITE_HL65_DSC3B3_CDR_STATUS2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e2, (_val))
#define MODIFY_HL65_DSC3B3_CDR_STATUS2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e2, (_val), (_mask))

/* Phase Interpolator Status 0 Register */
#define READ_HL65_DSC3B3_PI_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e3, (_val))
#define WRITE_HL65_DSC3B3_PI_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e3, (_val))
#define MODIFY_HL65_DSC3B3_PI_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e3, (_val), (_mask))

/* Phase Interpolator Status 1 Register */
#define READ_HL65_DSC3B3_PI_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e4, (_val))
#define WRITE_HL65_DSC3B3_PI_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e4, (_val))
#define MODIFY_HL65_DSC3B3_PI_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e4, (_val), (_mask))

/* DFE VGA Status 0 Register */
#define READ_HL65_DSC3B3_DFE_VGA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e5, (_val))
#define WRITE_HL65_DSC3B3_DFE_VGA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e5, (_val))
#define MODIFY_HL65_DSC3B3_DFE_VGA_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e5, (_val), (_mask))

/* DFE VGA Status 1 Register */
#define READ_HL65_DSC3B3_DFE_VGA_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e6, (_val))
#define WRITE_HL65_DSC3B3_DFE_VGA_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e6, (_val))
#define MODIFY_HL65_DSC3B3_DFE_VGA_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e6, (_val), (_mask))

/* State Machine Status 0 Register */
#define READ_HL65_DSC3B3_SM_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e7, (_val))
#define WRITE_HL65_DSC3B3_SM_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e7, (_val))
#define MODIFY_HL65_DSC3B3_SM_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e7, (_val), (_mask))

/* State Machine Status 1 Register */
#define READ_HL65_DSC3B3_SM_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e8, (_val))
#define WRITE_HL65_DSC3B3_SM_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e8, (_val))
#define MODIFY_HL65_DSC3B3_SM_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e8, (_val), (_mask))

/* State Machine Status 2 Register */
#define READ_HL65_DSC3B3_SM_STATUS2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e9, (_val))
#define WRITE_HL65_DSC3B3_SM_STATUS2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e9, (_val))
#define MODIFY_HL65_DSC3B3_SM_STATUS2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e9, (_val), (_mask))

/* State Machine Status 3 Register */
#define READ_HL65_DSC3B3_SM_STATUS3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ea, (_val))
#define WRITE_HL65_DSC3B3_SM_STATUS3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ea, (_val))
#define MODIFY_HL65_DSC3B3_SM_STATUS3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ea, (_val), (_mask))

/* State Machine Status 4 Register */
#define READ_HL65_DSC3B3_SM_STATUS4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082eb, (_val))
#define WRITE_HL65_DSC3B3_SM_STATUS4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082eb, (_val))
#define MODIFY_HL65_DSC3B3_SM_STATUS4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082eb, (_val), (_mask))

/* DSC Analog Status 0 Register */
#define READ_HL65_DSC3B3_ANA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ec, (_val))
#define WRITE_HL65_DSC3B3_ANA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ec, (_val))
#define MODIFY_HL65_DSC3B3_ANA_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ec, (_val), (_mask))

/* State Machine Status 5 Register */
#define READ_HL65_DSC3B3_SM_STATUS5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ed, (_val))
#define WRITE_HL65_DSC3B3_SM_STATUS5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ed, (_val))
#define MODIFY_HL65_DSC3B3_SM_STATUS5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ed, (_val), (_mask))

/* State Machine Status 6 Register */
#define READ_HL65_DSC3B3_SM_STATUS6r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ee, (_val))
#define WRITE_HL65_DSC3B3_SM_STATUS6r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ee, (_val))
#define MODIFY_HL65_DSC3B3_SM_STATUS6r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ee, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc3bB
 ***************************************************************************/

/* CDR Status 0 Register */
#define READ_HL65_DSC3BB_CDR_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f0, (_val))
#define WRITE_HL65_DSC3BB_CDR_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f0, (_val))
#define MODIFY_HL65_DSC3BB_CDR_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f0, (_val), (_mask))

/* CDR Status 1 Register */
#define READ_HL65_DSC3BB_CDR_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f1, (_val))
#define WRITE_HL65_DSC3BB_CDR_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f1, (_val))
#define MODIFY_HL65_DSC3BB_CDR_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f1, (_val), (_mask))

/* CDR Status 2 Register */
#define READ_HL65_DSC3BB_CDR_STATUS2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f2, (_val))
#define WRITE_HL65_DSC3BB_CDR_STATUS2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f2, (_val))
#define MODIFY_HL65_DSC3BB_CDR_STATUS2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f2, (_val), (_mask))

/* Phase Interpolator Status 0 Register */
#define READ_HL65_DSC3BB_PI_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f3, (_val))
#define WRITE_HL65_DSC3BB_PI_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f3, (_val))
#define MODIFY_HL65_DSC3BB_PI_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f3, (_val), (_mask))

/* Phase Interpolator Status 1 Register */
#define READ_HL65_DSC3BB_PI_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f4, (_val))
#define WRITE_HL65_DSC3BB_PI_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f4, (_val))
#define MODIFY_HL65_DSC3BB_PI_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f4, (_val), (_mask))

/* DFE VGA Status 0 Register */
#define READ_HL65_DSC3BB_DFE_VGA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f5, (_val))
#define WRITE_HL65_DSC3BB_DFE_VGA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f5, (_val))
#define MODIFY_HL65_DSC3BB_DFE_VGA_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f5, (_val), (_mask))

/* DFE VGA Status 1 Register */
#define READ_HL65_DSC3BB_DFE_VGA_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f6, (_val))
#define WRITE_HL65_DSC3BB_DFE_VGA_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f6, (_val))
#define MODIFY_HL65_DSC3BB_DFE_VGA_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f6, (_val), (_mask))

/* State Machine Status 0 Register */
#define READ_HL65_DSC3BB_SM_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f7, (_val))
#define WRITE_HL65_DSC3BB_SM_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f7, (_val))
#define MODIFY_HL65_DSC3BB_SM_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f7, (_val), (_mask))

/* State Machine Status 1 Register */
#define READ_HL65_DSC3BB_SM_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f8, (_val))
#define WRITE_HL65_DSC3BB_SM_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f8, (_val))
#define MODIFY_HL65_DSC3BB_SM_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f8, (_val), (_mask))

/* State Machine Status 2 Register */
#define READ_HL65_DSC3BB_SM_STATUS2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f9, (_val))
#define WRITE_HL65_DSC3BB_SM_STATUS2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f9, (_val))
#define MODIFY_HL65_DSC3BB_SM_STATUS2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f9, (_val), (_mask))

/* State Machine Status 3 Register */
#define READ_HL65_DSC3BB_SM_STATUS3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082fa, (_val))
#define WRITE_HL65_DSC3BB_SM_STATUS3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082fa, (_val))
#define MODIFY_HL65_DSC3BB_SM_STATUS3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082fa, (_val), (_mask))

/* State Machine Status 4 Register */
#define READ_HL65_DSC3BB_SM_STATUS4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082fb, (_val))
#define WRITE_HL65_DSC3BB_SM_STATUS4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082fb, (_val))
#define MODIFY_HL65_DSC3BB_SM_STATUS4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082fb, (_val), (_mask))

/* DSC Analog Status 0 Register */
#define READ_HL65_DSC3BB_ANA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082fc, (_val))
#define WRITE_HL65_DSC3BB_ANA_STATUS0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082fc, (_val))
#define MODIFY_HL65_DSC3BB_ANA_STATUS0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082fc, (_val), (_mask))

/* State Machine Status 5 Register */
#define READ_HL65_DSC3BB_SM_STATUS5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082fd, (_val))
#define WRITE_HL65_DSC3BB_SM_STATUS5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082fd, (_val))
#define MODIFY_HL65_DSC3BB_SM_STATUS5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082fd, (_val), (_mask))

/* State Machine Status 6 Register */
#define READ_HL65_DSC3BB_SM_STATUS6r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000082fe, (_val))
#define WRITE_HL65_DSC3BB_SM_STATUS6r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082fe, (_val))
#define MODIFY_HL65_DSC3BB_SM_STATUS6r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082fe, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Digital
 ***************************************************************************/

/* 1000X control 1 register */
#define READ_HL65_DIGITAL_CONTROL1000X1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008300, (_val))
#define WRITE_HL65_DIGITAL_CONTROL1000X1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008300, (_val))
#define MODIFY_HL65_DIGITAL_CONTROL1000X1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008300, (_val), (_mask))

/* 1000X control 2 register */
#define READ_HL65_DIGITAL_CONTROL1000X2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008301, (_val))
#define WRITE_HL65_DIGITAL_CONTROL1000X2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008301, (_val))
#define MODIFY_HL65_DIGITAL_CONTROL1000X2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008301, (_val), (_mask))

/* 1000X control 3 register */
#define READ_HL65_DIGITAL_CONTROL1000X3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008302, (_val))
#define WRITE_HL65_DIGITAL_CONTROL1000X3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008302, (_val))
#define MODIFY_HL65_DIGITAL_CONTROL1000X3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008302, (_val), (_mask))

/* 1000X control 4 register */
#define READ_HL65_DIGITAL_CONTROL1000X4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008303, (_val))
#define WRITE_HL65_DIGITAL_CONTROL1000X4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008303, (_val))
#define MODIFY_HL65_DIGITAL_CONTROL1000X4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008303, (_val), (_mask))

/* 1000X status 1 register */
#define READ_HL65_DIGITAL_STATUS1000X1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008304, (_val))
#define WRITE_HL65_DIGITAL_STATUS1000X1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008304, (_val))
#define MODIFY_HL65_DIGITAL_STATUS1000X1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008304, (_val), (_mask))

/* 1000X status 2 register */
#define READ_HL65_DIGITAL_STATUS1000X2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008305, (_val))
#define WRITE_HL65_DIGITAL_STATUS1000X2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008305, (_val))
#define MODIFY_HL65_DIGITAL_STATUS1000X2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008305, (_val), (_mask))

/* 1000X status 3 register */
#define READ_HL65_DIGITAL_STATUS1000X3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008306, (_val))
#define WRITE_HL65_DIGITAL_STATUS1000X3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008306, (_val))
#define MODIFY_HL65_DIGITAL_STATUS1000X3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008306, (_val), (_mask))

/* Invalid code group count register */
#define READ_HL65_DIGITAL_BADCODEGROUPr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008307, (_val))
#define WRITE_HL65_DIGITAL_BADCODEGROUPr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008307, (_val))
#define MODIFY_HL65_DIGITAL_BADCODEGROUPr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008307, (_val), (_mask))

/* Miscellaneous 1 control register */
#define READ_HL65_DIGITAL_MISC1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008308, (_val))
#define WRITE_HL65_DIGITAL_MISC1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008308, (_val))
#define MODIFY_HL65_DIGITAL_MISC1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008308, (_val), (_mask))

/* Miscellaneous 2 control register */
#define READ_HL65_DIGITAL_MISC2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008309, (_val))
#define WRITE_HL65_DIGITAL_MISC2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008309, (_val))
#define MODIFY_HL65_DIGITAL_MISC2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008309, (_val), (_mask))

/* Pattern generator control register */
#define READ_HL65_DIGITAL_PATGENCTRLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000830a, (_val))
#define WRITE_HL65_DIGITAL_PATGENCTRLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000830a, (_val))
#define MODIFY_HL65_DIGITAL_PATGENCTRLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830a, (_val), (_mask))

/* Pattern generator status register */
#define READ_HL65_DIGITAL_PATGENSTATr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000830b, (_val))
#define WRITE_HL65_DIGITAL_PATGENSTATr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000830b, (_val))
#define MODIFY_HL65_DIGITAL_PATGENSTATr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830b, (_val), (_mask))

/* Test mode register */
#define READ_HL65_DIGITAL_TESTMODEr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000830c, (_val))
#define WRITE_HL65_DIGITAL_TESTMODEr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000830c, (_val))
#define MODIFY_HL65_DIGITAL_TESTMODEr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830c, (_val), (_mask))

/* Tx packet count register */
#define READ_HL65_DIGITAL_TXPKTCNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000830d, (_val))
#define WRITE_HL65_DIGITAL_TXPKTCNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000830d, (_val))
#define MODIFY_HL65_DIGITAL_TXPKTCNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830d, (_val), (_mask))

/* Rx packet count register */
#define READ_HL65_DIGITAL_RXPKTCNTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000830e, (_val))
#define WRITE_HL65_DIGITAL_RXPKTCNTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000830e, (_val))
#define MODIFY_HL65_DIGITAL_RXPKTCNTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Test
 ***************************************************************************/

/* Serdes ID 0 register */
#define READ_HL65_TEST_SERDESID0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008310, (_val))
#define WRITE_HL65_TEST_SERDESID0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008310, (_val))
#define MODIFY_HL65_TEST_SERDESID0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008310, (_val), (_mask))

/* Serdes ID 1 register */
#define READ_HL65_TEST_SERDESID1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008311, (_val))
#define WRITE_HL65_TEST_SERDESID1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008311, (_val))
#define MODIFY_HL65_TEST_SERDESID1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008311, (_val), (_mask))

/* Serdes ID 2 register */
#define READ_HL65_TEST_SERDESID2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008312, (_val))
#define WRITE_HL65_TEST_SERDESID2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008312, (_val))
#define MODIFY_HL65_TEST_SERDESID2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008312, (_val), (_mask))

/* Serdes ID 3 register */
#define READ_HL65_TEST_SERDESID3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008313, (_val))
#define WRITE_HL65_TEST_SERDESID3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008313, (_val))
#define MODIFY_HL65_TEST_SERDESID3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008313, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Digital3
 ***************************************************************************/

/* AN lost link count time, bits 15:0 */
#define READ_HL65_DIGITAL3_DIGCTL_3_0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008320, (_val))
#define WRITE_HL65_DIGITAL3_DIGCTL_3_0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008320, (_val))
#define MODIFY_HL65_DIGITAL3_DIGCTL_3_0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008320, (_val), (_mask))

/* AN switch count time, bits 15:0 */
#define READ_HL65_DIGITAL3_DIGCTL_3_1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008321, (_val))
#define WRITE_HL65_DIGITAL3_DIGCTL_3_1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008321, (_val))
#define MODIFY_HL65_DIGITAL3_DIGCTL_3_1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008321, (_val), (_mask))

/* AN link count time, bits 15:0 */
#define READ_HL65_DIGITAL3_DIGCTL_3_2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008322, (_val))
#define WRITE_HL65_DIGITAL3_DIGCTL_3_2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008322, (_val))
#define MODIFY_HL65_DIGITAL3_DIGCTL_3_2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008322, (_val), (_mask))

/* AN switch count & link count time, bits 23:16 */
#define READ_HL65_DIGITAL3_DIGCTL_3_3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008323, (_val))
#define WRITE_HL65_DIGITAL3_DIGCTL_3_3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008323, (_val))
#define MODIFY_HL65_DIGITAL3_DIGCTL_3_3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008323, (_val), (_mask))

/* Over 1G message page number & AN fail count timer */
#define READ_HL65_DIGITAL3_DIGCTL_3_4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008324, (_val))
#define WRITE_HL65_DIGITAL3_DIGCTL_3_4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008324, (_val))
#define MODIFY_HL65_DIGITAL3_DIGCTL_3_4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008324, (_val), (_mask))

/* AN ignore link count time, bits 15:0 */
#define READ_HL65_DIGITAL3_DIGCTL_3_5r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008325, (_val))
#define WRITE_HL65_DIGITAL3_DIGCTL_3_5r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008325, (_val))
#define MODIFY_HL65_DIGITAL3_DIGCTL_3_5r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008325, (_val), (_mask))

/* AN lost link count & ignore link count time, bits 23:16 */
#define READ_HL65_DIGITAL3_DIGCTL_3_6r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008326, (_val))
#define WRITE_HL65_DIGITAL3_DIGCTL_3_6r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008326, (_val))
#define MODIFY_HL65_DIGITAL3_DIGCTL_3_6r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008326, (_val), (_mask))

/* Test port out bits 15:0, tpout[15:0] */
#define READ_HL65_DIGITAL3_TPOUT_1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008327, (_val))
#define WRITE_HL65_DIGITAL3_TPOUT_1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008327, (_val))
#define MODIFY_HL65_DIGITAL3_TPOUT_1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008327, (_val), (_mask))

/* Test port out bits 23:8, tpout[23:8] */
#define READ_HL65_DIGITAL3_TPOUT_2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008328, (_val))
#define WRITE_HL65_DIGITAL3_TPOUT_2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008328, (_val))
#define MODIFY_HL65_DIGITAL3_TPOUT_2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008328, (_val), (_mask))

/* AN local device user page 1 */
#define READ_HL65_DIGITAL3_UP1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008329, (_val))
#define WRITE_HL65_DIGITAL3_UP1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008329, (_val))
#define MODIFY_HL65_DIGITAL3_UP1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008329, (_val), (_mask))

/* AN local device user page 2 */
#define READ_HL65_DIGITAL3_UP2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000832a, (_val))
#define WRITE_HL65_DIGITAL3_UP2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000832a, (_val))
#define MODIFY_HL65_DIGITAL3_UP2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832a, (_val), (_mask))

/* AN local device user page 3 */
#define READ_HL65_DIGITAL3_UP3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000832b, (_val))
#define WRITE_HL65_DIGITAL3_UP3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000832b, (_val))
#define MODIFY_HL65_DIGITAL3_UP3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832b, (_val), (_mask))

/* AN link partner user page 1 */
#define READ_HL65_DIGITAL3_LP_UP1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000832c, (_val))
#define WRITE_HL65_DIGITAL3_LP_UP1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000832c, (_val))
#define MODIFY_HL65_DIGITAL3_LP_UP1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832c, (_val), (_mask))

/* AN link partner user page 2 */
#define READ_HL65_DIGITAL3_LP_UP2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000832d, (_val))
#define WRITE_HL65_DIGITAL3_LP_UP2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000832d, (_val))
#define MODIFY_HL65_DIGITAL3_LP_UP2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832d, (_val), (_mask))

/* AN link partner user page 3 */
#define READ_HL65_DIGITAL3_LP_UP3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000832e, (_val))
#define WRITE_HL65_DIGITAL3_LP_UP3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000832e, (_val))
#define MODIFY_HL65_DIGITAL3_LP_UP3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832e, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Digital4
 ***************************************************************************/

/* Miscellaneous Rx status register */
#define READ_HL65_DIGITAL4_MISCRXSTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008330, (_val))
#define WRITE_HL65_DIGITAL4_MISCRXSTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008330, (_val))
#define MODIFY_HL65_DIGITAL4_MISCRXSTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008330, (_val), (_mask))

/* Link partner basepage register */
#define READ_HL65_DIGITAL4_LP_BASEPAGEr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008331, (_val))
#define WRITE_HL65_DIGITAL4_LP_BASEPAGEr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008331, (_val))
#define MODIFY_HL65_DIGITAL4_LP_BASEPAGEr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008331, (_val), (_mask))

/* Link partner nextpage 0 register */
#define READ_HL65_DIGITAL4_LP_NEXTPAGE_0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008332, (_val))
#define WRITE_HL65_DIGITAL4_LP_NEXTPAGE_0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008332, (_val))
#define MODIFY_HL65_DIGITAL4_LP_NEXTPAGE_0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008332, (_val), (_mask))

/* Link partner nextpage 1 register */
#define READ_HL65_DIGITAL4_LP_NEXTPAGE_1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008333, (_val))
#define WRITE_HL65_DIGITAL4_LP_NEXTPAGE_1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008333, (_val))
#define MODIFY_HL65_DIGITAL4_LP_NEXTPAGE_1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008333, (_val), (_mask))

/* Link partner nextpage 2 register */
#define READ_HL65_DIGITAL4_LP_NEXTPAGE_2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008334, (_val))
#define WRITE_HL65_DIGITAL4_LP_NEXTPAGE_2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008334, (_val))
#define MODIFY_HL65_DIGITAL4_LP_NEXTPAGE_2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008334, (_val), (_mask))

/* Link partner nextpage 3 register */
#define READ_HL65_DIGITAL4_LP_NEXTPAGE_3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008335, (_val))
#define WRITE_HL65_DIGITAL4_LP_NEXTPAGE_3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008335, (_val))
#define MODIFY_HL65_DIGITAL4_LP_NEXTPAGE_3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008335, (_val), (_mask))

/* Link partner nextpage 4 register */
#define READ_HL65_DIGITAL4_LP_NEXTPAGE_4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008336, (_val))
#define WRITE_HL65_DIGITAL4_LP_NEXTPAGE_4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008336, (_val))
#define MODIFY_HL65_DIGITAL4_LP_NEXTPAGE_4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008336, (_val), (_mask))

/* Remote phy nextpage 0 register */
#define READ_HL65_DIGITAL4_RP_NEXTPAGE_0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008337, (_val))
#define WRITE_HL65_DIGITAL4_RP_NEXTPAGE_0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008337, (_val))
#define MODIFY_HL65_DIGITAL4_RP_NEXTPAGE_0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008337, (_val), (_mask))

/* Remote phy nextpage 1 register */
#define READ_HL65_DIGITAL4_RP_NEXTPAGE_1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008338, (_val))
#define WRITE_HL65_DIGITAL4_RP_NEXTPAGE_1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008338, (_val))
#define MODIFY_HL65_DIGITAL4_RP_NEXTPAGE_1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008338, (_val), (_mask))

/* Remote phy nextpage 2 register */
#define READ_HL65_DIGITAL4_RP_NEXTPAGE_2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008339, (_val))
#define WRITE_HL65_DIGITAL4_RP_NEXTPAGE_2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008339, (_val))
#define MODIFY_HL65_DIGITAL4_RP_NEXTPAGE_2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008339, (_val), (_mask))

/* Remote phy nextpage 3 register */
#define READ_HL65_DIGITAL4_RP_NEXTPAGE_3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000833a, (_val))
#define WRITE_HL65_DIGITAL4_RP_NEXTPAGE_3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000833a, (_val))
#define MODIFY_HL65_DIGITAL4_RP_NEXTPAGE_3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833a, (_val), (_mask))

/* Remote phy nextpage 4 register */
#define READ_HL65_DIGITAL4_RP_NEXTPAGE_4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000833b, (_val))
#define WRITE_HL65_DIGITAL4_RP_NEXTPAGE_4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000833b, (_val))
#define MODIFY_HL65_DIGITAL4_RP_NEXTPAGE_4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833b, (_val), (_mask))

/* Miscellaneous 3 control register */
#define READ_HL65_DIGITAL4_MISC3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000833c, (_val))
#define WRITE_HL65_DIGITAL4_MISC3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000833c, (_val))
#define MODIFY_HL65_DIGITAL4_MISC3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833c, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Digital6
 ***************************************************************************/

/* MP5, Message Page 5, next page control register */
#define READ_HL65_DIGITAL6_MP5_NEXTPAGECTRLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008350, (_val))
#define WRITE_HL65_DIGITAL6_MP5_NEXTPAGECTRLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008350, (_val))
#define MODIFY_HL65_DIGITAL6_MP5_NEXTPAGECTRLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008350, (_val), (_mask))

/* sgmii & max timer offsets */
#define READ_HL65_DIGITAL6_LINK_TIMER_OFFSET1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008351, (_val))
#define WRITE_HL65_DIGITAL6_LINK_TIMER_OFFSET1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008351, (_val))
#define MODIFY_HL65_DIGITAL6_LINK_TIMER_OFFSET1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008351, (_val), (_mask))

/* link up & link down timer offsets */
#define READ_HL65_DIGITAL6_LINK_TIMER_OFFSET2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008352, (_val))
#define WRITE_HL65_DIGITAL6_LINK_TIMER_OFFSET2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008352, (_val))
#define MODIFY_HL65_DIGITAL6_LINK_TIMER_OFFSET2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008352, (_val), (_mask))

/* break link & next page link timer offsets */
#define READ_HL65_DIGITAL6_LINK_TIMER_OFFSET3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008353, (_val))
#define WRITE_HL65_DIGITAL6_LINK_TIMER_OFFSET3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008353, (_val))
#define MODIFY_HL65_DIGITAL6_LINK_TIMER_OFFSET3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008353, (_val), (_mask))

/* 11 MSbits of the oui, oui[23:13] */
#define READ_HL65_DIGITAL6_OUI_MSB_FIELDr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008354, (_val))
#define WRITE_HL65_DIGITAL6_OUI_MSB_FIELDr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008354, (_val))
#define MODIFY_HL65_DIGITAL6_OUI_MSB_FIELDr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008354, (_val), (_mask))

/* 11 middle bits of the oui, oui[12:2] */
#define READ_HL65_DIGITAL6_OUI_LSB_FIELDr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008355, (_val))
#define WRITE_HL65_DIGITAL6_OUI_LSB_FIELDr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008355, (_val))
#define MODIFY_HL65_DIGITAL6_OUI_LSB_FIELDr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008355, (_val), (_mask))

/* 2 LSbits of the oui, oui[1:0] */
#define READ_HL65_DIGITAL6_BAM_FIELDr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008356, (_val))
#define WRITE_HL65_DIGITAL6_BAM_FIELDr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008356, (_val))
#define MODIFY_HL65_DIGITAL6_BAM_FIELDr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008356, (_val), (_mask))

/* User defined field of MP5 */
#define READ_HL65_DIGITAL6_UD_FIELDr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008357, (_val))
#define WRITE_HL65_DIGITAL6_UD_FIELDr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008357, (_val))
#define MODIFY_HL65_DIGITAL6_UD_FIELDr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008357, (_val), (_mask))

/* Link partner's 11 MSbits of the oui, oui[23:13] */
#define READ_HL65_DIGITAL6_LP_OUI_MSB_FIELDr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008358, (_val))
#define WRITE_HL65_DIGITAL6_LP_OUI_MSB_FIELDr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008358, (_val))
#define MODIFY_HL65_DIGITAL6_LP_OUI_MSB_FIELDr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008358, (_val), (_mask))

/* Link partner's 11 middle bits of the oui, oui[12:2] */
#define READ_HL65_DIGITAL6_LP_OUI_LSB_FIELDr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008359, (_val))
#define WRITE_HL65_DIGITAL6_LP_OUI_LSB_FIELDr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008359, (_val))
#define MODIFY_HL65_DIGITAL6_LP_OUI_LSB_FIELDr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008359, (_val), (_mask))

/* Link partner's 2 LSbits of the oui, oui[1:0] */
#define READ_HL65_DIGITAL6_LP_BAM_FIELDr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000835a, (_val))
#define WRITE_HL65_DIGITAL6_LP_BAM_FIELDr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000835a, (_val))
#define MODIFY_HL65_DIGITAL6_LP_BAM_FIELDr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000835a, (_val), (_mask))

/* Link partner's User defined field of MP5 */
#define READ_HL65_DIGITAL6_LP_UD_FIELDr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000835b, (_val))
#define WRITE_HL65_DIGITAL6_LP_UD_FIELDr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000835b, (_val))
#define MODIFY_HL65_DIGITAL6_LP_UD_FIELDr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000835b, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_CL73_UserB0
 ***************************************************************************/

/* Clause 73 user control */
#define READ_HL65_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008370, (_val))
#define WRITE_HL65_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008370, (_val))
#define MODIFY_HL65_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008370, (_val), (_mask))

/* Clause 73 user status */
#define READ_HL65_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008371, (_val))
#define WRITE_HL65_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008371, (_val))
#define MODIFY_HL65_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008371, (_val), (_mask))

/* Clause 73 BAM control 1 */
#define READ_HL65_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008372, (_val))
#define WRITE_HL65_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008372, (_val))
#define MODIFY_HL65_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008372, (_val), (_mask))

/* Clause 73 BAM control 2 */
#define READ_HL65_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008373, (_val))
#define WRITE_HL65_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008373, (_val))
#define MODIFY_HL65_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008373, (_val), (_mask))

/* Clause 73 BAM control 3 */
#define READ_HL65_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008374, (_val))
#define WRITE_HL65_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008374, (_val))
#define MODIFY_HL65_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008374, (_val), (_mask))

/* Clause 73 BAM status 1 */
#define READ_HL65_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008375, (_val))
#define WRITE_HL65_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008375, (_val))
#define MODIFY_HL65_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008375, (_val), (_mask))

/* Clause 73 BAM status 2 */
#define READ_HL65_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008376, (_val))
#define WRITE_HL65_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008376, (_val))
#define MODIFY_HL65_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008376, (_val), (_mask))

/* Clause 73 BAM status 3 */
#define READ_HL65_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008377, (_val))
#define WRITE_HL65_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008377, (_val))
#define MODIFY_HL65_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008377, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc4b0
 ***************************************************************************/

/* State Machine Control 13 Register */
#define READ_HL65_DSC4B0_SM_CTRL13r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008380, (_val))
#define WRITE_HL65_DSC4B0_SM_CTRL13r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008380, (_val))
#define MODIFY_HL65_DSC4B0_SM_CTRL13r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008380, (_val), (_mask))

/* State Machine Control 14 Register */
#define READ_HL65_DSC4B0_SM_CTRL14r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008381, (_val))
#define WRITE_HL65_DSC4B0_SM_CTRL14r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008381, (_val))
#define MODIFY_HL65_DSC4B0_SM_CTRL14r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008381, (_val), (_mask))

/* State Machine Control 15 Register */
#define READ_HL65_DSC4B0_SM_CTRL15r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008382, (_val))
#define WRITE_HL65_DSC4B0_SM_CTRL15r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008382, (_val))
#define MODIFY_HL65_DSC4B0_SM_CTRL15r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008382, (_val), (_mask))

/* State Machine Control 16 Register */
#define READ_HL65_DSC4B0_SM_CTRL16r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008383, (_val))
#define WRITE_HL65_DSC4B0_SM_CTRL16r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008383, (_val))
#define MODIFY_HL65_DSC4B0_SM_CTRL16r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008383, (_val), (_mask))

/* State Machine Control 17 Register */
#define READ_HL65_DSC4B0_SM_CTRL17r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008384, (_val))
#define WRITE_HL65_DSC4B0_SM_CTRL17r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008384, (_val))
#define MODIFY_HL65_DSC4B0_SM_CTRL17r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008384, (_val), (_mask))

/* State Machine Status 7 Register */
#define READ_HL65_DSC4B0_SM_STATUS7r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008385, (_val))
#define WRITE_HL65_DSC4B0_SM_STATUS7r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008385, (_val))
#define MODIFY_HL65_DSC4B0_SM_STATUS7r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008385, (_val), (_mask))

/* State Machine Status 8 Register */
#define READ_HL65_DSC4B0_SM_STATUS8r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008386, (_val))
#define WRITE_HL65_DSC4B0_SM_STATUS8r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008386, (_val))
#define MODIFY_HL65_DSC4B0_SM_STATUS8r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008386, (_val), (_mask))

/* State Machine Status 9 Register */
#define READ_HL65_DSC4B0_SM_STATUS9r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008387, (_val))
#define WRITE_HL65_DSC4B0_SM_STATUS9r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008387, (_val))
#define MODIFY_HL65_DSC4B0_SM_STATUS9r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008387, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc4b1
 ***************************************************************************/

/* State Machine Control 13 Register */
#define READ_HL65_DSC4B1_SM_CTRL13r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008390, (_val))
#define WRITE_HL65_DSC4B1_SM_CTRL13r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008390, (_val))
#define MODIFY_HL65_DSC4B1_SM_CTRL13r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008390, (_val), (_mask))

/* State Machine Control 14 Register */
#define READ_HL65_DSC4B1_SM_CTRL14r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008391, (_val))
#define WRITE_HL65_DSC4B1_SM_CTRL14r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008391, (_val))
#define MODIFY_HL65_DSC4B1_SM_CTRL14r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008391, (_val), (_mask))

/* State Machine Control 15 Register */
#define READ_HL65_DSC4B1_SM_CTRL15r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008392, (_val))
#define WRITE_HL65_DSC4B1_SM_CTRL15r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008392, (_val))
#define MODIFY_HL65_DSC4B1_SM_CTRL15r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008392, (_val), (_mask))

/* State Machine Control 16 Register */
#define READ_HL65_DSC4B1_SM_CTRL16r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008393, (_val))
#define WRITE_HL65_DSC4B1_SM_CTRL16r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008393, (_val))
#define MODIFY_HL65_DSC4B1_SM_CTRL16r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008393, (_val), (_mask))

/* State Machine Control 17 Register */
#define READ_HL65_DSC4B1_SM_CTRL17r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008394, (_val))
#define WRITE_HL65_DSC4B1_SM_CTRL17r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008394, (_val))
#define MODIFY_HL65_DSC4B1_SM_CTRL17r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008394, (_val), (_mask))

/* State Machine Status 7 Register */
#define READ_HL65_DSC4B1_SM_STATUS7r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008395, (_val))
#define WRITE_HL65_DSC4B1_SM_STATUS7r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008395, (_val))
#define MODIFY_HL65_DSC4B1_SM_STATUS7r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008395, (_val), (_mask))

/* State Machine Status 8 Register */
#define READ_HL65_DSC4B1_SM_STATUS8r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008396, (_val))
#define WRITE_HL65_DSC4B1_SM_STATUS8r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008396, (_val))
#define MODIFY_HL65_DSC4B1_SM_STATUS8r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008396, (_val), (_mask))

/* State Machine Status 9 Register */
#define READ_HL65_DSC4B1_SM_STATUS9r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008397, (_val))
#define WRITE_HL65_DSC4B1_SM_STATUS9r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008397, (_val))
#define MODIFY_HL65_DSC4B1_SM_STATUS9r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008397, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc4b2
 ***************************************************************************/

/* State Machine Control 13 Register */
#define READ_HL65_DSC4B2_SM_CTRL13r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a0, (_val))
#define WRITE_HL65_DSC4B2_SM_CTRL13r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a0, (_val))
#define MODIFY_HL65_DSC4B2_SM_CTRL13r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a0, (_val), (_mask))

/* State Machine Control 14 Register */
#define READ_HL65_DSC4B2_SM_CTRL14r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a1, (_val))
#define WRITE_HL65_DSC4B2_SM_CTRL14r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a1, (_val))
#define MODIFY_HL65_DSC4B2_SM_CTRL14r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a1, (_val), (_mask))

/* State Machine Control 15 Register */
#define READ_HL65_DSC4B2_SM_CTRL15r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a2, (_val))
#define WRITE_HL65_DSC4B2_SM_CTRL15r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a2, (_val))
#define MODIFY_HL65_DSC4B2_SM_CTRL15r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a2, (_val), (_mask))

/* State Machine Control 16 Register */
#define READ_HL65_DSC4B2_SM_CTRL16r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a3, (_val))
#define WRITE_HL65_DSC4B2_SM_CTRL16r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a3, (_val))
#define MODIFY_HL65_DSC4B2_SM_CTRL16r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a3, (_val), (_mask))

/* State Machine Control 17 Register */
#define READ_HL65_DSC4B2_SM_CTRL17r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a4, (_val))
#define WRITE_HL65_DSC4B2_SM_CTRL17r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a4, (_val))
#define MODIFY_HL65_DSC4B2_SM_CTRL17r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a4, (_val), (_mask))

/* State Machine Status 7 Register */
#define READ_HL65_DSC4B2_SM_STATUS7r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a5, (_val))
#define WRITE_HL65_DSC4B2_SM_STATUS7r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a5, (_val))
#define MODIFY_HL65_DSC4B2_SM_STATUS7r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a5, (_val), (_mask))

/* State Machine Status 8 Register */
#define READ_HL65_DSC4B2_SM_STATUS8r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a6, (_val))
#define WRITE_HL65_DSC4B2_SM_STATUS8r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a6, (_val))
#define MODIFY_HL65_DSC4B2_SM_STATUS8r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a6, (_val), (_mask))

/* State Machine Status 9 Register */
#define READ_HL65_DSC4B2_SM_STATUS9r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a7, (_val))
#define WRITE_HL65_DSC4B2_SM_STATUS9r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a7, (_val))
#define MODIFY_HL65_DSC4B2_SM_STATUS9r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a7, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc4b3
 ***************************************************************************/

/* State Machine Control 13 Register */
#define READ_HL65_DSC4B3_SM_CTRL13r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b0, (_val))
#define WRITE_HL65_DSC4B3_SM_CTRL13r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b0, (_val))
#define MODIFY_HL65_DSC4B3_SM_CTRL13r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b0, (_val), (_mask))

/* State Machine Control 14 Register */
#define READ_HL65_DSC4B3_SM_CTRL14r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b1, (_val))
#define WRITE_HL65_DSC4B3_SM_CTRL14r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b1, (_val))
#define MODIFY_HL65_DSC4B3_SM_CTRL14r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b1, (_val), (_mask))

/* State Machine Control 15 Register */
#define READ_HL65_DSC4B3_SM_CTRL15r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b2, (_val))
#define WRITE_HL65_DSC4B3_SM_CTRL15r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b2, (_val))
#define MODIFY_HL65_DSC4B3_SM_CTRL15r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b2, (_val), (_mask))

/* State Machine Control 16 Register */
#define READ_HL65_DSC4B3_SM_CTRL16r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b3, (_val))
#define WRITE_HL65_DSC4B3_SM_CTRL16r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b3, (_val))
#define MODIFY_HL65_DSC4B3_SM_CTRL16r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b3, (_val), (_mask))

/* State Machine Control 17 Register */
#define READ_HL65_DSC4B3_SM_CTRL17r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b4, (_val))
#define WRITE_HL65_DSC4B3_SM_CTRL17r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b4, (_val))
#define MODIFY_HL65_DSC4B3_SM_CTRL17r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b4, (_val), (_mask))

/* State Machine Status 7 Register */
#define READ_HL65_DSC4B3_SM_STATUS7r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b5, (_val))
#define WRITE_HL65_DSC4B3_SM_STATUS7r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b5, (_val))
#define MODIFY_HL65_DSC4B3_SM_STATUS7r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b5, (_val), (_mask))

/* State Machine Status 8 Register */
#define READ_HL65_DSC4B3_SM_STATUS8r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b6, (_val))
#define WRITE_HL65_DSC4B3_SM_STATUS8r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b6, (_val))
#define MODIFY_HL65_DSC4B3_SM_STATUS8r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b6, (_val), (_mask))

/* State Machine Status 9 Register */
#define READ_HL65_DSC4B3_SM_STATUS9r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b7, (_val))
#define WRITE_HL65_DSC4B3_SM_STATUS9r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b7, (_val))
#define MODIFY_HL65_DSC4B3_SM_STATUS9r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b7, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Dsc4bB
 ***************************************************************************/

/* State Machine Control 13 Register */
#define READ_HL65_DSC4BB_SM_CTRL13r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c0, (_val))
#define WRITE_HL65_DSC4BB_SM_CTRL13r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c0, (_val))
#define MODIFY_HL65_DSC4BB_SM_CTRL13r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c0, (_val), (_mask))

/* State Machine Control 14 Register */
#define READ_HL65_DSC4BB_SM_CTRL14r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c1, (_val))
#define WRITE_HL65_DSC4BB_SM_CTRL14r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c1, (_val))
#define MODIFY_HL65_DSC4BB_SM_CTRL14r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c1, (_val), (_mask))

/* State Machine Control 15 Register */
#define READ_HL65_DSC4BB_SM_CTRL15r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c2, (_val))
#define WRITE_HL65_DSC4BB_SM_CTRL15r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c2, (_val))
#define MODIFY_HL65_DSC4BB_SM_CTRL15r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c2, (_val), (_mask))

/* State Machine Control 16 Register */
#define READ_HL65_DSC4BB_SM_CTRL16r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c3, (_val))
#define WRITE_HL65_DSC4BB_SM_CTRL16r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c3, (_val))
#define MODIFY_HL65_DSC4BB_SM_CTRL16r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c3, (_val), (_mask))

/* State Machine Control 17 Register */
#define READ_HL65_DSC4BB_SM_CTRL17r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c4, (_val))
#define WRITE_HL65_DSC4BB_SM_CTRL17r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c4, (_val))
#define MODIFY_HL65_DSC4BB_SM_CTRL17r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c4, (_val), (_mask))

/* State Machine Status 7 Register */
#define READ_HL65_DSC4BB_SM_STATUS7r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c5, (_val))
#define WRITE_HL65_DSC4BB_SM_STATUS7r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c5, (_val))
#define MODIFY_HL65_DSC4BB_SM_STATUS7r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c5, (_val), (_mask))

/* State Machine Status 8 Register */
#define READ_HL65_DSC4BB_SM_STATUS8r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c6, (_val))
#define WRITE_HL65_DSC4BB_SM_STATUS8r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c6, (_val))
#define MODIFY_HL65_DSC4BB_SM_STATUS8r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c6, (_val), (_mask))

/* State Machine Status 9 Register */
#define READ_HL65_DSC4BB_SM_STATUS9r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c7, (_val))
#define WRITE_HL65_DSC4BB_SM_STATUS9r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c7, (_val))
#define MODIFY_HL65_DSC4BB_SM_STATUS9r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c7, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_FX100
 ***************************************************************************/

/* 100FX control register 1 */
#define READ_HL65_FX100_CONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008400, (_val))
#define WRITE_HL65_FX100_CONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008400, (_val))
#define MODIFY_HL65_FX100_CONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008400, (_val), (_mask))

/* 100FX control register 2 */
#define READ_HL65_FX100_CONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008401, (_val))
#define WRITE_HL65_FX100_CONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008401, (_val))
#define MODIFY_HL65_FX100_CONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008401, (_val), (_mask))

/* 100FX control register 3 */
#define READ_HL65_FX100_CONTROL3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008402, (_val))
#define WRITE_HL65_FX100_CONTROL3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008402, (_val))
#define MODIFY_HL65_FX100_CONTROL3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008402, (_val), (_mask))

/* 100FX status register 1 */
#define READ_HL65_FX100_STATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008403, (_val))
#define WRITE_HL65_FX100_STATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008403, (_val))
#define MODIFY_HL65_FX100_STATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008403, (_val), (_mask))

/* 100FX status register 3 */
#define READ_HL65_FX100_STATUS3r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008405, (_val))
#define WRITE_HL65_FX100_STATUS3r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008405, (_val))
#define MODIFY_HL65_FX100_STATUS3r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008405, (_val), (_mask))

/* 100FX status register 4 */
#define READ_HL65_FX100_STATUS4r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x00008406, (_val))
#define WRITE_HL65_FX100_STATUS4r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008406, (_val))
#define MODIFY_HL65_FX100_STATUS4r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008406, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_aerBlk
 ***************************************************************************/

/* Address Expansion Register */
#define READ_HL65_AERBLK_AERr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffde, (_val))
#define WRITE_HL65_AERBLK_AERr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffde, (_val))
#define MODIFY_HL65_AERBLK_AERr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffde, (_val), (_mask))


/****************************************************************************
 * Hypercore_USER_Combo_IEEE0
 ***************************************************************************/

/* IEEE MII control register */
#define READ_HL65_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe0, (_val))
#define WRITE_HL65_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe0, (_val))
#define MODIFY_HL65_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe0, (_val), (_mask))

/* IEEE MII status register */
#define READ_HL65_COMBO_IEEE0_MIISTATr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe1, (_val))
#define WRITE_HL65_COMBO_IEEE0_MIISTATr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe1, (_val))
#define MODIFY_HL65_COMBO_IEEE0_MIISTATr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe1, (_val), (_mask))

/* IEEE phy ID LSByte register */
#define READ_HL65_COMBO_IEEE0_ID1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe2, (_val))
#define WRITE_HL65_COMBO_IEEE0_ID1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe2, (_val))
#define MODIFY_HL65_COMBO_IEEE0_ID1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe2, (_val), (_mask))

/* IEEE phy ID MSByte register */
#define READ_HL65_COMBO_IEEE0_ID2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe3, (_val))
#define WRITE_HL65_COMBO_IEEE0_ID2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe3, (_val))
#define MODIFY_HL65_COMBO_IEEE0_ID2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe3, (_val), (_mask))

/* IEEE auto-negotiation advertised abilities register */
#define READ_HL65_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe4, (_val))
#define WRITE_HL65_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe4, (_val))
#define MODIFY_HL65_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe4, (_val), (_mask))

/* IEEE auto-negotiation link partner abilities register */
#define READ_HL65_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe5, (_val))
#define WRITE_HL65_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe5, (_val))
#define MODIFY_HL65_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe5, (_val), (_mask))

/* IEEE auto-negotiation expansion register */
#define READ_HL65_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe6, (_val))
#define WRITE_HL65_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe6, (_val))
#define MODIFY_HL65_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe6, (_val), (_mask))

/* IEEE auto-negotiation next page register */
#define READ_HL65_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe7, (_val))
#define WRITE_HL65_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe7, (_val))
#define MODIFY_HL65_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe7, (_val), (_mask))

/* IEEE auto-negotiation link partner next page register */
#define READ_HL65_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe8, (_val))
#define WRITE_HL65_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe8, (_val))
#define MODIFY_HL65_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe8, (_val), (_mask))

/* IEEE MII extended status register */
#define READ_HL65_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffef, (_val))
#define WRITE_HL65_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffef, (_val))
#define MODIFY_HL65_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffef, (_val), (_mask))


/****************************************************************************
 * Hypercore_IEEE_PMD_PMD_ieee0Blk
 ***************************************************************************/

/* PMD Control 1 */
#define READ_HL65_PMD_IEEE0BLK_PMD_IEEECONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x08000000, (_val))
#define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEECONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000000, (_val))
#define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEECONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000000, (_val), (_mask))

/* PMD Status 1 */
#define READ_HL65_PMD_IEEE0BLK_PMD_IEEESTATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x08000001, (_val))
#define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEESTATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000001, (_val))
#define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEESTATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000001, (_val), (_mask))

/* PMD Device ID [15:0] */
#define READ_HL65_PMD_IEEE0BLK_PMD_IEEEID1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x08000002, (_val))
#define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEEID1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000002, (_val))
#define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEEID1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000002, (_val), (_mask))

/* PMD Device ID [31:16] */
#define READ_HL65_PMD_IEEE0BLK_PMD_IEEEID2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x08000003, (_val))
#define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEEID2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000003, (_val))
#define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEEID2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000003, (_val), (_mask))

/* PMD Speed Ability */
#define READ_HL65_PMD_IEEE0BLK_PMD_IEEESPEEDABILITYr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x08000004, (_val))
#define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEESPEEDABILITYr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000004, (_val))
#define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEESPEEDABILITYr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000004, (_val), (_mask))

/* PMD Devices in Package 1 */
#define READ_HL65_PMD_IEEE0BLK_PMD_IEEEDEVINPKG2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x08000005, (_val))
#define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEEDEVINPKG2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000005, (_val))
#define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEEDEVINPKG2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000005, (_val), (_mask))

/* PMD Devices in Package 2 */
#define READ_HL65_PMD_IEEE0BLK_PMD_IEEEDEVINPKG1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x08000006, (_val))
#define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEEDEVINPKG1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000006, (_val))
#define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEEDEVINPKG1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000006, (_val), (_mask))

/* PMD Control 2 */
#define READ_HL65_PMD_IEEE0BLK_PMD_IEEECONTROL2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x08000007, (_val))
#define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEECONTROL2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000007, (_val))
#define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEECONTROL2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000007, (_val), (_mask))

/* PMD Status 2 */
#define READ_HL65_PMD_IEEE0BLK_PMD_IEEESTATUS2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x08000008, (_val))
#define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEESTATUS2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000008, (_val))
#define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEESTATUS2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000008, (_val), (_mask))

/* PMD Transmit Disable */
#define READ_HL65_PMD_IEEE0BLK_PMD_TXDISABLE_TYPEr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x08000009, (_val))
#define WRITE_HL65_PMD_IEEE0BLK_PMD_TXDISABLE_TYPEr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000009, (_val))
#define MODIFY_HL65_PMD_IEEE0BLK_PMD_TXDISABLE_TYPEr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000009, (_val), (_mask))

/* PMD Receive Signal Detect */
#define READ_HL65_PMD_IEEE0BLK_PMD_RXSIGNALDETECTr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0800000a, (_val))
#define WRITE_HL65_PMD_IEEE0BLK_PMD_RXSIGNALDETECTr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0800000a, (_val))
#define MODIFY_HL65_PMD_IEEE0BLK_PMD_RXSIGNALDETECTr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0800000a, (_val), (_mask))

/* PMD Extended Ability */
#define READ_HL65_PMD_IEEE0BLK_PMD_EXTENDEDABILITYr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x0800000b, (_val))
#define WRITE_HL65_PMD_IEEE0BLK_PMD_EXTENDEDABILITYr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0800000b, (_val))
#define MODIFY_HL65_PMD_IEEE0BLK_PMD_EXTENDEDABILITYr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0800000b, (_val), (_mask))


/****************************************************************************
 * Hypercore_IEEE_PMD_PMD_ieee10Blk
 ***************************************************************************/

/* PMD 1000BASE-KX control */
#define READ_HL65_PMD_IEEE10BLK_PMD_KX_CONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x080000a0, (_val))
#define WRITE_HL65_PMD_IEEE10BLK_PMD_KX_CONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x080000a0, (_val))
#define MODIFY_HL65_PMD_IEEE10BLK_PMD_KX_CONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x080000a0, (_val), (_mask))

/* PMD 1000BASE-KX status */
#define READ_HL65_PMD_IEEE10BLK_PMD_KX_STATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x080000a1, (_val))
#define WRITE_HL65_PMD_IEEE10BLK_PMD_KX_STATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x080000a1, (_val))
#define MODIFY_HL65_PMD_IEEE10BLK_PMD_KX_STATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x080000a1, (_val), (_mask))


/****************************************************************************
 * Hypercore_IEEE_DTE_DTE_ieee0Blk
 ***************************************************************************/

/* DTE-XS Control 1 */
#define READ_HL65_DTE_IEEE0BLK_DTE_IEEECONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x28000000, (_val))
#define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEECONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000000, (_val))
#define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEECONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000000, (_val), (_mask))

/* DTE-XS Status 1 */
#define READ_HL65_DTE_IEEE0BLK_DTE_IEEESTATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x28000001, (_val))
#define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEESTATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000001, (_val))
#define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEESTATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000001, (_val), (_mask))

/* DTE-XS Device ID [15:0] */
#define READ_HL65_DTE_IEEE0BLK_DTE_IEEEID1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x28000002, (_val))
#define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEEID1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000002, (_val))
#define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEEID1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000002, (_val), (_mask))

/* DTE-XS Device ID [31:16] */
#define READ_HL65_DTE_IEEE0BLK_DTE_IEEEID2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x28000003, (_val))
#define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEEID2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000003, (_val))
#define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEEID2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000003, (_val), (_mask))

/* DTE-XS Speed Ability */
#define READ_HL65_DTE_IEEE0BLK_DTE_IEEESPEEDABILITYr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x28000004, (_val))
#define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEESPEEDABILITYr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000004, (_val))
#define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEESPEEDABILITYr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000004, (_val), (_mask))

/* DTE-XS Devices in Package 1 */
#define READ_HL65_DTE_IEEE0BLK_DTE_IEEEDEVINPKG2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x28000005, (_val))
#define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEEDEVINPKG2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000005, (_val))
#define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEEDEVINPKG2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000005, (_val), (_mask))

/* DTE-XS Devices in Package 2 */
#define READ_HL65_DTE_IEEE0BLK_DTE_IEEEDEVINPKG1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x28000006, (_val))
#define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEEDEVINPKG1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000006, (_val))
#define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEEDEVINPKG1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000006, (_val), (_mask))

/* DTE-XS Status 2 */
#define READ_HL65_DTE_IEEE0BLK_DTE_IEEESTATUS2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x28000008, (_val))
#define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEESTATUS2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000008, (_val))
#define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEESTATUS2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000008, (_val), (_mask))


/****************************************************************************
 * Hypercore_IEEE_DTE_DTE_ieee1Blk
 ***************************************************************************/

/* XGXS lane Status */
#define READ_HL65_DTE_IEEE1BLK_DTE_LANESTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x28000018, (_val))
#define WRITE_HL65_DTE_IEEE1BLK_DTE_LANESTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000018, (_val))
#define MODIFY_HL65_DTE_IEEE1BLK_DTE_LANESTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000018, (_val), (_mask))

/* XGXS Test Control */
#define READ_HL65_DTE_IEEE1BLK_DTE_IEEETESTCONTROLr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x28000019, (_val))
#define WRITE_HL65_DTE_IEEE1BLK_DTE_IEEETESTCONTROLr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000019, (_val))
#define MODIFY_HL65_DTE_IEEE1BLK_DTE_IEEETESTCONTROLr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000019, (_val), (_mask))


/****************************************************************************
 * Hypercore_IEEE_CL73_AN_ieee0Blk
 ***************************************************************************/

/* AN Control 1 */
#define READ_HL65_AN_IEEE0BLK_AN_IEEECONTROL1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000000, (_val))
#define WRITE_HL65_AN_IEEE0BLK_AN_IEEECONTROL1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000000, (_val))
#define MODIFY_HL65_AN_IEEE0BLK_AN_IEEECONTROL1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000000, (_val), (_mask))

/* AN Status 1 */
#define READ_HL65_AN_IEEE0BLK_AN_IEEESTATUS1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000001, (_val))
#define WRITE_HL65_AN_IEEE0BLK_AN_IEEESTATUS1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000001, (_val))
#define MODIFY_HL65_AN_IEEE0BLK_AN_IEEESTATUS1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000001, (_val), (_mask))

/* AN Device ID [15:0] */
#define READ_HL65_AN_IEEE0BLK_AN_IEEEID1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000002, (_val))
#define WRITE_HL65_AN_IEEE0BLK_AN_IEEEID1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000002, (_val))
#define MODIFY_HL65_AN_IEEE0BLK_AN_IEEEID1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000002, (_val), (_mask))

/* AN Device ID [31:16] */
#define READ_HL65_AN_IEEE0BLK_AN_IEEEID2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000003, (_val))
#define WRITE_HL65_AN_IEEE0BLK_AN_IEEEID2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000003, (_val))
#define MODIFY_HL65_AN_IEEE0BLK_AN_IEEEID2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000003, (_val), (_mask))

/* AN Devices in Package 1 */
#define READ_HL65_AN_IEEE0BLK_AN_IEEEDEVINPKG2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000005, (_val))
#define WRITE_HL65_AN_IEEE0BLK_AN_IEEEDEVINPKG2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000005, (_val))
#define MODIFY_HL65_AN_IEEE0BLK_AN_IEEEDEVINPKG2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000005, (_val), (_mask))

/* AN Devices in Package 2 */
#define READ_HL65_AN_IEEE0BLK_AN_IEEEDEVINPKG1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000006, (_val))
#define WRITE_HL65_AN_IEEE0BLK_AN_IEEEDEVINPKG1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000006, (_val))
#define MODIFY_HL65_AN_IEEE0BLK_AN_IEEEDEVINPKG1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000006, (_val), (_mask))


/****************************************************************************
 * Hypercore_IEEE_CL73_AN_ieee1Blk
 ***************************************************************************/

/* AN advertisement 0 */
#define READ_HL65_AN_IEEE1BLK_AN_ADVERTISEMENT0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000010, (_val))
#define WRITE_HL65_AN_IEEE1BLK_AN_ADVERTISEMENT0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000010, (_val))
#define MODIFY_HL65_AN_IEEE1BLK_AN_ADVERTISEMENT0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000010, (_val), (_mask))

/* AN advertisement 1 */
#define READ_HL65_AN_IEEE1BLK_AN_ADVERTISEMENT1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000011, (_val))
#define WRITE_HL65_AN_IEEE1BLK_AN_ADVERTISEMENT1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000011, (_val))
#define MODIFY_HL65_AN_IEEE1BLK_AN_ADVERTISEMENT1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000011, (_val), (_mask))

/* AN LP base page ability 0 */
#define READ_HL65_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000013, (_val))
#define WRITE_HL65_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000013, (_val))
#define MODIFY_HL65_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000013, (_val), (_mask))

/* AN LP base page ability 1 */
#define READ_HL65_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000014, (_val))
#define WRITE_HL65_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000014, (_val))
#define MODIFY_HL65_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000014, (_val), (_mask))

/* AN XNP transmit 0 */
#define READ_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000016, (_val))
#define WRITE_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000016, (_val))
#define MODIFY_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000016, (_val), (_mask))

/* AN XNP transmit 1 */
#define READ_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000017, (_val))
#define WRITE_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000017, (_val))
#define MODIFY_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000017, (_val), (_mask))

/* AN XNP transmit 2 */
#define READ_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000018, (_val))
#define WRITE_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000018, (_val))
#define MODIFY_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000018, (_val), (_mask))

/* AN LP XNP ability 0 */
#define READ_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY0r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000019, (_val))
#define WRITE_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY0r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000019, (_val))
#define MODIFY_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY0r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000019, (_val), (_mask))

/* AN LP XNP ability 1 */
#define READ_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY1r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x3800001a, (_val))
#define WRITE_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY1r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x3800001a, (_val))
#define MODIFY_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY1r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x3800001a, (_val), (_mask))

/* AN LP XNP ability 2 */
#define READ_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY2r(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x3800001b, (_val))
#define WRITE_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY2r(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x3800001b, (_val))
#define MODIFY_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY2r(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x3800001b, (_val), (_mask))


/****************************************************************************
 * Hypercore_IEEE_CL73_AN_ieee3Blk
 ***************************************************************************/

/* Autonegotiation Backplane Ethernet status */
#define READ_HL65_AN_IEEE3BLK_AN_BPSTATUSr(_unit, _pc, _val) \
             HL65_REG_READ((_unit), (_pc), 0x00, 0x38000030, (_val))
#define WRITE_HL65_AN_IEEE3BLK_AN_BPSTATUSr(_unit, _pc, _val) \
             HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000030, (_val))
#define MODIFY_HL65_AN_IEEE3BLK_AN_BPSTATUSr(_unit, _pc, _val, _mask) \
             HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000030, (_val), (_mask))


/****************************************************************************
 * Hypercore_IEEE_CL22_ieee0Blk
 ***************************************************************************/
/****************************************************************************
 * ieee0Blk :: MIICntl
 ***************************************************************************/
/* ieee0Blk :: MIICntl :: rst_hw [15:15] */
#define IEEE0BLK_MIICNTL_RST_HW_MASK                               0x8000
#define IEEE0BLK_MIICNTL_RST_HW_ALIGN                              0
#define IEEE0BLK_MIICNTL_RST_HW_BITS                               1
#define IEEE0BLK_MIICNTL_RST_HW_SHIFT                              15

/* ieee0Blk :: MIICntl :: gloopback [14:14] */
#define IEEE0BLK_MIICNTL_GLOOPBACK_MASK                            0x4000
#define IEEE0BLK_MIICNTL_GLOOPBACK_ALIGN                           0
#define IEEE0BLK_MIICNTL_GLOOPBACK_BITS                            1
#define IEEE0BLK_MIICNTL_GLOOPBACK_SHIFT                           14

/* ieee0Blk :: MIICntl :: manual_speed0 [13:13] */
#define IEEE0BLK_MIICNTL_MANUAL_SPEED0_MASK                        0x2000
#define IEEE0BLK_MIICNTL_MANUAL_SPEED0_ALIGN                       0
#define IEEE0BLK_MIICNTL_MANUAL_SPEED0_BITS                        1
#define IEEE0BLK_MIICNTL_MANUAL_SPEED0_SHIFT                       13

/* ieee0Blk :: MIICntl :: autoneg_enable [12:12] */
#define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_MASK                       0x1000
#define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_ALIGN                      0
#define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_BITS                       1
#define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_SHIFT                      12

/* ieee0Blk :: MIICntl :: pwrdwn_sw [11:11] */
#define IEEE0BLK_MIICNTL_PWRDWN_SW_MASK                            0x0800
#define IEEE0BLK_MIICNTL_PWRDWN_SW_ALIGN                           0
#define IEEE0BLK_MIICNTL_PWRDWN_SW_BITS                            1
#define IEEE0BLK_MIICNTL_PWRDWN_SW_SHIFT                           11

/* ieee0Blk :: MIICntl :: reserved0 [10:10] */
#define IEEE0BLK_MIICNTL_RESERVED0_MASK                            0x0400
#define IEEE0BLK_MIICNTL_RESERVED0_ALIGN                           0
#define IEEE0BLK_MIICNTL_RESERVED0_BITS                            1
#define IEEE0BLK_MIICNTL_RESERVED0_SHIFT                           10

/* ieee0Blk :: MIICntl :: restart_autoneg [09:09] */
#define IEEE0BLK_MIICNTL_RESTART_AUTONEG_MASK                      0x0200
#define IEEE0BLK_MIICNTL_RESTART_AUTONEG_ALIGN                     0
#define IEEE0BLK_MIICNTL_RESTART_AUTONEG_BITS                      1
#define IEEE0BLK_MIICNTL_RESTART_AUTONEG_SHIFT                     9

/* ieee0Blk :: MIICntl :: full_duplex [08:08] */
#define IEEE0BLK_MIICNTL_FULL_DUPLEX_MASK                          0x0100
#define IEEE0BLK_MIICNTL_FULL_DUPLEX_ALIGN                         0
#define IEEE0BLK_MIICNTL_FULL_DUPLEX_BITS                          1
#define IEEE0BLK_MIICNTL_FULL_DUPLEX_SHIFT                         8

/* ieee0Blk :: MIICntl :: collision_test_en [07:07] */
#define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_MASK                    0x0080
#define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_ALIGN                   0
#define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_BITS                    1
#define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_SHIFT                   7

/* ieee0Blk :: MIICntl :: manual_speed1 [06:06] */
#define IEEE0BLK_MIICNTL_MANUAL_SPEED1_MASK                        0x0040
#define IEEE0BLK_MIICNTL_MANUAL_SPEED1_ALIGN                       0
#define IEEE0BLK_MIICNTL_MANUAL_SPEED1_BITS                        1
#define IEEE0BLK_MIICNTL_MANUAL_SPEED1_SHIFT                       6

/* ieee0Blk :: MIICntl :: reserved1 [05:00] */
#define IEEE0BLK_MIICNTL_RESERVED1_MASK                            0x003f
#define IEEE0BLK_MIICNTL_RESERVED1_ALIGN                           0
#define IEEE0BLK_MIICNTL_RESERVED1_BITS                            6
#define IEEE0BLK_MIICNTL_RESERVED1_SHIFT                           0


/****************************************************************************
 * ieee0Blk :: MIIStat
 ***************************************************************************/
/* ieee0Blk :: MIIStat :: s100BASE_T4_capable [15:15] */
#define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_MASK                  0x8000
#define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_ALIGN                 0
#define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_BITS                  1
#define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_SHIFT                 15

/* ieee0Blk :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */
#define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK       0x4000
#define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN      0
#define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS       1
#define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT      14

/* ieee0Blk :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */
#define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK       0x2000
#define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN      0
#define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS       1
#define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT      13

/* ieee0Blk :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */
#define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK        0x1000
#define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN       0
#define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS        1
#define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT       12

/* ieee0Blk :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */
#define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK        0x0800
#define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN       0
#define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS        1
#define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT       11

/* ieee0Blk :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */
#define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK      0x0400
#define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN     0
#define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS      1
#define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT     10

/* ieee0Blk :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */
#define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK      0x0200
#define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN     0
#define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS      1
#define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT     9

/* ieee0Blk :: MIIStat :: extended_status [08:08] */
#define IEEE0BLK_MIISTAT_EXTENDED_STATUS_MASK                      0x0100
#define IEEE0BLK_MIISTAT_EXTENDED_STATUS_ALIGN                     0
#define IEEE0BLK_MIISTAT_EXTENDED_STATUS_BITS                      1
#define IEEE0BLK_MIISTAT_EXTENDED_STATUS_SHIFT                     8

/* ieee0Blk :: MIIStat :: reserved0 [07:07] */
#define IEEE0BLK_MIISTAT_RESERVED0_MASK                            0x0080
#define IEEE0BLK_MIISTAT_RESERVED0_ALIGN                           0
#define IEEE0BLK_MIISTAT_RESERVED0_BITS                            1
#define IEEE0BLK_MIISTAT_RESERVED0_SHIFT                           7

/* ieee0Blk :: MIIStat :: mf_preamble_supression [06:06] */
#define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK               0x0040
#define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN              0
#define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS               1
#define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT              6

/* ieee0Blk :: MIIStat :: autoneg_complete [05:05] */
#define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_MASK                     0x0020
#define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_ALIGN                    0
#define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_BITS                     1
#define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_SHIFT                    5

/* ieee0Blk :: MIIStat :: remote_fault [04:04] */
#define IEEE0BLK_MIISTAT_REMOTE_FAULT_MASK                         0x0010
#define IEEE0BLK_MIISTAT_REMOTE_FAULT_ALIGN                        0
#define IEEE0BLK_MIISTAT_REMOTE_FAULT_BITS                         1
#define IEEE0BLK_MIISTAT_REMOTE_FAULT_SHIFT                        4

/* ieee0Blk :: MIIStat :: autoneg_ability [03:03] */
#define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_MASK                      0x0008
#define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_ALIGN                     0
#define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_BITS                      1
#define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_SHIFT                     3

/* ieee0Blk :: MIIStat :: link_status [02:02] */
#define IEEE0BLK_MIISTAT_LINK_STATUS_MASK                          0x0004
#define IEEE0BLK_MIISTAT_LINK_STATUS_ALIGN                         0
#define IEEE0BLK_MIISTAT_LINK_STATUS_BITS                          1
#define IEEE0BLK_MIISTAT_LINK_STATUS_SHIFT                         2

/* ieee0Blk :: MIIStat :: jabber_detect [01:01] */
#define IEEE0BLK_MIISTAT_JABBER_DETECT_MASK                        0x0002
#define IEEE0BLK_MIISTAT_JABBER_DETECT_ALIGN                       0
#define IEEE0BLK_MIISTAT_JABBER_DETECT_BITS                        1
#define IEEE0BLK_MIISTAT_JABBER_DETECT_SHIFT                       1

/* ieee0Blk :: MIIStat :: extended_capability [00:00] */
#define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_MASK                  0x0001
#define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_ALIGN                 0
#define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_BITS                  1
#define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_SHIFT                 0


/****************************************************************************
 * ieee0Blk :: Id1
 ***************************************************************************/
/* ieee0Blk :: Id1 :: regid [15:00] */
#define IEEE0BLK_ID1_REGID_MASK                                    0xffff
#define IEEE0BLK_ID1_REGID_ALIGN                                   0
#define IEEE0BLK_ID1_REGID_BITS                                    16
#define IEEE0BLK_ID1_REGID_SHIFT                                   0


/****************************************************************************
 * ieee0Blk :: Id2
 ***************************************************************************/
/* ieee0Blk :: Id2 :: regid [15:00] */
#define IEEE0BLK_ID2_REGID_MASK                                    0xffff
#define IEEE0BLK_ID2_REGID_ALIGN                                   0
#define IEEE0BLK_ID2_REGID_BITS                                    16
#define IEEE0BLK_ID2_REGID_SHIFT                                   0


/****************************************************************************
 * ieee0Blk :: AutoNegAdv
 ***************************************************************************/
/* ieee0Blk :: AutoNegAdv :: next_page [15:15] */
#define IEEE0BLK_AUTONEGADV_NEXT_PAGE_MASK                         0x8000
#define IEEE0BLK_AUTONEGADV_NEXT_PAGE_ALIGN                        0
#define IEEE0BLK_AUTONEGADV_NEXT_PAGE_BITS                         1
#define IEEE0BLK_AUTONEGADV_NEXT_PAGE_SHIFT                        15

/* ieee0Blk :: AutoNegAdv :: reserved0 [14:14] */
#define IEEE0BLK_AUTONEGADV_RESERVED0_MASK                         0x4000
#define IEEE0BLK_AUTONEGADV_RESERVED0_ALIGN                        0
#define IEEE0BLK_AUTONEGADV_RESERVED0_BITS                         1
#define IEEE0BLK_AUTONEGADV_RESERVED0_SHIFT                        14

/* ieee0Blk :: AutoNegAdv :: remote_fault [13:12] */
#define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_MASK                      0x3000
#define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_ALIGN                     0
#define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_BITS                      2
#define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_SHIFT                     12

/* ieee0Blk :: AutoNegAdv :: reserved1 [11:09] */
#define IEEE0BLK_AUTONEGADV_RESERVED1_MASK                         0x0e00
#define IEEE0BLK_AUTONEGADV_RESERVED1_ALIGN                        0
#define IEEE0BLK_AUTONEGADV_RESERVED1_BITS                         3
#define IEEE0BLK_AUTONEGADV_RESERVED1_SHIFT                        9

/* ieee0Blk :: AutoNegAdv :: pause [08:07] */
#define IEEE0BLK_AUTONEGADV_PAUSE_MASK                             0x0180
#define IEEE0BLK_AUTONEGADV_PAUSE_ALIGN                            0
#define IEEE0BLK_AUTONEGADV_PAUSE_BITS                             2
#define IEEE0BLK_AUTONEGADV_PAUSE_SHIFT                            7

/* ieee0Blk :: AutoNegAdv :: half_duplex [06:06] */
#define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_MASK                       0x0040
#define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_ALIGN                      0
#define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_BITS                       1
#define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_SHIFT                      6

/* ieee0Blk :: AutoNegAdv :: full_duplex [05:05] */
#define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_MASK                       0x0020
#define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_ALIGN                      0
#define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_BITS                       1
#define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_SHIFT                      5

/* ieee0Blk :: AutoNegAdv :: reserved2 [04:00] */
#define IEEE0BLK_AUTONEGADV_RESERVED2_MASK                         0x001f
#define IEEE0BLK_AUTONEGADV_RESERVED2_ALIGN                        0
#define IEEE0BLK_AUTONEGADV_RESERVED2_BITS                         5
#define IEEE0BLK_AUTONEGADV_RESERVED2_SHIFT                        0


/****************************************************************************
 * ieee0Blk :: AutoNegLPAbil
 ***************************************************************************/
/* ieee0Blk :: AutoNegLPAbil :: next_page [15:15] */
#define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_MASK                      0x8000
#define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_ALIGN                     0
#define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_BITS                      1
#define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_SHIFT                     15

/* ieee0Blk :: AutoNegLPAbil :: acknowledge [14:14] */
#define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_MASK                    0x4000
#define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN                   0
#define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_BITS                    1
#define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT                   14

/* ieee0Blk :: AutoNegLPAbil :: remote_fault [13:12] */
#define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_MASK                   0x3000
#define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_ALIGN                  0
#define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_BITS                   2
#define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_SHIFT                  12

/* ieee0Blk :: AutoNegLPAbil :: reserved0 [11:09] */
#define IEEE0BLK_AUTONEGLPABIL_RESERVED0_MASK                      0x0e00
#define IEEE0BLK_AUTONEGLPABIL_RESERVED0_ALIGN                     0
#define IEEE0BLK_AUTONEGLPABIL_RESERVED0_BITS                      3
#define IEEE0BLK_AUTONEGLPABIL_RESERVED0_SHIFT                     9

/* ieee0Blk :: AutoNegLPAbil :: pause [08:07] */
#define IEEE0BLK_AUTONEGLPABIL_PAUSE_MASK                          0x0180
#define IEEE0BLK_AUTONEGLPABIL_PAUSE_ALIGN                         0
#define IEEE0BLK_AUTONEGLPABIL_PAUSE_BITS                          2
#define IEEE0BLK_AUTONEGLPABIL_PAUSE_SHIFT                         7

/* ieee0Blk :: AutoNegLPAbil :: half_duplex [06:06] */
#define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_MASK                    0x0040
#define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_ALIGN                   0
#define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_BITS                    1
#define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_SHIFT                   6

/* ieee0Blk :: AutoNegLPAbil :: full_duplex [05:05] */
#define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_MASK                    0x0020
#define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_ALIGN                   0
#define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_BITS                    1
#define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_SHIFT                   5

/* ieee0Blk :: AutoNegLPAbil :: reserved1 [04:01] */
#define IEEE0BLK_AUTONEGLPABIL_RESERVED1_MASK                      0x001e
#define IEEE0BLK_AUTONEGLPABIL_RESERVED1_ALIGN                     0
#define IEEE0BLK_AUTONEGLPABIL_RESERVED1_BITS                      4
#define IEEE0BLK_AUTONEGLPABIL_RESERVED1_SHIFT                     1

/* ieee0Blk :: AutoNegLPAbil :: sgmii_mode [00:00] */
#define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_MASK                     0x0001
#define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_ALIGN                    0
#define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_BITS                     1
#define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_SHIFT                    0


/****************************************************************************
 * ieee0Blk :: AutoNegExp
 ***************************************************************************/
/* ieee0Blk :: AutoNegExp :: reserved0 [15:03] */
#define IEEE0BLK_AUTONEGEXP_RESERVED0_MASK                         0xfff8
#define IEEE0BLK_AUTONEGEXP_RESERVED0_ALIGN                        0
#define IEEE0BLK_AUTONEGEXP_RESERVED0_BITS                         13
#define IEEE0BLK_AUTONEGEXP_RESERVED0_SHIFT                        3

/* ieee0Blk :: AutoNegExp :: next_page_ability [02:02] */
#define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK                 0x0004
#define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN                0
#define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS                 1
#define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT                2

/* ieee0Blk :: AutoNegExp :: page_received [01:01] */
#define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_MASK                     0x0002
#define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_ALIGN                    0
#define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_BITS                     1
#define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_SHIFT                    1

/* ieee0Blk :: AutoNegExp :: reserved1 [00:00] */
#define IEEE0BLK_AUTONEGEXP_RESERVED1_MASK                         0x0001
#define IEEE0BLK_AUTONEGEXP_RESERVED1_ALIGN                        0
#define IEEE0BLK_AUTONEGEXP_RESERVED1_BITS                         1
#define IEEE0BLK_AUTONEGEXP_RESERVED1_SHIFT                        0


/****************************************************************************
 * ieee0Blk :: AutoNegNP
 ***************************************************************************/
/* ieee0Blk :: AutoNegNP :: Next_Page [15:15] */
#define IEEE0BLK_AUTONEGNP_NEXT_PAGE_MASK                          0x8000
#define IEEE0BLK_AUTONEGNP_NEXT_PAGE_ALIGN                         0
#define IEEE0BLK_AUTONEGNP_NEXT_PAGE_BITS                          1
#define IEEE0BLK_AUTONEGNP_NEXT_PAGE_SHIFT                         15

/* ieee0Blk :: AutoNegNP :: Ack [14:14] */
#define IEEE0BLK_AUTONEGNP_ACK_MASK                                0x4000
#define IEEE0BLK_AUTONEGNP_ACK_ALIGN                               0
#define IEEE0BLK_AUTONEGNP_ACK_BITS                                1
#define IEEE0BLK_AUTONEGNP_ACK_SHIFT                               14

/* ieee0Blk :: AutoNegNP :: Message_Page [13:13] */
#define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_MASK                       0x2000
#define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_ALIGN                      0
#define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_BITS                       1
#define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_SHIFT                      13

/* ieee0Blk :: AutoNegNP :: Ack2 [12:12] */
#define IEEE0BLK_AUTONEGNP_ACK2_MASK                               0x1000
#define IEEE0BLK_AUTONEGNP_ACK2_ALIGN                              0
#define IEEE0BLK_AUTONEGNP_ACK2_BITS                               1
#define IEEE0BLK_AUTONEGNP_ACK2_SHIFT                              12

/* ieee0Blk :: AutoNegNP :: Toggle [11:11] */
#define IEEE0BLK_AUTONEGNP_TOGGLE_MASK                             0x0800
#define IEEE0BLK_AUTONEGNP_TOGGLE_ALIGN                            0
#define IEEE0BLK_AUTONEGNP_TOGGLE_BITS                             1
#define IEEE0BLK_AUTONEGNP_TOGGLE_SHIFT                            11

/* ieee0Blk :: AutoNegNP :: Message [10:00] */
#define IEEE0BLK_AUTONEGNP_MESSAGE_MASK                            0x07ff
#define IEEE0BLK_AUTONEGNP_MESSAGE_ALIGN                           0
#define IEEE0BLK_AUTONEGNP_MESSAGE_BITS                            11
#define IEEE0BLK_AUTONEGNP_MESSAGE_SHIFT                           0


/****************************************************************************
 * ieee0Blk :: AutoNegLPAbil2
 ***************************************************************************/
/* ieee0Blk :: AutoNegLPAbil2 :: Next_Page [15:15] */
#define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_MASK                     0x8000
#define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_ALIGN                    0
#define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_BITS                     1
#define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_SHIFT                    15

/* ieee0Blk :: AutoNegLPAbil2 :: Ack [14:14] */
#define IEEE0BLK_AUTONEGLPABIL2_ACK_MASK                           0x4000
#define IEEE0BLK_AUTONEGLPABIL2_ACK_ALIGN                          0
#define IEEE0BLK_AUTONEGLPABIL2_ACK_BITS                           1
#define IEEE0BLK_AUTONEGLPABIL2_ACK_SHIFT                          14

/* ieee0Blk :: AutoNegLPAbil2 :: Message_Page [13:13] */
#define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_MASK                  0x2000
#define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN                 0
#define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_BITS                  1
#define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT                 13

/* ieee0Blk :: AutoNegLPAbil2 :: Ack2 [12:12] */
#define IEEE0BLK_AUTONEGLPABIL2_ACK2_MASK                          0x1000
#define IEEE0BLK_AUTONEGLPABIL2_ACK2_ALIGN                         0
#define IEEE0BLK_AUTONEGLPABIL2_ACK2_BITS                          1
#define IEEE0BLK_AUTONEGLPABIL2_ACK2_SHIFT                         12

/* ieee0Blk :: AutoNegLPAbil2 :: Toggle [11:11] */
#define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_MASK                        0x0800
#define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_ALIGN                       0
#define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_BITS                        1
#define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_SHIFT                       11

/* ieee0Blk :: AutoNegLPAbil2 :: Message [10:00] */
#define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_MASK                       0x07ff
#define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_ALIGN                      0
#define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_BITS                       11
#define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_SHIFT                      0


/****************************************************************************
 * ieee0Blk :: MIIextStat
 ***************************************************************************/
/* ieee0Blk :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK   0x8000
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN  0
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS   1
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT  15

/* ieee0Blk :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK   0x4000
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN  0
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS   1
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT  14

/* ieee0Blk :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK   0x2000
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN  0
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS   1
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT  13

/* ieee0Blk :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK   0x1000
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN  0
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS   1
#define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT  12

/* ieee0Blk :: MIIextStat :: reserved0 [11:00] */
#define IEEE0BLK_MIIEXTSTAT_RESERVED0_MASK                         0x0fff
#define IEEE0BLK_MIIEXTSTAT_RESERVED0_ALIGN                        0
#define IEEE0BLK_MIIEXTSTAT_RESERVED0_BITS                         12
#define IEEE0BLK_MIIEXTSTAT_RESERVED0_SHIFT                        0


/****************************************************************************
 * Hypercore_USER_XgxsBlk0
 ***************************************************************************/
/****************************************************************************
 * XgxsBlk0 :: xgxsControl
 ***************************************************************************/
/* XgxsBlk0 :: xgxsControl :: pgen_en [15:15] */
#define XGXSBLK0_XGXSCONTROL_PGEN_EN_MASK                          0x8000
#define XGXSBLK0_XGXSCONTROL_PGEN_EN_ALIGN                         0
#define XGXSBLK0_XGXSCONTROL_PGEN_EN_BITS                          1
#define XGXSBLK0_XGXSCONTROL_PGEN_EN_SHIFT                         15

/* XgxsBlk0 :: xgxsControl :: pcmp_en [14:14] */
#define XGXSBLK0_XGXSCONTROL_PCMP_EN_MASK                          0x4000
#define XGXSBLK0_XGXSCONTROL_PCMP_EN_ALIGN                         0
#define XGXSBLK0_XGXSCONTROL_PCMP_EN_BITS                          1
#define XGXSBLK0_XGXSCONTROL_PCMP_EN_SHIFT                         14

/* XgxsBlk0 :: xgxsControl :: start_sequencer [13:13] */
#define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_MASK                  0x2000
#define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_ALIGN                 0
#define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_BITS                  1
#define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_SHIFT                 13

/* XgxsBlk0 :: xgxsControl :: reset_anlg [12:12] */
#define XGXSBLK0_XGXSCONTROL_RESET_ANLG_MASK                       0x1000
#define XGXSBLK0_XGXSCONTROL_RESET_ANLG_ALIGN                      0
#define XGXSBLK0_XGXSCONTROL_RESET_ANLG_BITS                       1
#define XGXSBLK0_XGXSCONTROL_RESET_ANLG_SHIFT                      12

/* XgxsBlk0 :: xgxsControl :: mode_10g [11:08] */
#define XGXSBLK0_XGXSCONTROL_MODE_10G_MASK                         0x0f00
#define XGXSBLK0_XGXSCONTROL_MODE_10G_ALIGN                        0
#define XGXSBLK0_XGXSCONTROL_MODE_10G_BITS                         4
#define XGXSBLK0_XGXSCONTROL_MODE_10G_SHIFT                        8
#define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS                         0
#define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXG_nCC                     1
#define XGXSBLK0_XGXSCONTROL_MODE_10G_IndLane_OS5                  5
#define XGXSBLK0_XGXSCONTROL_MODE_10G_Indlanes                     6
#define XGXSBLK0_XGXSCONTROL_MODE_10G_PCI                          7
#define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS_nLQ                     8
#define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS_nLQnCC                  9
#define XGXSBLK0_XGXSCONTROL_MODE_10G_PBypass                      10
#define XGXSBLK0_XGXSCONTROL_MODE_10G_PBypass_nDSK                 11
#define XGXSBLK0_XGXSCONTROL_MODE_10G_ComboCoreMode                12
#define XGXSBLK0_XGXSCONTROL_MODE_10G_Clocks_off                   15

/* XgxsBlk0 :: xgxsControl :: pll_bypass [07:07] */
#define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_MASK                       0x0080
#define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_ALIGN                      0
#define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_BITS                       1
#define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_SHIFT                      7

/* XgxsBlk0 :: xgxsControl :: rloop [06:06] */
#define XGXSBLK0_XGXSCONTROL_RLOOP_MASK                            0x0040
#define XGXSBLK0_XGXSCONTROL_RLOOP_ALIGN                           0
#define XGXSBLK0_XGXSCONTROL_RLOOP_BITS                            1
#define XGXSBLK0_XGXSCONTROL_RLOOP_SHIFT                           6

/* XgxsBlk0 :: xgxsControl :: reserved0 [05:05] */
#define XGXSBLK0_XGXSCONTROL_RESERVED0_MASK                        0x0020
#define XGXSBLK0_XGXSCONTROL_RESERVED0_ALIGN                       0
#define XGXSBLK0_XGXSCONTROL_RESERVED0_BITS                        1
#define XGXSBLK0_XGXSCONTROL_RESERVED0_SHIFT                       5

/* XgxsBlk0 :: xgxsControl :: mdio_cont_en [04:04] */
#define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_MASK                     0x0010
#define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_ALIGN                    0
#define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_BITS                     1
#define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_SHIFT                    4

/* XgxsBlk0 :: xgxsControl :: cdet_en [03:03] */
#define XGXSBLK0_XGXSCONTROL_CDET_EN_MASK                          0x0008
#define XGXSBLK0_XGXSCONTROL_CDET_EN_ALIGN                         0
#define XGXSBLK0_XGXSCONTROL_CDET_EN_BITS                          1
#define XGXSBLK0_XGXSCONTROL_CDET_EN_SHIFT                         3

/* XgxsBlk0 :: xgxsControl :: eden [02:02] */
#define XGXSBLK0_XGXSCONTROL_EDEN_MASK                             0x0004
#define XGXSBLK0_XGXSCONTROL_EDEN_ALIGN                            0
#define XGXSBLK0_XGXSCONTROL_EDEN_BITS                             1
#define XGXSBLK0_XGXSCONTROL_EDEN_SHIFT                            2

/* XgxsBlk0 :: xgxsControl :: afrst_en [01:01] */
#define XGXSBLK0_XGXSCONTROL_AFRST_EN_MASK                         0x0002
#define XGXSBLK0_XGXSCONTROL_AFRST_EN_ALIGN                        0
#define XGXSBLK0_XGXSCONTROL_AFRST_EN_BITS                         1
#define XGXSBLK0_XGXSCONTROL_AFRST_EN_SHIFT                        1

/* XgxsBlk0 :: xgxsControl :: txcko_div [00:00] */
#define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_MASK                        0x0001
#define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_ALIGN                       0
#define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_BITS                        1
#define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_SHIFT                       0


/****************************************************************************
 * XgxsBlk0 :: xgxsStatus
 ***************************************************************************/
/* XgxsBlk0 :: xgxsStatus :: status_en [15:15] */
#define XGXSBLK0_XGXSSTATUS_STATUS_EN_MASK                         0x8000
#define XGXSBLK0_XGXSSTATUS_STATUS_EN_ALIGN                        0
#define XGXSBLK0_XGXSSTATUS_STATUS_EN_BITS                         1
#define XGXSBLK0_XGXSSTATUS_STATUS_EN_SHIFT                        15

/* XgxsBlk0 :: xgxsStatus :: reserved0 [14:14] */
#define XGXSBLK0_XGXSSTATUS_RESERVED0_MASK                         0x4000
#define XGXSBLK0_XGXSSTATUS_RESERVED0_ALIGN                        0
#define XGXSBLK0_XGXSSTATUS_RESERVED0_BITS                         1
#define XGXSBLK0_XGXSSTATUS_RESERVED0_SHIFT                        14

/* XgxsBlk0 :: xgxsStatus :: tx_remote_fault [13:13] */
#define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_MASK                   0x2000
#define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_ALIGN                  0
#define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_BITS                   1
#define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_SHIFT                  13

/* XgxsBlk0 :: xgxsStatus :: rx_remote_fault [12:12] */
#define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_MASK                   0x1000
#define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_ALIGN                  0
#define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_BITS                   1
#define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_SHIFT                  12

/* XgxsBlk0 :: xgxsStatus :: txpll_lock [11:11] */
#define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_MASK                        0x0800
#define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_ALIGN                       0
#define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_BITS                        1
#define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_SHIFT                       11

/* XgxsBlk0 :: xgxsStatus :: txd_fifo_err [10:10] */
#define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_MASK                      0x0400
#define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_ALIGN                     0
#define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_BITS                      1
#define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_SHIFT                     10

/* XgxsBlk0 :: xgxsStatus :: sequencer_done [09:09] */
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_MASK                    0x0200
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_ALIGN                   0
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_BITS                    1
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_SHIFT                   9

/* XgxsBlk0 :: xgxsStatus :: sequencer_pass [08:08] */
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_MASK                    0x0100
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_ALIGN                   0
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_BITS                    1
#define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_SHIFT                   8

/* XgxsBlk0 :: xgxsStatus :: rxferr [07:04] */
#define XGXSBLK0_XGXSSTATUS_RXFERR_MASK                            0x00f0
#define XGXSBLK0_XGXSSTATUS_RXFERR_ALIGN                           0
#define XGXSBLK0_XGXSSTATUS_RXFERR_BITS                            4
#define XGXSBLK0_XGXSSTATUS_RXFERR_SHIFT                           4

/* XgxsBlk0 :: xgxsStatus :: pll_mode_afe [03:03] */
#define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_MASK                      0x0008
#define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_ALIGN                     0
#define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_BITS                      1
#define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_SHIFT                     3

/* XgxsBlk0 :: xgxsStatus :: ckcmp_unflow [02:02] */
#define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_MASK                      0x0004
#define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_ALIGN                     0
#define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_BITS                      1
#define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_SHIFT                     2

/* XgxsBlk0 :: xgxsStatus :: ckcmp_ovflow [01:01] */
#define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_MASK                      0x0002
#define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_ALIGN                     0
#define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_BITS                      1
#define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_SHIFT                     1

/* XgxsBlk0 :: xgxsStatus :: skew_status [00:00] */
#define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_MASK                       0x0001
#define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_ALIGN                      0
#define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_BITS                       1
#define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_SHIFT                      0


/****************************************************************************
 * XgxsBlk0 :: xgmiiIdle
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiIdle :: I [15:08] */
#define XGXSBLK0_XGMIIIDLE_I_MASK                                  0xff00
#define XGXSBLK0_XGMIIIDLE_I_ALIGN                                 0
#define XGXSBLK0_XGMIIIDLE_I_BITS                                  8
#define XGXSBLK0_XGMIIIDLE_I_SHIFT                                 8

/* XgxsBlk0 :: xgmiiIdle :: Ib [07:00] */
#define XGXSBLK0_XGMIIIDLE_IB_MASK                                 0x00ff
#define XGXSBLK0_XGMIIIDLE_IB_ALIGN                                0
#define XGXSBLK0_XGMIIIDLE_IB_BITS                                 8
#define XGXSBLK0_XGMIIIDLE_IB_SHIFT                                0


/****************************************************************************
 * XgxsBlk0 :: xgmiiSync
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiSync :: K [15:08] */
#define XGXSBLK0_XGMIISYNC_K_MASK                                  0xff00
#define XGXSBLK0_XGMIISYNC_K_ALIGN                                 0
#define XGXSBLK0_XGMIISYNC_K_BITS                                  8
#define XGXSBLK0_XGMIISYNC_K_SHIFT                                 8

/* XgxsBlk0 :: xgmiiSync :: Kb [07:00] */
#define XGXSBLK0_XGMIISYNC_KB_MASK                                 0x00ff
#define XGXSBLK0_XGMIISYNC_KB_ALIGN                                0
#define XGXSBLK0_XGMIISYNC_KB_BITS                                 8
#define XGXSBLK0_XGMIISYNC_KB_SHIFT                                0


/****************************************************************************
 * XgxsBlk0 :: xgmiiSkip
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiSkip :: R [15:08] */
#define XGXSBLK0_XGMIISKIP_R_MASK                                  0xff00
#define XGXSBLK0_XGMIISKIP_R_ALIGN                                 0
#define XGXSBLK0_XGMIISKIP_R_BITS                                  8
#define XGXSBLK0_XGMIISKIP_R_SHIFT                                 8

/* XgxsBlk0 :: xgmiiSkip :: Rb [07:00] */
#define XGXSBLK0_XGMIISKIP_RB_MASK                                 0x00ff
#define XGXSBLK0_XGMIISKIP_RB_ALIGN                                0
#define XGXSBLK0_XGMIISKIP_RB_BITS                                 8
#define XGXSBLK0_XGMIISKIP_RB_SHIFT                                0


/****************************************************************************
 * XgxsBlk0 :: xgmiiSopEop
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiSopEop :: S [15:08] */
#define XGXSBLK0_XGMIISOPEOP_S_MASK                                0xff00
#define XGXSBLK0_XGMIISOPEOP_S_ALIGN                               0
#define XGXSBLK0_XGMIISOPEOP_S_BITS                                8
#define XGXSBLK0_XGMIISOPEOP_S_SHIFT                               8

/* XgxsBlk0 :: xgmiiSopEop :: T [07:00] */
#define XGXSBLK0_XGMIISOPEOP_T_MASK                                0x00ff
#define XGXSBLK0_XGMIISOPEOP_T_ALIGN                               0
#define XGXSBLK0_XGMIISOPEOP_T_BITS                                8
#define XGXSBLK0_XGMIISOPEOP_T_SHIFT                               0


/****************************************************************************
 * XgxsBlk0 :: xgmiiAlign
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiAlign :: E [15:08] */
#define XGXSBLK0_XGMIIALIGN_E_MASK                                 0xff00
#define XGXSBLK0_XGMIIALIGN_E_ALIGN                                0
#define XGXSBLK0_XGMIIALIGN_E_BITS                                 8
#define XGXSBLK0_XGMIIALIGN_E_SHIFT                                8

/* XgxsBlk0 :: xgmiiAlign :: A [07:00] */
#define XGXSBLK0_XGMIIALIGN_A_MASK                                 0x00ff
#define XGXSBLK0_XGMIIALIGN_A_ALIGN                                0
#define XGXSBLK0_XGMIIALIGN_A_BITS                                 8
#define XGXSBLK0_XGMIIALIGN_A_SHIFT                                0


/****************************************************************************
 * XgxsBlk0 :: xgmiiRcontrol
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiRcontrol :: reserved0 [15:15] */
#define XGXSBLK0_XGMIIRCONTROL_RESERVED0_MASK                      0x8000
#define XGXSBLK0_XGMIIRCONTROL_RESERVED0_ALIGN                     0
#define XGXSBLK0_XGMIIRCONTROL_RESERVED0_BITS                      1
#define XGXSBLK0_XGMIIRCONTROL_RESERVED0_SHIFT                     15

/* XgxsBlk0 :: xgmiiRcontrol :: tx_lf0_en [14:14] */
#define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_MASK                      0x4000
#define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_ALIGN                     0
#define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_BITS                      1
#define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_SHIFT                     14

/* XgxsBlk0 :: xgmiiRcontrol :: tx_lf1_en [13:13] */
#define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_MASK                      0x2000
#define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_ALIGN                     0
#define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_BITS                      1
#define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_SHIFT                     13

/* XgxsBlk0 :: xgmiiRcontrol :: tx_lf2_en [12:12] */
#define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_MASK                      0x1000
#define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_ALIGN                     0
#define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_BITS                      1
#define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_SHIFT                     12

/* XgxsBlk0 :: xgmiiRcontrol :: force_inbndls_en [11:11] */
#define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_MASK               0x0800
#define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_ALIGN              0
#define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_BITS               1
#define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_SHIFT              11

/* XgxsBlk0 :: xgmiiRcontrol :: chk_end_en [10:10] */
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_MASK                     0x0400
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_ALIGN                    0
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_BITS                     1
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_SHIFT                    10

/* XgxsBlk0 :: xgmiiRcontrol :: chk_end_std_en [09:09] */
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_MASK                 0x0200
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_ALIGN                0
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_BITS                 1
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_SHIFT                9

/* XgxsBlk0 :: xgmiiRcontrol :: chk_end_force [08:08] */
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_MASK                  0x0100
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_ALIGN                 0
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_BITS                  1
#define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_SHIFT                 8

/* XgxsBlk0 :: xgmiiRcontrol :: reserved1 [07:07] */
#define XGXSBLK0_XGMIIRCONTROL_RESERVED1_MASK                      0x0080
#define XGXSBLK0_XGMIIRCONTROL_RESERVED1_ALIGN                     0
#define XGXSBLK0_XGMIIRCONTROL_RESERVED1_BITS                      1
#define XGXSBLK0_XGMIIRCONTROL_RESERVED1_SHIFT                     7

/* XgxsBlk0 :: xgmiiRcontrol :: scr_en_4lane [06:06] */
#define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_MASK                   0x0040
#define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_ALIGN                  0
#define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_BITS                   1
#define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_SHIFT                  6

/* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_noIPG_en [05:05] */
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_MASK                 0x0020
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_ALIGN                0
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_BITS                 1
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_SHIFT                5

/* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_afrst_en [04:04] */
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_MASK                 0x0010
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_ALIGN                0
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_BITS                 1
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_SHIFT                4

/* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_gt1_Icol_dis [03:03] */
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_MASK             0x0008
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_ALIGN            0
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_BITS             1
#define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_SHIFT            3

/* XgxsBlk0 :: xgmiiRcontrol :: reserved2 [02:00] */
#define XGXSBLK0_XGMIIRCONTROL_RESERVED2_MASK                      0x0007
#define XGXSBLK0_XGMIIRCONTROL_RESERVED2_ALIGN                     0
#define XGXSBLK0_XGMIIRCONTROL_RESERVED2_BITS                      3
#define XGXSBLK0_XGMIIRCONTROL_RESERVED2_SHIFT                     0


/****************************************************************************
 * XgxsBlk0 :: xgmiiTcontrol
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiTcontrol :: swapen [15:15] */
#define XGXSBLK0_XGMIITCONTROL_SWAPEN_MASK                         0x8000
#define XGXSBLK0_XGMIITCONTROL_SWAPEN_ALIGN                        0
#define XGXSBLK0_XGMIITCONTROL_SWAPEN_BITS                         1
#define XGXSBLK0_XGMIITCONTROL_SWAPEN_SHIFT                        15

/* XgxsBlk0 :: xgmiiTcontrol :: swap_lane_ind [14:14] */
#define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_MASK                  0x4000
#define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_ALIGN                 0
#define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_BITS                  1
#define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_SHIFT                 14

/* XgxsBlk0 :: xgmiiTcontrol :: pn_sel [13:13] */
#define XGXSBLK0_XGMIITCONTROL_PN_SEL_MASK                         0x2000
#define XGXSBLK0_XGMIITCONTROL_PN_SEL_ALIGN                        0
#define XGXSBLK0_XGMIITCONTROL_PN_SEL_BITS                         1
#define XGXSBLK0_XGMIITCONTROL_PN_SEL_SHIFT                        13

/* XgxsBlk0 :: xgmiiTcontrol :: reserved0 [12:09] */
#define XGXSBLK0_XGMIITCONTROL_RESERVED0_MASK                      0x1e00
#define XGXSBLK0_XGMIITCONTROL_RESERVED0_ALIGN                     0
#define XGXSBLK0_XGMIITCONTROL_RESERVED0_BITS                      4
#define XGXSBLK0_XGMIITCONTROL_RESERVED0_SHIFT                     9

/* XgxsBlk0 :: xgmiiTcontrol :: alignstat_rxlf_en [08:08] */
#define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_MASK              0x0100
#define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_ALIGN             0
#define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_BITS              1
#define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_SHIFT             8

/* XgxsBlk0 :: xgmiiTcontrol :: flip_txrx_lf [07:07] */
#define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_MASK                   0x0080
#define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_ALIGN                  0
#define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_BITS                   1
#define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_SHIFT                  7

/* XgxsBlk0 :: xgmiiTcontrol :: xenpak_lfclr_en [06:06] */
#define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_MASK                0x0040
#define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_ALIGN               0
#define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_BITS                1
#define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_SHIFT               6

/* XgxsBlk0 :: xgmiiTcontrol :: tx_xgmii_Tcol_old_en [05:05] */
#define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_MASK           0x0020
#define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_ALIGN          0
#define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_BITS           1
#define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_SHIFT          5

/* XgxsBlk0 :: xgmiiTcontrol :: tx_force_dpath_IorRF_en [04:04] */
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_MASK        0x0010
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_ALIGN       0
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_BITS        1
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_SHIFT       4

/* XgxsBlk0 :: xgmiiTcontrol :: tx_force_dpath_I_en [03:03] */
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_MASK            0x0008
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_ALIGN           0
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_BITS            1
#define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_SHIFT           3

/* XgxsBlk0 :: xgmiiTcontrol :: reserved1 [02:00] */
#define XGXSBLK0_XGMIITCONTROL_RESERVED1_MASK                      0x0007
#define XGXSBLK0_XGMIITCONTROL_RESERVED1_ALIGN                     0
#define XGXSBLK0_XGMIITCONTROL_RESERVED1_BITS                      3
#define XGXSBLK0_XGMIITCONTROL_RESERVED1_SHIFT                     0


/****************************************************************************
 * XgxsBlk0 :: xgmiiSwap
 ***************************************************************************/
/* XgxsBlk0 :: xgmiiSwap :: swap_count [15:00] */
#define XGXSBLK0_XGMIISWAP_SWAP_COUNT_MASK                         0xffff
#define XGXSBLK0_XGMIISWAP_SWAP_COUNT_ALIGN                        0
#define XGXSBLK0_XGMIISWAP_SWAP_COUNT_BITS                         16
#define XGXSBLK0_XGMIISWAP_SWAP_COUNT_SHIFT                        0


/****************************************************************************
 * XgxsBlk0 :: lssLsid
 ***************************************************************************/
/* XgxsBlk0 :: lssLsid :: lss_ls_id [15:08] */
#define XGXSBLK0_LSSLSID_LSS_LS_ID_MASK                            0xff00
#define XGXSBLK0_LSSLSID_LSS_LS_ID_ALIGN                           0
#define XGXSBLK0_LSSLSID_LSS_LS_ID_BITS                            8
#define XGXSBLK0_LSSLSID_LSS_LS_ID_SHIFT                           8

/* XgxsBlk0 :: lssLsid :: lss_domain_id [07:00] */
#define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_MASK                        0x00ff
#define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_ALIGN                       0
#define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_BITS                        8
#define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_SHIFT                       0


/****************************************************************************
 * XgxsBlk0 :: lssTinfo
 ***************************************************************************/
/* XgxsBlk0 :: lssTinfo :: lss_function_id [15:08] */
#define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_MASK                     0xff00
#define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_ALIGN                    0
#define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_BITS                     8
#define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_SHIFT                    8

/* XgxsBlk0 :: lssTinfo :: lssL_info_byte [07:00] */
#define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_MASK                      0x00ff
#define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_ALIGN                     0
#define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_BITS                      8
#define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_SHIFT                     0


/****************************************************************************
 * XgxsBlk0 :: lssRinfo
 ***************************************************************************/
/* XgxsBlk0 :: lssRinfo :: control_en [15:15] */
#define XGXSBLK0_LSSRINFO_CONTROL_EN_MASK                          0x8000
#define XGXSBLK0_LSSRINFO_CONTROL_EN_ALIGN                         0
#define XGXSBLK0_LSSRINFO_CONTROL_EN_BITS                          1
#define XGXSBLK0_LSSRINFO_CONTROL_EN_SHIFT                         15

/* XgxsBlk0 :: lssRinfo :: reserved0 [14:14] */
#define XGXSBLK0_LSSRINFO_RESERVED0_MASK                           0x4000
#define XGXSBLK0_LSSRINFO_RESERVED0_ALIGN                          0
#define XGXSBLK0_LSSRINFO_RESERVED0_BITS                           1
#define XGXSBLK0_LSSRINFO_RESERVED0_SHIFT                          14

/* XgxsBlk0 :: lssRinfo :: lss_ls_id8 [13:13] */
#define XGXSBLK0_LSSRINFO_LSS_LS_ID8_MASK                          0x2000
#define XGXSBLK0_LSSRINFO_LSS_LS_ID8_ALIGN                         0
#define XGXSBLK0_LSSRINFO_LSS_LS_ID8_BITS                          1
#define XGXSBLK0_LSSRINFO_LSS_LS_ID8_SHIFT                         13

/* XgxsBlk0 :: lssRinfo :: lss_domain_id8 [12:12] */
#define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_MASK                      0x1000
#define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_ALIGN                     0
#define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_BITS                      1
#define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_SHIFT                     12

/* XgxsBlk0 :: lssRinfo :: lss_function_id8 [11:11] */
#define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_MASK                    0x0800
#define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_ALIGN                   0
#define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_BITS                    1
#define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_SHIFT                   11

/* XgxsBlk0 :: lssRinfo :: lssL_info_byte8 [10:10] */
#define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_MASK                     0x0400
#define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_ALIGN                    0
#define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_BITS                     1
#define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_SHIFT                    10

/* XgxsBlk0 :: lssRinfo :: reserved1 [09:09] */
#define XGXSBLK0_LSSRINFO_RESERVED1_MASK                           0x0200
#define XGXSBLK0_LSSRINFO_RESERVED1_ALIGN                          0
#define XGXSBLK0_LSSRINFO_RESERVED1_BITS                           1
#define XGXSBLK0_LSSRINFO_RESERVED1_SHIFT                          9

/* XgxsBlk0 :: lssRinfo :: lssR_info_byte [08:00] */
#define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_MASK                      0x01ff
#define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_ALIGN                     0
#define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_BITS                      9
#define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_SHIFT                     0


/****************************************************************************
 * XgxsBlk0 :: mmdSelect
 ***************************************************************************/
/* XgxsBlk0 :: mmdSelect :: multiPRTs_en [15:15] */
#define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_MASK                       0x8000
#define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_ALIGN                      0
#define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_BITS                       1
#define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_SHIFT                      15

/* XgxsBlk0 :: mmdSelect :: multiMMDs_en [14:14] */
#define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_MASK                       0x4000
#define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_ALIGN                      0
#define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_BITS                       1
#define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_SHIFT                      14

/* XgxsBlk0 :: mmdSelect :: reserved0 [13:04] */
#define XGXSBLK0_MMDSELECT_RESERVED0_MASK                          0x3ff0
#define XGXSBLK0_MMDSELECT_RESERVED0_ALIGN                         0
#define XGXSBLK0_MMDSELECT_RESERVED0_BITS                          10
#define XGXSBLK0_MMDSELECT_RESERVED0_SHIFT                         4

/* XgxsBlk0 :: mmdSelect :: devAN_en [03:03] */
#define XGXSBLK0_MMDSELECT_DEVAN_EN_MASK                           0x0008
#define XGXSBLK0_MMDSELECT_DEVAN_EN_ALIGN                          0
#define XGXSBLK0_MMDSELECT_DEVAN_EN_BITS                           1
#define XGXSBLK0_MMDSELECT_DEVAN_EN_SHIFT                          3

/* XgxsBlk0 :: mmdSelect :: devPMD_en [02:02] */
#define XGXSBLK0_MMDSELECT_DEVPMD_EN_MASK                          0x0004
#define XGXSBLK0_MMDSELECT_DEVPMD_EN_ALIGN                         0
#define XGXSBLK0_MMDSELECT_DEVPMD_EN_BITS                          1
#define XGXSBLK0_MMDSELECT_DEVPMD_EN_SHIFT                         2

/* XgxsBlk0 :: mmdSelect :: devDEVAD_en [01:01] */
#define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_MASK                        0x0002
#define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_ALIGN                       0
#define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_BITS                        1
#define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_SHIFT                       1

/* XgxsBlk0 :: mmdSelect :: devCL22_en [00:00] */
#define XGXSBLK0_MMDSELECT_DEVCL22_EN_MASK                         0x0001
#define XGXSBLK0_MMDSELECT_DEVCL22_EN_ALIGN                        0
#define XGXSBLK0_MMDSELECT_DEVCL22_EN_BITS                         1
#define XGXSBLK0_MMDSELECT_DEVCL22_EN_SHIFT                        0


/****************************************************************************
 * XgxsBlk0 :: miscControl1
 ***************************************************************************/
/* XgxsBlk0 :: miscControl1 :: PMD_Lane3_tx_disable [15:15] */
#define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_MASK            0x8000
#define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_ALIGN           0
#define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_BITS            1
#define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_SHIFT           15

/* XgxsBlk0 :: miscControl1 :: PMD_Lane2_tx_disable [14:14] */
#define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_MASK            0x4000
#define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_ALIGN           0
#define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_BITS            1
#define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_SHIFT           14

/* XgxsBlk0 :: miscControl1 :: PMD_Lane1_tx_disable [13:13] */
#define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_MASK            0x2000
#define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_ALIGN           0
#define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_BITS            1
#define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_SHIFT           13

/* XgxsBlk0 :: miscControl1 :: PMD_Lane0_tx_disable [12:12] */
#define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_MASK            0x1000
#define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_ALIGN           0
#define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_BITS            1
#define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_SHIFT           12

/* XgxsBlk0 :: miscControl1 :: Global_PMD_tx_disable [11:11] */
#define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_MASK           0x0800
#define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_ALIGN          0
#define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_BITS           1
#define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_SHIFT          11

/* XgxsBlk0 :: miscControl1 :: PCS_dev_en_override_mask [10:10] */
#define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_MASK        0x0400
#define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_ALIGN       0
#define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_BITS        1
#define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_SHIFT       10

/* XgxsBlk0 :: miscControl1 :: PMD_dev_en_override_mask [09:09] */
#define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_MASK        0x0200
#define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_ALIGN       0
#define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_BITS        1
#define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_SHIFT       9

/* XgxsBlk0 :: miscControl1 :: reserved0 [08:08] */
#define XGXSBLK0_MISCCONTROL1_RESERVED0_MASK                       0x0100
#define XGXSBLK0_MISCCONTROL1_RESERVED0_ALIGN                      0
#define XGXSBLK0_MISCCONTROL1_RESERVED0_BITS                       1
#define XGXSBLK0_MISCCONTROL1_RESERVED0_SHIFT                      8

/* XgxsBlk0 :: miscControl1 :: clear_linkdown [07:07] */
#define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_MASK                  0x0080
#define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_ALIGN                 0
#define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_BITS                  1
#define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_SHIFT                 7

/* XgxsBlk0 :: miscControl1 :: latch_linkdown_enable [06:06] */
#define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_MASK           0x0040
#define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_ALIGN          0
#define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_BITS           1
#define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_SHIFT          6

/* XgxsBlk0 :: miscControl1 :: reserved1 [05:05] */
#define XGXSBLK0_MISCCONTROL1_RESERVED1_MASK                       0x0020
#define XGXSBLK0_MISCCONTROL1_RESERVED1_ALIGN                      0
#define XGXSBLK0_MISCCONTROL1_RESERVED1_BITS                       1
#define XGXSBLK0_MISCCONTROL1_RESERVED1_SHIFT                      5

/* XgxsBlk0 :: miscControl1 :: force_div5_for_lxck25 [04:04] */
#define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_MASK           0x0010
#define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_ALIGN          0
#define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_BITS           1
#define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_SHIFT          4

/* XgxsBlk0 :: miscControl1 :: pardet10g_pwrdnLink_en [03:03] */
#define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_MASK          0x0008
#define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_ALIGN         0
#define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_BITS          1
#define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_SHIFT         3

/* XgxsBlk0 :: miscControl1 :: invert_rx_sigdet [02:02] */
#define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_MASK                0x0004
#define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_ALIGN               0
#define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_BITS                1
#define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_SHIFT               2

/* XgxsBlk0 :: miscControl1 :: ieee_blksel_autodet [01:01] */
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_MASK             0x0002
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_ALIGN            0
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_BITS             1
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_SHIFT            1

/* XgxsBlk0 :: miscControl1 :: ieee_blksel_val [00:00] */
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_MASK                 0x0001
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_ALIGN                0
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_BITS                 1
#define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_SHIFT                0


/****************************************************************************
 * XgxsBlk0 :: BlockAddress
 ***************************************************************************/
/* XgxsBlk0 :: BlockAddress :: reserved0 [15:15] */
#define XGXSBLK0_BLOCKADDRESS_RESERVED0_MASK                       0x8000
#define XGXSBLK0_BLOCKADDRESS_RESERVED0_ALIGN                      0
#define XGXSBLK0_BLOCKADDRESS_RESERVED0_BITS                       1
#define XGXSBLK0_BLOCKADDRESS_RESERVED0_SHIFT                      15

/* XgxsBlk0 :: BlockAddress :: BlockAddress [14:04] */
#define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_MASK                    0x7ff0
#define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_ALIGN                   0
#define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_BITS                    11
#define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_SHIFT                   4

/* XgxsBlk0 :: BlockAddress :: reserved1 [03:00] */
#define XGXSBLK0_BLOCKADDRESS_RESERVED1_MASK                       0x000f
#define XGXSBLK0_BLOCKADDRESS_RESERVED1_ALIGN                      0
#define XGXSBLK0_BLOCKADDRESS_RESERVED1_BITS                       4
#define XGXSBLK0_BLOCKADDRESS_RESERVED1_SHIFT                      0


/****************************************************************************
 * Hypercore_USER_XgxsBlk1
 ***************************************************************************/
/****************************************************************************
 * XgxsBlk1 :: deskew
 ***************************************************************************/
/* XgxsBlk1 :: deskew :: link_en [15:15] */
#define XGXSBLK1_DESKEW_LINK_EN_MASK                               0x8000
#define XGXSBLK1_DESKEW_LINK_EN_ALIGN                              0
#define XGXSBLK1_DESKEW_LINK_EN_BITS                               1
#define XGXSBLK1_DESKEW_LINK_EN_SHIFT                              15

/* XgxsBlk1 :: deskew :: deskew_hyst_en [14:14] */
#define XGXSBLK1_DESKEW_DESKEW_HYST_EN_MASK                        0x4000
#define XGXSBLK1_DESKEW_DESKEW_HYST_EN_ALIGN                       0
#define XGXSBLK1_DESKEW_DESKEW_HYST_EN_BITS                        1
#define XGXSBLK1_DESKEW_DESKEW_HYST_EN_SHIFT                       14

/* XgxsBlk1 :: deskew :: dswin [13:09] */
#define XGXSBLK1_DESKEW_DSWIN_MASK                                 0x3e00
#define XGXSBLK1_DESKEW_DSWIN_ALIGN                                0
#define XGXSBLK1_DESKEW_DSWIN_BITS                                 5
#define XGXSBLK1_DESKEW_DSWIN_SHIFT                                9

/* XgxsBlk1 :: deskew :: mpwin [08:00] */
#define XGXSBLK1_DESKEW_MPWIN_MASK                                 0x01ff
#define XGXSBLK1_DESKEW_MPWIN_ALIGN                                0
#define XGXSBLK1_DESKEW_MPWIN_BITS                                 9
#define XGXSBLK1_DESKEW_MPWIN_SHIFT                                0


/****************************************************************************
 * XgxsBlk1 :: link
 ***************************************************************************/
/* XgxsBlk1 :: link :: Acolwin [15:00] */
#define XGXSBLK1_LINK_ACOLWIN_MASK                                 0xffff
#define XGXSBLK1_LINK_ACOLWIN_ALIGN                                0
#define XGXSBLK1_LINK_ACOLWIN_BITS                                 16
#define XGXSBLK1_LINK_ACOLWIN_SHIFT                                0


/****************************************************************************
 * XgxsBlk1 :: testRx
 ***************************************************************************/
/* XgxsBlk1 :: testRx :: reserved0 [15:08] */
#define XGXSBLK1_TESTRX_RESERVED0_MASK                             0xff00
#define XGXSBLK1_TESTRX_RESERVED0_ALIGN                            0
#define XGXSBLK1_TESTRX_RESERVED0_BITS                             8
#define XGXSBLK1_TESTRX_RESERVED0_SHIFT                            8

/* XgxsBlk1 :: testRx :: rx_inBandMdio_Qfltr_en [07:07] */
#define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_MASK                0x0080
#define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_ALIGN               0
#define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_BITS                1
#define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_SHIFT               7

/* XgxsBlk1 :: testRx :: link_force [06:06] */
#define XGXSBLK1_TESTRX_LINK_FORCE_MASK                            0x0040
#define XGXSBLK1_TESTRX_LINK_FORCE_ALIGN                           0
#define XGXSBLK1_TESTRX_LINK_FORCE_BITS                            1
#define XGXSBLK1_TESTRX_LINK_FORCE_SHIFT                           6

/* XgxsBlk1 :: testRx :: rxtm_modsel [05:03] */
#define XGXSBLK1_TESTRX_RXTM_MODSEL_MASK                           0x0038
#define XGXSBLK1_TESTRX_RXTM_MODSEL_ALIGN                          0
#define XGXSBLK1_TESTRX_RXTM_MODSEL_BITS                           3
#define XGXSBLK1_TESTRX_RXTM_MODSEL_SHIFT                          3

/* XgxsBlk1 :: testRx :: rxtm_tstsel [02:00] */
#define XGXSBLK1_TESTRX_RXTM_TSTSEL_MASK                           0x0007
#define XGXSBLK1_TESTRX_RXTM_TSTSEL_ALIGN                          0
#define XGXSBLK1_TESTRX_RXTM_TSTSEL_BITS                           3
#define XGXSBLK1_TESTRX_RXTM_TSTSEL_SHIFT                          0


/****************************************************************************
 * XgxsBlk1 :: testTx
 ***************************************************************************/
/* XgxsBlk1 :: testTx :: reserved0 [15:08] */
#define XGXSBLK1_TESTTX_RESERVED0_MASK                             0xff00
#define XGXSBLK1_TESTTX_RESERVED0_ALIGN                            0
#define XGXSBLK1_TESTTX_RESERVED0_BITS                             8
#define XGXSBLK1_TESTTX_RESERVED0_SHIFT                            8

/* XgxsBlk1 :: testTx :: rx_ck4x1muxsel [07:06] */
#define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_MASK                        0x00c0
#define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_ALIGN                       0
#define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_BITS                        2
#define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_SHIFT                       6

/* XgxsBlk1 :: testTx :: txtm_modsel [05:03] */
#define XGXSBLK1_TESTTX_TXTM_MODSEL_MASK                           0x0038
#define XGXSBLK1_TESTTX_TXTM_MODSEL_ALIGN                          0
#define XGXSBLK1_TESTTX_TXTM_MODSEL_BITS                           3
#define XGXSBLK1_TESTTX_TXTM_MODSEL_SHIFT                          3

/* XgxsBlk1 :: testTx :: txtm_tstsel [02:00] */
#define XGXSBLK1_TESTTX_TXTM_TSTSEL_MASK                           0x0007
#define XGXSBLK1_TESTTX_TXTM_TSTSEL_ALIGN                          0
#define XGXSBLK1_TESTTX_TXTM_TSTSEL_BITS                           3
#define XGXSBLK1_TESTTX_TXTM_TSTSEL_SHIFT                          0


/****************************************************************************
 * XgxsBlk1 :: testXg
 ***************************************************************************/
/* XgxsBlk1 :: testXg :: evnt_cntr_sel [15:15] */
#define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_MASK                         0x8000
#define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_ALIGN                        0
#define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_BITS                         1
#define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_SHIFT                        15

/* XgxsBlk1 :: testXg :: txdt_sel [14:14] */
#define XGXSBLK1_TESTXG_TXDT_SEL_MASK                              0x4000
#define XGXSBLK1_TESTXG_TXDT_SEL_ALIGN                             0
#define XGXSBLK1_TESTXG_TXDT_SEL_BITS                              1
#define XGXSBLK1_TESTXG_TXDT_SEL_SHIFT                             14

/* XgxsBlk1 :: testXg :: slice_sel [13:12] */
#define XGXSBLK1_TESTXG_SLICE_SEL_MASK                             0x3000
#define XGXSBLK1_TESTXG_SLICE_SEL_ALIGN                            0
#define XGXSBLK1_TESTXG_SLICE_SEL_BITS                             2
#define XGXSBLK1_TESTXG_SLICE_SEL_SHIFT                            12

/* XgxsBlk1 :: testXg :: reserved0 [11:08] */
#define XGXSBLK1_TESTXG_RESERVED0_MASK                             0x0f00
#define XGXSBLK1_TESTXG_RESERVED0_ALIGN                            0
#define XGXSBLK1_TESTXG_RESERVED0_BITS                             4
#define XGXSBLK1_TESTXG_RESERVED0_SHIFT                            8

/* XgxsBlk1 :: testXg :: test_reg_sel [07:07] */
#define XGXSBLK1_TESTXG_TEST_REG_SEL_MASK                          0x0080
#define XGXSBLK1_TESTXG_TEST_REG_SEL_ALIGN                         0
#define XGXSBLK1_TESTXG_TEST_REG_SEL_BITS                          1
#define XGXSBLK1_TESTXG_TEST_REG_SEL_SHIFT                         7

/* XgxsBlk1 :: testXg :: xg_txtstsel [06:04] */
#define XGXSBLK1_TESTXG_XG_TXTSTSEL_MASK                           0x0070
#define XGXSBLK1_TESTXG_XG_TXTSTSEL_ALIGN                          0
#define XGXSBLK1_TESTXG_XG_TXTSTSEL_BITS                           3
#define XGXSBLK1_TESTXG_XG_TXTSTSEL_SHIFT                          4

/* XgxsBlk1 :: testXg :: xg_rxtstsel [03:00] */
#define XGXSBLK1_TESTXG_XG_RXTSTSEL_MASK                           0x000f
#define XGXSBLK1_TESTXG_XG_RXTSTSEL_ALIGN                          0
#define XGXSBLK1_TESTXG_XG_RXTSTSEL_BITS                           4
#define XGXSBLK1_TESTXG_XG_RXTSTSEL_SHIFT                          0


/****************************************************************************
 * XgxsBlk1 :: laneCtrl0
 ***************************************************************************/
/* XgxsBlk1 :: laneCtrl0 :: ed66en [15:12] */
#define XGXSBLK1_LANECTRL0_ED66EN_MASK                             0xf000
#define XGXSBLK1_LANECTRL0_ED66EN_ALIGN                            0
#define XGXSBLK1_LANECTRL0_ED66EN_BITS                             4
#define XGXSBLK1_LANECTRL0_ED66EN_SHIFT                            12

/* XgxsBlk1 :: laneCtrl0 :: reserved0 [11:08] */
#define XGXSBLK1_LANECTRL0_RESERVED0_MASK                          0x0f00
#define XGXSBLK1_LANECTRL0_RESERVED0_ALIGN                         0
#define XGXSBLK1_LANECTRL0_RESERVED0_BITS                          4
#define XGXSBLK1_LANECTRL0_RESERVED0_SHIFT                         8

/* XgxsBlk1 :: laneCtrl0 :: cl36_pcs_en_rx [07:04] */
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_MASK                     0x00f0
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_ALIGN                    0
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_BITS                     4
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_SHIFT                    4

/* XgxsBlk1 :: laneCtrl0 :: cl36_pcs_en_tx [03:00] */
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_MASK                     0x000f
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_ALIGN                    0
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_BITS                     4
#define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_SHIFT                    0


/****************************************************************************
 * XgxsBlk1 :: laneCtrl1
 ***************************************************************************/
/* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln3 [15:14] */
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_MASK                      0xc000
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_ALIGN                     0
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_BITS                      2
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_SHIFT                     14
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_SWSDR_div2                0
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_SWSDR_div1                1
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_DWSDR_div2                2
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_DWSDR_div1                3

/* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln2 [13:12] */
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_MASK                      0x3000
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_ALIGN                     0
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_BITS                      2
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_SHIFT                     12
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_SWSDR_div2                0
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_SWSDR_div1                1
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_DWSDR_div2                2
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_DWSDR_div1                3

/* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln1 [11:10] */
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_MASK                      0x0c00
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_ALIGN                     0
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_BITS                      2
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_SHIFT                     10
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_SWSDR_div2                0
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_SWSDR_div1                1
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_DWSDR_div2                2
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_DWSDR_div1                3

/* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln0 [09:08] */
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_MASK                      0x0300
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_ALIGN                     0
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_BITS                      2
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_SHIFT                     8
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_SWSDR_div2                0
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_SWSDR_div1                1
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_DWSDR_div2                2
#define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_DWSDR_div1                3

/* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln3 [07:06] */
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_MASK                      0x00c0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_ALIGN                     0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_BITS                      2
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_SHIFT                     6
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_SWSDR_div2                0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_SWSDR_div1                1
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_DWSDR_div2                2
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_DWSDR_div1                3

/* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln2 [05:04] */
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_MASK                      0x0030
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_ALIGN                     0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_BITS                      2
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_SHIFT                     4
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_SWSDR_div2                0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_SWSDR_div1                1
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_DWSDR_div2                2
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_DWSDR_div1                3

/* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln1 [03:02] */
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_MASK                      0x000c
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_ALIGN                     0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_BITS                      2
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_SHIFT                     2
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_SWSDR_div2                0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_SWSDR_div1                1
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_DWSDR_div2                2
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_DWSDR_div1                3

/* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln0 [01:00] */
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_MASK                      0x0003
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_ALIGN                     0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_BITS                      2
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_SHIFT                     0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_SWSDR_div2                0
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_SWSDR_div1                1
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_DWSDR_div2                2
#define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_DWSDR_div1                3


/****************************************************************************
 * XgxsBlk1 :: laneCtrl2
 ***************************************************************************/
/* XgxsBlk1 :: laneCtrl2 :: cdet_en1g [15:12] */
#define XGXSBLK1_LANECTRL2_CDET_EN1G_MASK                          0xf000
#define XGXSBLK1_LANECTRL2_CDET_EN1G_ALIGN                         0
#define XGXSBLK1_LANECTRL2_CDET_EN1G_BITS                          4
#define XGXSBLK1_LANECTRL2_CDET_EN1G_SHIFT                         12

/* XgxsBlk1 :: laneCtrl2 :: eden1g [11:08] */
#define XGXSBLK1_LANECTRL2_EDEN1G_MASK                             0x0f00
#define XGXSBLK1_LANECTRL2_EDEN1G_ALIGN                            0
#define XGXSBLK1_LANECTRL2_EDEN1G_BITS                             4
#define XGXSBLK1_LANECTRL2_EDEN1G_SHIFT                            8

/* XgxsBlk1 :: laneCtrl2 :: rloop1g [07:04] */
#define XGXSBLK1_LANECTRL2_RLOOP1G_MASK                            0x00f0
#define XGXSBLK1_LANECTRL2_RLOOP1G_ALIGN                           0
#define XGXSBLK1_LANECTRL2_RLOOP1G_BITS                            4
#define XGXSBLK1_LANECTRL2_RLOOP1G_SHIFT                           4

/* XgxsBlk1 :: laneCtrl2 :: gloop1g [03:00] */
#define XGXSBLK1_LANECTRL2_GLOOP1G_MASK                            0x000f
#define XGXSBLK1_LANECTRL2_GLOOP1G_ALIGN                           0
#define XGXSBLK1_LANECTRL2_GLOOP1G_BITS                            4
#define XGXSBLK1_LANECTRL2_GLOOP1G_SHIFT                           0


/****************************************************************************
 * XgxsBlk1 :: laneCtrl3
 ***************************************************************************/
/* XgxsBlk1 :: laneCtrl3 :: lock_ref [15:12] */
#define XGXSBLK1_LANECTRL3_LOCK_REF_MASK                           0xf000
#define XGXSBLK1_LANECTRL3_LOCK_REF_ALIGN                          0
#define XGXSBLK1_LANECTRL3_LOCK_REF_BITS                           4
#define XGXSBLK1_LANECTRL3_LOCK_REF_SHIFT                          12

/* XgxsBlk1 :: laneCtrl3 :: pwrdwn_force [11:11] */
#define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_MASK                       0x0800
#define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_ALIGN                      0
#define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_BITS                       1
#define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_SHIFT                      11

/* XgxsBlk1 :: laneCtrl3 :: lock_ref_en [10:10] */
#define XGXSBLK1_LANECTRL3_LOCK_REF_EN_MASK                        0x0400
#define XGXSBLK1_LANECTRL3_LOCK_REF_EN_ALIGN                       0
#define XGXSBLK1_LANECTRL3_LOCK_REF_EN_BITS                        1
#define XGXSBLK1_LANECTRL3_LOCK_REF_EN_SHIFT                       10

/* XgxsBlk1 :: laneCtrl3 :: pwrdwn10g_pll_dis [09:09] */
#define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_MASK                  0x0200
#define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_ALIGN                 0
#define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_BITS                  1
#define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_SHIFT                 9

/* XgxsBlk1 :: laneCtrl3 :: pwrdwn_pll [08:08] */
#define XGXSBLK1_LANECTRL3_PWRDWN_PLL_MASK                         0x0100
#define XGXSBLK1_LANECTRL3_PWRDWN_PLL_ALIGN                        0
#define XGXSBLK1_LANECTRL3_PWRDWN_PLL_BITS                         1
#define XGXSBLK1_LANECTRL3_PWRDWN_PLL_SHIFT                        8

/* XgxsBlk1 :: laneCtrl3 :: pwrdn_tx [07:04] */
#define XGXSBLK1_LANECTRL3_PWRDN_TX_MASK                           0x00f0
#define XGXSBLK1_LANECTRL3_PWRDN_TX_ALIGN                          0
#define XGXSBLK1_LANECTRL3_PWRDN_TX_BITS                           4
#define XGXSBLK1_LANECTRL3_PWRDN_TX_SHIFT                          4

/* XgxsBlk1 :: laneCtrl3 :: pwrdn_rx [03:00] */
#define XGXSBLK1_LANECTRL3_PWRDN_RX_MASK                           0x000f
#define XGXSBLK1_LANECTRL3_PWRDN_RX_ALIGN                          0
#define XGXSBLK1_LANECTRL3_PWRDN_RX_BITS                           4
#define XGXSBLK1_LANECTRL3_PWRDN_RX_SHIFT                          0


/****************************************************************************
 * XgxsBlk1 :: lanePrbs
 ***************************************************************************/
/* XgxsBlk1 :: lanePrbs :: prbs_en3 [15:15] */
#define XGXSBLK1_LANEPRBS_PRBS_EN3_MASK                            0x8000
#define XGXSBLK1_LANEPRBS_PRBS_EN3_ALIGN                           0
#define XGXSBLK1_LANEPRBS_PRBS_EN3_BITS                            1
#define XGXSBLK1_LANEPRBS_PRBS_EN3_SHIFT                           15

/* XgxsBlk1 :: lanePrbs :: prbs_inv3 [14:14] */
#define XGXSBLK1_LANEPRBS_PRBS_INV3_MASK                           0x4000
#define XGXSBLK1_LANEPRBS_PRBS_INV3_ALIGN                          0
#define XGXSBLK1_LANEPRBS_PRBS_INV3_BITS                           1
#define XGXSBLK1_LANEPRBS_PRBS_INV3_SHIFT                          14

/* XgxsBlk1 :: lanePrbs :: prbs_order3 [13:12] */
#define XGXSBLK1_LANEPRBS_PRBS_ORDER3_MASK                         0x3000
#define XGXSBLK1_LANEPRBS_PRBS_ORDER3_ALIGN                        0
#define XGXSBLK1_LANEPRBS_PRBS_ORDER3_BITS                         2
#define XGXSBLK1_LANEPRBS_PRBS_ORDER3_SHIFT                        12
#define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs7                        0
#define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs15                       1
#define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs23                       2
#define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs31                       3

/* XgxsBlk1 :: lanePrbs :: prbs_en2 [11:11] */
#define XGXSBLK1_LANEPRBS_PRBS_EN2_MASK                            0x0800
#define XGXSBLK1_LANEPRBS_PRBS_EN2_ALIGN                           0
#define XGXSBLK1_LANEPRBS_PRBS_EN2_BITS                            1
#define XGXSBLK1_LANEPRBS_PRBS_EN2_SHIFT                           11

/* XgxsBlk1 :: lanePrbs :: prbs_inv2 [10:10] */
#define XGXSBLK1_LANEPRBS_PRBS_INV2_MASK                           0x0400
#define XGXSBLK1_LANEPRBS_PRBS_INV2_ALIGN                          0
#define XGXSBLK1_LANEPRBS_PRBS_INV2_BITS                           1
#define XGXSBLK1_LANEPRBS_PRBS_INV2_SHIFT                          10

/* XgxsBlk1 :: lanePrbs :: prbs_order2 [09:08] */
#define XGXSBLK1_LANEPRBS_PRBS_ORDER2_MASK                         0x0300
#define XGXSBLK1_LANEPRBS_PRBS_ORDER2_ALIGN                        0
#define XGXSBLK1_LANEPRBS_PRBS_ORDER2_BITS                         2
#define XGXSBLK1_LANEPRBS_PRBS_ORDER2_SHIFT                        8
#define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs7                        0
#define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs15                       1
#define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs23                       2
#define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs31                       3

/* XgxsBlk1 :: lanePrbs :: prbs_en1 [07:07] */
#define XGXSBLK1_LANEPRBS_PRBS_EN1_MASK                            0x0080
#define XGXSBLK1_LANEPRBS_PRBS_EN1_ALIGN                           0
#define XGXSBLK1_LANEPRBS_PRBS_EN1_BITS                            1
#define XGXSBLK1_LANEPRBS_PRBS_EN1_SHIFT                           7

/* XgxsBlk1 :: lanePrbs :: prbs_inv1 [06:06] */
#define XGXSBLK1_LANEPRBS_PRBS_INV1_MASK                           0x0040
#define XGXSBLK1_LANEPRBS_PRBS_INV1_ALIGN                          0
#define XGXSBLK1_LANEPRBS_PRBS_INV1_BITS                           1
#define XGXSBLK1_LANEPRBS_PRBS_INV1_SHIFT                          6

/* XgxsBlk1 :: lanePrbs :: prbs_order1 [05:04] */
#define XGXSBLK1_LANEPRBS_PRBS_ORDER1_MASK                         0x0030
#define XGXSBLK1_LANEPRBS_PRBS_ORDER1_ALIGN                        0
#define XGXSBLK1_LANEPRBS_PRBS_ORDER1_BITS                         2
#define XGXSBLK1_LANEPRBS_PRBS_ORDER1_SHIFT                        4
#define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs7                        0
#define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs15                       1
#define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs23                       2
#define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs31                       3

/* XgxsBlk1 :: lanePrbs :: prbs_en0 [03:03] */
#define XGXSBLK1_LANEPRBS_PRBS_EN0_MASK                            0x0008
#define XGXSBLK1_LANEPRBS_PRBS_EN0_ALIGN                           0
#define XGXSBLK1_LANEPRBS_PRBS_EN0_BITS                            1
#define XGXSBLK1_LANEPRBS_PRBS_EN0_SHIFT                           3

/* XgxsBlk1 :: lanePrbs :: prbs_inv0 [02:02] */
#define XGXSBLK1_LANEPRBS_PRBS_INV0_MASK                           0x0004
#define XGXSBLK1_LANEPRBS_PRBS_INV0_ALIGN                          0
#define XGXSBLK1_LANEPRBS_PRBS_INV0_BITS                           1
#define XGXSBLK1_LANEPRBS_PRBS_INV0_SHIFT                          2

/* XgxsBlk1 :: lanePrbs :: prbs_order0 [01:00] */
#define XGXSBLK1_LANEPRBS_PRBS_ORDER0_MASK                         0x0003
#define XGXSBLK1_LANEPRBS_PRBS_ORDER0_ALIGN                        0
#define XGXSBLK1_LANEPRBS_PRBS_ORDER0_BITS                         2
#define XGXSBLK1_LANEPRBS_PRBS_ORDER0_SHIFT                        0
#define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs7                        0
#define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs15                       1
#define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs23                       2
#define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs31                       3


/****************************************************************************
 * XgxsBlk1 :: laneTest
 ***************************************************************************/
/* XgxsBlk1 :: laneTest :: tmux_sel [15:12] */
#define XGXSBLK1_LANETEST_TMUX_SEL_MASK                            0xf000
#define XGXSBLK1_LANETEST_TMUX_SEL_ALIGN                           0
#define XGXSBLK1_LANETEST_TMUX_SEL_BITS                            4
#define XGXSBLK1_LANETEST_TMUX_SEL_SHIFT                           12
#define XGXSBLK1_LANETEST_TMUX_SEL_off                             0
#define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln0                          1
#define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln1                          2
#define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln2                          3
#define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln3                          4
#define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln0                          5
#define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln1                          6
#define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln2                          7
#define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln3                          8
#define XGXSBLK1_LANETEST_TMUX_SEL_pll                             11
#define XGXSBLK1_LANETEST_TMUX_SEL_mdio                            12
#define XGXSBLK1_LANETEST_TMUX_SEL_tMux1G                          15

/* XgxsBlk1 :: laneTest :: inBandMdioRxRstEn [11:11] */
#define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_MASK                   0x0800
#define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_ALIGN                  0
#define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_BITS                   1
#define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_SHIFT                  11

/* XgxsBlk1 :: laneTest :: pwrdn_ext_dis [10:10] */
#define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_MASK                       0x0400
#define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_ALIGN                      0
#define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_BITS                       1
#define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_SHIFT                      10

/* XgxsBlk1 :: laneTest :: pwrdn_safe_dis [09:09] */
#define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_MASK                      0x0200
#define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_ALIGN                     0
#define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_BITS                      1
#define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_SHIFT                     9

/* XgxsBlk1 :: laneTest :: pwrdwn_clks_en [08:08] */
#define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_MASK                      0x0100
#define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_ALIGN                     0
#define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_BITS                      1
#define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_SHIFT                     8

/* XgxsBlk1 :: laneTest :: rxSeqStart_ext_dis [07:07] */
#define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_MASK                  0x0080
#define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_ALIGN                 0
#define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_BITS                  1
#define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_SHIFT                 7

/* XgxsBlk1 :: laneTest :: pll_lock_rstb_r [06:06] */
#define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_MASK                     0x0040
#define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_ALIGN                    0
#define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_BITS                     1
#define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_SHIFT                    6

/* XgxsBlk1 :: laneTest :: lfck_bypass [05:05] */
#define XGXSBLK1_LANETEST_LFCK_BYPASS_MASK                         0x0020
#define XGXSBLK1_LANETEST_LFCK_BYPASS_ALIGN                        0
#define XGXSBLK1_LANETEST_LFCK_BYPASS_BITS                         1
#define XGXSBLK1_LANETEST_LFCK_BYPASS_SHIFT                        5

/* XgxsBlk1 :: laneTest :: rx_snoop_en [04:04] */
#define XGXSBLK1_LANETEST_RX_SNOOP_EN_MASK                         0x0010
#define XGXSBLK1_LANETEST_RX_SNOOP_EN_ALIGN                        0
#define XGXSBLK1_LANETEST_RX_SNOOP_EN_BITS                         1
#define XGXSBLK1_LANETEST_RX_SNOOP_EN_SHIFT                        4

/* XgxsBlk1 :: laneTest :: mode_10g_snoop [03:00] */
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_MASK                      0x000f
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_ALIGN                     0
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_BITS                      4
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_SHIFT                     0
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXS                      0
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXG_nCC                  1
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_IndLane_OS5               5
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_Indlanes                  6
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_PCI                       7
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXS_nLQ                  8
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXS_nLQnCC               9
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_PBypass                   10
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_PBypass_nDSK              11
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_ComboCoreMode             12
#define XGXSBLK1_LANETEST_MODE_10G_SNOOP_Clocks_off                15


/****************************************************************************
 * XgxsBlk1 :: lssRevnt
 ***************************************************************************/
/* union - case txActive [15:00] */
/* XgxsBlk1 :: lssRevnt :: txActive [15:00] */
#define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_MASK                   0xffff
#define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_ALIGN                  0
#define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_BITS                   16
#define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_SHIFT                  0


/* union - case lssRevent [15:00] */
/* XgxsBlk1 :: lssRevnt :: lss_Revent [15:00] */
#define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_MASK                0xffff
#define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_ALIGN               0
#define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_BITS                16
#define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_SHIFT               0



/****************************************************************************
 * XgxsBlk1 :: dskevnt
 ***************************************************************************/
/* union - case rxActive [15:00] */
/* XgxsBlk1 :: dskevnt :: rxActive [15:00] */
#define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_MASK                    0xffff
#define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_ALIGN                   0
#define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_BITS                    16
#define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_SHIFT                   0


/* union - case deskwevent [15:00] */
/* XgxsBlk1 :: dskevnt :: deskewEvent [15:00] */
#define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_MASK               0xffff
#define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_ALIGN              0
#define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_BITS               16
#define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_SHIFT              0



/****************************************************************************
 * XgxsBlk1 :: Aerrevnt
 ***************************************************************************/
/* XgxsBlk1 :: Aerrevnt :: Aerrevnt [15:00] */
#define XGXSBLK1_AERREVNT_AERREVNT_MASK                            0xffff
#define XGXSBLK1_AERREVNT_AERREVNT_ALIGN                           0
#define XGXSBLK1_AERREVNT_AERREVNT_BITS                            16
#define XGXSBLK1_AERREVNT_AERREVNT_SHIFT                           0


/****************************************************************************
 * XgxsBlk1 :: ckcmpevnt
 ***************************************************************************/
/* XgxsBlk1 :: ckcmpevnt :: ckcmpevnt [15:00] */
#define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_MASK                          0xffff
#define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_ALIGN                         0
#define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_BITS                          16
#define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_SHIFT                         0


/****************************************************************************
 * Hypercore_USER_TxBert
 ***************************************************************************/
/****************************************************************************
 * TxBert :: txBertCtrl
 ***************************************************************************/
/* TxBert :: txBertCtrl :: pkt_en [15:15] */
#define TXBERT_TXBERTCTRL_PKT_EN_MASK                              0x8000
#define TXBERT_TXBERTCTRL_PKT_EN_ALIGN                             0
#define TXBERT_TXBERTCTRL_PKT_EN_BITS                              1
#define TXBERT_TXBERTCTRL_PKT_EN_SHIFT                             15

/* TxBert :: txBertCtrl :: seed_ld [14:14] */
#define TXBERT_TXBERTCTRL_SEED_LD_MASK                             0x4000
#define TXBERT_TXBERTCTRL_SEED_LD_ALIGN                            0
#define TXBERT_TXBERTCTRL_SEED_LD_BITS                             1
#define TXBERT_TXBERTCTRL_SEED_LD_SHIFT                            14

/* TxBert :: txBertCtrl :: prbs_order [13:12] */
#define TXBERT_TXBERTCTRL_PRBS_ORDER_MASK                          0x3000
#define TXBERT_TXBERTCTRL_PRBS_ORDER_ALIGN                         0
#define TXBERT_TXBERTCTRL_PRBS_ORDER_BITS                          2
#define TXBERT_TXBERTCTRL_PRBS_ORDER_SHIFT                         12

/* TxBert :: txBertCtrl :: ramp_en [11:11] */
#define TXBERT_TXBERTCTRL_RAMP_EN_MASK                             0x0800
#define TXBERT_TXBERTCTRL_RAMP_EN_ALIGN                            0
#define TXBERT_TXBERTCTRL_RAMP_EN_BITS                             1
#define TXBERT_TXBERTCTRL_RAMP_EN_SHIFT                            11

/* TxBert :: txBertCtrl :: rndm_en [10:10] */
#define TXBERT_TXBERTCTRL_RNDM_EN_MASK                             0x0400
#define TXBERT_TXBERTCTRL_RNDM_EN_ALIGN                            0
#define TXBERT_TXBERTCTRL_RNDM_EN_BITS                             1
#define TXBERT_TXBERTCTRL_RNDM_EN_SHIFT                            10

/* TxBert :: txBertCtrl :: Q_en [09:09] */
#define TXBERT_TXBERTCTRL_Q_EN_MASK                                0x0200
#define TXBERT_TXBERTCTRL_Q_EN_ALIGN                               0
#define TXBERT_TXBERTCTRL_Q_EN_BITS                                1
#define TXBERT_TXBERTCTRL_Q_EN_SHIFT                               9

/* TxBert :: txBertCtrl :: Q_link_en [08:08] */
#define TXBERT_TXBERTCTRL_Q_LINK_EN_MASK                           0x0100
#define TXBERT_TXBERTCTRL_Q_LINK_EN_ALIGN                          0
#define TXBERT_TXBERTCTRL_Q_LINK_EN_BITS                           1
#define TXBERT_TXBERTCTRL_Q_LINK_EN_SHIFT                          8

/* TxBert :: txBertCtrl :: skew_en [07:07] */
#define TXBERT_TXBERTCTRL_SKEW_EN_MASK                             0x0080
#define TXBERT_TXBERTCTRL_SKEW_EN_ALIGN                            0
#define TXBERT_TXBERTCTRL_SKEW_EN_BITS                             1
#define TXBERT_TXBERTCTRL_SKEW_EN_SHIFT                            7

/* TxBert :: txBertCtrl :: cjpat_en [06:06] */
#define TXBERT_TXBERTCTRL_CJPAT_EN_MASK                            0x0040
#define TXBERT_TXBERTCTRL_CJPAT_EN_ALIGN                           0
#define TXBERT_TXBERTCTRL_CJPAT_EN_BITS                            1
#define TXBERT_TXBERTCTRL_CJPAT_EN_SHIFT                           6

/* TxBert :: txBertCtrl :: crpat_en [05:05] */
#define TXBERT_TXBERTCTRL_CRPAT_EN_MASK                            0x0020
#define TXBERT_TXBERTCTRL_CRPAT_EN_ALIGN                           0
#define TXBERT_TXBERTCTRL_CRPAT_EN_BITS                            1
#define TXBERT_TXBERTCTRL_CRPAT_EN_SHIFT                           5

/* TxBert :: txBertCtrl :: cjrmp_en [04:04] */
#define TXBERT_TXBERTCTRL_CJRMP_EN_MASK                            0x0010
#define TXBERT_TXBERTCTRL_CJRMP_EN_ALIGN                           0
#define TXBERT_TXBERTCTRL_CJRMP_EN_BITS                            1
#define TXBERT_TXBERTCTRL_CJRMP_EN_SHIFT                           4

/* TxBert :: txBertCtrl :: txck_out_force [03:03] */
#define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_MASK                      0x0008
#define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_ALIGN                     0
#define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_BITS                      1
#define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_SHIFT                     3

/* TxBert :: txBertCtrl :: fifo_rst [02:02] */
#define TXBERT_TXBERTCTRL_FIFO_RST_MASK                            0x0004
#define TXBERT_TXBERTCTRL_FIFO_RST_ALIGN                           0
#define TXBERT_TXBERTCTRL_FIFO_RST_BITS                            1
#define TXBERT_TXBERTCTRL_FIFO_RST_SHIFT                           2

/* TxBert :: txBertCtrl :: countRst_dis [01:01] */
#define TXBERT_TXBERTCTRL_COUNTRST_DIS_MASK                        0x0002
#define TXBERT_TXBERTCTRL_COUNTRST_DIS_ALIGN                       0
#define TXBERT_TXBERTCTRL_COUNTRST_DIS_BITS                        1
#define TXBERT_TXBERTCTRL_COUNTRST_DIS_SHIFT                       1

/* TxBert :: txBertCtrl :: count_clr [00:00] */
#define TXBERT_TXBERTCTRL_COUNT_CLR_MASK                           0x0001
#define TXBERT_TXBERTCTRL_COUNT_CLR_ALIGN                          0
#define TXBERT_TXBERTCTRL_COUNT_CLR_BITS                           1
#define TXBERT_TXBERTCTRL_COUNT_CLR_SHIFT                          0


/****************************************************************************
 * TxBert :: txBertSopEop
 ***************************************************************************/
/* TxBert :: txBertSopEop :: SOP [15:08] */
#define TXBERT_TXBERTSOPEOP_SOP_MASK                               0xff00
#define TXBERT_TXBERTSOPEOP_SOP_ALIGN                              0
#define TXBERT_TXBERTSOPEOP_SOP_BITS                               8
#define TXBERT_TXBERTSOPEOP_SOP_SHIFT                              8

/* TxBert :: txBertSopEop :: EOP [07:00] */
#define TXBERT_TXBERTSOPEOP_EOP_MASK                               0x00ff
#define TXBERT_TXBERTSOPEOP_EOP_ALIGN                              0
#define TXBERT_TXBERTSOPEOP_EOP_BITS                               8
#define TXBERT_TXBERTSOPEOP_EOP_SHIFT                              0


/****************************************************************************
 * TxBert :: txBertSize0
 ***************************************************************************/
/* TxBert :: txBertSize0 :: ipg_size [15:10] */
#define TXBERT_TXBERTSIZE0_IPG_SIZE_MASK                           0xfc00
#define TXBERT_TXBERTSIZE0_IPG_SIZE_ALIGN                          0
#define TXBERT_TXBERTSIZE0_IPG_SIZE_BITS                           6
#define TXBERT_TXBERTSIZE0_IPG_SIZE_SHIFT                          10

/* TxBert :: txBertSize0 :: pkt_size [09:00] */
#define TXBERT_TXBERTSIZE0_PKT_SIZE_MASK                           0x03ff
#define TXBERT_TXBERTSIZE0_PKT_SIZE_ALIGN                          0
#define TXBERT_TXBERTSIZE0_PKT_SIZE_BITS                           10
#define TXBERT_TXBERTSIZE0_PKT_SIZE_SHIFT                          0


/****************************************************************************
 * TxBert :: txBertSize1
 ***************************************************************************/
/* TxBert :: txBertSize1 :: awin_size [15:10] */
#define TXBERT_TXBERTSIZE1_AWIN_SIZE_MASK                          0xfc00
#define TXBERT_TXBERTSIZE1_AWIN_SIZE_ALIGN                         0
#define TXBERT_TXBERTSIZE1_AWIN_SIZE_BITS                          6
#define TXBERT_TXBERTSIZE1_AWIN_SIZE_SHIFT                         10

/* TxBert :: txBertSize1 :: PktStpCnt [09:00] */
#define TXBERT_TXBERTSIZE1_PKTSTPCNT_MASK                          0x03ff
#define TXBERT_TXBERTSIZE1_PKTSTPCNT_ALIGN                         0
#define TXBERT_TXBERTSIZE1_PKTSTPCNT_BITS                          10
#define TXBERT_TXBERTSIZE1_PKTSTPCNT_SHIFT                         0


/****************************************************************************
 * TxBert :: txBertSize2
 ***************************************************************************/
/* TxBert :: txBertSize2 :: skew3 [15:12] */
#define TXBERT_TXBERTSIZE2_SKEW3_MASK                              0xf000
#define TXBERT_TXBERTSIZE2_SKEW3_ALIGN                             0
#define TXBERT_TXBERTSIZE2_SKEW3_BITS                              4
#define TXBERT_TXBERTSIZE2_SKEW3_SHIFT                             12

/* TxBert :: txBertSize2 :: skew2 [11:08] */
#define TXBERT_TXBERTSIZE2_SKEW2_MASK                              0x0f00
#define TXBERT_TXBERTSIZE2_SKEW2_ALIGN                             0
#define TXBERT_TXBERTSIZE2_SKEW2_BITS                              4
#define TXBERT_TXBERTSIZE2_SKEW2_SHIFT                             8

/* TxBert :: txBertSize2 :: skew1 [07:04] */
#define TXBERT_TXBERTSIZE2_SKEW1_MASK                              0x00f0
#define TXBERT_TXBERTSIZE2_SKEW1_ALIGN                             0
#define TXBERT_TXBERTSIZE2_SKEW1_BITS                              4
#define TXBERT_TXBERTSIZE2_SKEW1_SHIFT                             4

/* TxBert :: txBertSize2 :: skew0 [03:00] */
#define TXBERT_TXBERTSIZE2_SKEW0_MASK                              0x000f
#define TXBERT_TXBERTSIZE2_SKEW0_ALIGN                             0
#define TXBERT_TXBERTSIZE2_SKEW0_BITS                              4
#define TXBERT_TXBERTSIZE2_SKEW0_SHIFT                             0


/****************************************************************************
 * TxBert :: txBertIpg0
 ***************************************************************************/
/* TxBert :: txBertIpg0 :: ipg1 [15:08] */
#define TXBERT_TXBERTIPG0_IPG1_MASK                                0xff00
#define TXBERT_TXBERTIPG0_IPG1_ALIGN                               0
#define TXBERT_TXBERTIPG0_IPG1_BITS                                8
#define TXBERT_TXBERTIPG0_IPG1_SHIFT                               8

/* TxBert :: txBertIpg0 :: ipg0 [07:00] */
#define TXBERT_TXBERTIPG0_IPG0_MASK                                0x00ff
#define TXBERT_TXBERTIPG0_IPG0_ALIGN                               0
#define TXBERT_TXBERTIPG0_IPG0_BITS                                8
#define TXBERT_TXBERTIPG0_IPG0_SHIFT                               0


/****************************************************************************
 * TxBert :: txBertIpg1
 ***************************************************************************/
/* TxBert :: txBertIpg1 :: ipg3 [15:08] */
#define TXBERT_TXBERTIPG1_IPG3_MASK                                0xff00
#define TXBERT_TXBERTIPG1_IPG3_ALIGN                               0
#define TXBERT_TXBERTIPG1_IPG3_BITS                                8
#define TXBERT_TXBERTIPG1_IPG3_SHIFT                               8

/* TxBert :: txBertIpg1 :: ipg2 [07:00] */
#define TXBERT_TXBERTIPG1_IPG2_MASK                                0x00ff
#define TXBERT_TXBERTIPG1_IPG2_ALIGN                               0
#define TXBERT_TXBERTIPG1_IPG2_BITS                                8
#define TXBERT_TXBERTIPG1_IPG2_SHIFT                               0


/****************************************************************************
 * TxBert :: txBertByteU
 ***************************************************************************/
/* TxBert :: txBertByteU :: byte_count_high [15:00] */
#define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_MASK                    0xffff
#define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_ALIGN                   0
#define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_BITS                    16
#define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_SHIFT                   0


/****************************************************************************
 * TxBert :: txBertByteL
 ***************************************************************************/
/* TxBert :: txBertByteL :: byte_count_low [15:00] */
#define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_MASK                     0xffff
#define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_ALIGN                    0
#define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_BITS                     16
#define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_SHIFT                    0


/****************************************************************************
 * TxBert :: txBertPacketU
 ***************************************************************************/
/* TxBert :: txBertPacketU :: pkt_count_high [15:00] */
#define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_MASK                   0xffff
#define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_ALIGN                  0
#define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_BITS                   16
#define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_SHIFT                  0


/****************************************************************************
 * TxBert :: txBertPacketL
 ***************************************************************************/
/* TxBert :: txBertPacketL :: pkt_count_low [15:00] */
#define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_MASK                    0xffff
#define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_ALIGN                   0
#define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_BITS                    16
#define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_SHIFT                   0


/****************************************************************************
 * Hypercore_USER_RxBert
 ***************************************************************************/
/****************************************************************************
 * RxBert :: rxBertCtrl
 ***************************************************************************/
/* RxBert :: rxBertCtrl :: pkt_en [15:15] */
#define RXBERT_RXBERTCTRL_PKT_EN_MASK                              0x8000
#define RXBERT_RXBERTCTRL_PKT_EN_ALIGN                             0
#define RXBERT_RXBERTCTRL_PKT_EN_BITS                              1
#define RXBERT_RXBERTCTRL_PKT_EN_SHIFT                             15

/* RxBert :: rxBertCtrl :: seed_ld [14:14] */
#define RXBERT_RXBERTCTRL_SEED_LD_MASK                             0x4000
#define RXBERT_RXBERTCTRL_SEED_LD_ALIGN                            0
#define RXBERT_RXBERTCTRL_SEED_LD_BITS                             1
#define RXBERT_RXBERTCTRL_SEED_LD_SHIFT                            14

/* RxBert :: rxBertCtrl :: prbs_order [13:12] */
#define RXBERT_RXBERTCTRL_PRBS_ORDER_MASK                          0x3000
#define RXBERT_RXBERTCTRL_PRBS_ORDER_ALIGN                         0
#define RXBERT_RXBERTCTRL_PRBS_ORDER_BITS                          2
#define RXBERT_RXBERTCTRL_PRBS_ORDER_SHIFT                         12

/* RxBert :: rxBertCtrl :: ramp_en [11:11] */
#define RXBERT_RXBERTCTRL_RAMP_EN_MASK                             0x0800
#define RXBERT_RXBERTCTRL_RAMP_EN_ALIGN                            0
#define RXBERT_RXBERTCTRL_RAMP_EN_BITS                             1
#define RXBERT_RXBERTCTRL_RAMP_EN_SHIFT                            11

/* RxBert :: rxBertCtrl :: cgbad_tst_en [10:10] */
#define RXBERT_RXBERTCTRL_CGBAD_TST_EN_MASK                        0x0400
#define RXBERT_RXBERTCTRL_CGBAD_TST_EN_ALIGN                       0
#define RXBERT_RXBERTCTRL_CGBAD_TST_EN_BITS                        1
#define RXBERT_RXBERTCTRL_CGBAD_TST_EN_SHIFT                       10

/* RxBert :: rxBertCtrl :: crcChk_en [09:09] */
#define RXBERT_RXBERTCTRL_CRCCHK_EN_MASK                           0x0200
#define RXBERT_RXBERTCTRL_CRCCHK_EN_ALIGN                          0
#define RXBERT_RXBERTCTRL_CRCCHK_EN_BITS                           1
#define RXBERT_RXBERTCTRL_CRCCHK_EN_SHIFT                          9

/* RxBert :: rxBertCtrl :: countRst_dis [08:08] */
#define RXBERT_RXBERTCTRL_COUNTRST_DIS_MASK                        0x0100
#define RXBERT_RXBERTCTRL_COUNTRST_DIS_ALIGN                       0
#define RXBERT_RXBERTCTRL_COUNTRST_DIS_BITS                        1
#define RXBERT_RXBERTCTRL_COUNTRST_DIS_SHIFT                       8

/* RxBert :: rxBertCtrl :: rxStatSel [07:07] */
#define RXBERT_RXBERTCTRL_RXSTATSEL_MASK                           0x0080
#define RXBERT_RXBERTCTRL_RXSTATSEL_ALIGN                          0
#define RXBERT_RXBERTCTRL_RXSTATSEL_BITS                           1
#define RXBERT_RXBERTCTRL_RXSTATSEL_SHIFT                          7

/* RxBert :: rxBertCtrl :: source_sel_r [06:06] */
#define RXBERT_RXBERTCTRL_SOURCE_SEL_R_MASK                        0x0040
#define RXBERT_RXBERTCTRL_SOURCE_SEL_R_ALIGN                       0
#define RXBERT_RXBERTCTRL_SOURCE_SEL_R_BITS                        1
#define RXBERT_RXBERTCTRL_SOURCE_SEL_R_SHIFT                       6

/* RxBert :: rxBertCtrl :: source_sel [05:04] */
#define RXBERT_RXBERTCTRL_SOURCE_SEL_MASK                          0x0030
#define RXBERT_RXBERTCTRL_SOURCE_SEL_ALIGN                         0
#define RXBERT_RXBERTCTRL_SOURCE_SEL_BITS                          2
#define RXBERT_RXBERTCTRL_SOURCE_SEL_SHIFT                         4

/* RxBert :: rxBertCtrl :: slice_sel [03:02] */
#define RXBERT_RXBERTCTRL_SLICE_SEL_MASK                           0x000c
#define RXBERT_RXBERTCTRL_SLICE_SEL_ALIGN                          0
#define RXBERT_RXBERTCTRL_SLICE_SEL_BITS                           2
#define RXBERT_RXBERTCTRL_SLICE_SEL_SHIFT                          2

/* RxBert :: rxBertCtrl :: err_clr [01:01] */
#define RXBERT_RXBERTCTRL_ERR_CLR_MASK                             0x0002
#define RXBERT_RXBERTCTRL_ERR_CLR_ALIGN                            0
#define RXBERT_RXBERTCTRL_ERR_CLR_BITS                             1
#define RXBERT_RXBERTCTRL_ERR_CLR_SHIFT                            1

/* RxBert :: rxBertCtrl :: count_clr [00:00] */
#define RXBERT_RXBERTCTRL_COUNT_CLR_MASK                           0x0001
#define RXBERT_RXBERTCTRL_COUNT_CLR_ALIGN                          0
#define RXBERT_RXBERTCTRL_COUNT_CLR_BITS                           1
#define RXBERT_RXBERTCTRL_COUNT_CLR_SHIFT                          0


/****************************************************************************
 * RxBert :: rxBertSopEop
 ***************************************************************************/
/* RxBert :: rxBertSopEop :: SOP [15:08] */
#define RXBERT_RXBERTSOPEOP_SOP_MASK                               0xff00
#define RXBERT_RXBERTSOPEOP_SOP_ALIGN                              0
#define RXBERT_RXBERTSOPEOP_SOP_BITS                               8
#define RXBERT_RXBERTSOPEOP_SOP_SHIFT                              8

/* RxBert :: rxBertSopEop :: EOP [07:00] */
#define RXBERT_RXBERTSOPEOP_EOP_MASK                               0x00ff
#define RXBERT_RXBERTSOPEOP_EOP_ALIGN                              0
#define RXBERT_RXBERTSOPEOP_EOP_BITS                               8
#define RXBERT_RXBERTSOPEOP_EOP_SHIFT                              0


/****************************************************************************
 * RxBert :: rxBertByteU
 ***************************************************************************/
/* RxBert :: rxBertByteU :: byte_count_high [15:00] */
#define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_MASK                    0xffff
#define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_ALIGN                   0
#define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_BITS                    16
#define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_SHIFT                   0


/****************************************************************************
 * RxBert :: rxBertByteL
 ***************************************************************************/
/* RxBert :: rxBertByteL :: byte_count_low [15:00] */
#define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_MASK                     0xffff
#define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_ALIGN                    0
#define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_BITS                     16
#define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_SHIFT                    0


/****************************************************************************
 * RxBert :: rxBertPacketU
 ***************************************************************************/
/* RxBert :: rxBertPacketU :: pkt_count_high [15:00] */
#define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_MASK                   0xffff
#define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_ALIGN                  0
#define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_BITS                   16
#define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_SHIFT                  0


/****************************************************************************
 * RxBert :: rxBertPacketL
 ***************************************************************************/
/* RxBert :: rxBertPacketL :: pkt_count_low [15:00] */
#define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_MASK                    0xffff
#define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_ALIGN                   0
#define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_BITS                    16
#define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_SHIFT                   0


/****************************************************************************
 * RxBert :: rxBertBitErr
 ***************************************************************************/
/* RxBert :: rxBertBitErr :: bit_err_count [15:00] */
#define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_MASK                     0xffff
#define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_ALIGN                    0
#define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_BITS                     16
#define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_SHIFT                    0


/****************************************************************************
 * RxBert :: rxBertByteErr
 ***************************************************************************/
/* RxBert :: rxBertByteErr :: byte_err_count [15:00] */
#define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_MASK                   0xffff
#define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_ALIGN                  0
#define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_BITS                   16
#define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_SHIFT                  0


/****************************************************************************
 * RxBert :: rxBertPktErr
 ***************************************************************************/
/* RxBert :: rxBertPktErr :: pkt_err_count [15:00] */
#define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_MASK                     0xffff
#define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_ALIGN                    0
#define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_BITS                     16
#define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_SHIFT                    0


/****************************************************************************
 * RxBert :: rxBertStatus
 ***************************************************************************/
/* union - case rxStatSel [15:00] */
/* RxBert :: rxBertStatus :: reserved0 [15:08] */
#define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_MASK               0xff00
#define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_ALIGN              0
#define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_BITS               8
#define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_SHIFT              8

/* RxBert :: rxBertStatus :: rx_10g_tmux [07:00] */
#define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_MASK             0x00ff
#define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_ALIGN            0
#define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_BITS             8
#define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_SHIFT            0


/* union - case crcChk_en [15:00] */
/* RxBert :: rxBertStatus :: link [15:15] */
#define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_MASK                    0x8000
#define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_ALIGN                   0
#define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_BITS                    1
#define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_SHIFT                   15

/* RxBert :: rxBertStatus :: prbs_stky [14:14] */
#define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_MASK               0x4000
#define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_ALIGN              0
#define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_BITS               1
#define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_SHIFT              14

/* RxBert :: rxBertStatus :: reserved0 [13:00] */
#define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_MASK               0x3fff
#define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_ALIGN              0
#define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_BITS               14
#define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_SHIFT              0


/* union - case rxBert [15:00] */
/* RxBert :: rxBertStatus :: prbs_lock [15:15] */
#define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_MASK                  0x8000
#define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_ALIGN                 0
#define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_BITS                  1
#define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_SHIFT                 15

/* RxBert :: rxBertStatus :: prbs_stky [14:14] */
#define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_MASK                  0x4000
#define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_ALIGN                 0
#define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_BITS                  1
#define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_SHIFT                 14

/* RxBert :: rxBertStatus :: prbs_state [13:11] */
#define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_MASK                 0x3800
#define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_ALIGN                0
#define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_BITS                 3
#define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_SHIFT                11

/* RxBert :: rxBertStatus :: reserved0 [10:07] */
#define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_MASK                  0x0780
#define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_ALIGN                 0
#define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_BITS                  4
#define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_SHIFT                 7

/* RxBert :: rxBertStatus :: bit_err_overflow [06:06] */
#define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_MASK           0x0040
#define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_ALIGN          0
#define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_BITS           1
#define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_SHIFT          6

/* RxBert :: rxBertStatus :: reserved1 [05:04] */
#define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_MASK                  0x0030
#define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_ALIGN                 0
#define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_BITS                  2
#define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_SHIFT                 4

/* RxBert :: rxBertStatus :: onefe_det [03:03] */
#define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_MASK                  0x0008
#define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_ALIGN                 0
#define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_BITS                  1
#define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_SHIFT                 3

/* RxBert :: rxBertStatus :: xor_comp [02:00] */
#define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_MASK                   0x0007
#define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_ALIGN                  0
#define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_BITS                   3
#define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_SHIFT                  0



/****************************************************************************
 * Hypercore_USER_TxPll
 ***************************************************************************/
/****************************************************************************
 * TxPll :: anaPllStatus
 ***************************************************************************/
/* TxPll :: anaPllStatus :: pllSeqDone [15:15] */
#define TXPLL_ANAPLLSTATUS_PLLSEQDONE_MASK                         0x8000
#define TXPLL_ANAPLLSTATUS_PLLSEQDONE_ALIGN                        0
#define TXPLL_ANAPLLSTATUS_PLLSEQDONE_BITS                         1
#define TXPLL_ANAPLLSTATUS_PLLSEQDONE_SHIFT                        15

/* TxPll :: anaPllStatus :: freqDone [14:14] */
#define TXPLL_ANAPLLSTATUS_FREQDONE_MASK                           0x4000
#define TXPLL_ANAPLLSTATUS_FREQDONE_ALIGN                          0
#define TXPLL_ANAPLLSTATUS_FREQDONE_BITS                           1
#define TXPLL_ANAPLLSTATUS_FREQDONE_SHIFT                          14

/* TxPll :: anaPllStatus :: vcoDone [13:13] */
#define TXPLL_ANAPLLSTATUS_VCODONE_MASK                            0x2000
#define TXPLL_ANAPLLSTATUS_VCODONE_ALIGN                           0
#define TXPLL_ANAPLLSTATUS_VCODONE_BITS                            1
#define TXPLL_ANAPLLSTATUS_VCODONE_SHIFT                           13

/* TxPll :: anaPllStatus :: reserved0 [12:12] */
#define TXPLL_ANAPLLSTATUS_RESERVED0_MASK                          0x1000
#define TXPLL_ANAPLLSTATUS_RESERVED0_ALIGN                         0
#define TXPLL_ANAPLLSTATUS_RESERVED0_BITS                          1
#define TXPLL_ANAPLLSTATUS_RESERVED0_SHIFT                         12

/* TxPll :: anaPllStatus :: pllSeqPass [11:11] */
#define TXPLL_ANAPLLSTATUS_PLLSEQPASS_MASK                         0x0800
#define TXPLL_ANAPLLSTATUS_PLLSEQPASS_ALIGN                        0
#define TXPLL_ANAPLLSTATUS_PLLSEQPASS_BITS                         1
#define TXPLL_ANAPLLSTATUS_PLLSEQPASS_SHIFT                        11

/* TxPll :: anaPllStatus :: freqPass [10:10] */
#define TXPLL_ANAPLLSTATUS_FREQPASS_MASK                           0x0400
#define TXPLL_ANAPLLSTATUS_FREQPASS_ALIGN                          0
#define TXPLL_ANAPLLSTATUS_FREQPASS_BITS                           1
#define TXPLL_ANAPLLSTATUS_FREQPASS_SHIFT                          10

/* TxPll :: anaPllStatus :: vcoPass [09:09] */
#define TXPLL_ANAPLLSTATUS_VCOPASS_MASK                            0x0200
#define TXPLL_ANAPLLSTATUS_VCOPASS_ALIGN                           0
#define TXPLL_ANAPLLSTATUS_VCOPASS_BITS                            1
#define TXPLL_ANAPLLSTATUS_VCOPASS_SHIFT                           9

/* TxPll :: anaPllStatus :: reserved1 [08:08] */
#define TXPLL_ANAPLLSTATUS_RESERVED1_MASK                          0x0100
#define TXPLL_ANAPLLSTATUS_RESERVED1_ALIGN                         0
#define TXPLL_ANAPLLSTATUS_RESERVED1_BITS                          1
#define TXPLL_ANAPLLSTATUS_RESERVED1_SHIFT                         8

/* TxPll :: anaPllStatus :: slowdn [07:07] */
#define TXPLL_ANAPLLSTATUS_SLOWDN_MASK                             0x0080
#define TXPLL_ANAPLLSTATUS_SLOWDN_ALIGN                            0
#define TXPLL_ANAPLLSTATUS_SLOWDN_BITS                             1
#define TXPLL_ANAPLLSTATUS_SLOWDN_SHIFT                            7

/* TxPll :: anaPllStatus :: lostPllLock_SM [06:06] */
#define TXPLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_MASK                     0x0040
#define TXPLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_ALIGN                    0
#define TXPLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_BITS                     1
#define TXPLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_SHIFT                    6

/* TxPll :: anaPllStatus :: reserved2 [05:04] */
#define TXPLL_ANAPLLSTATUS_RESERVED2_MASK                          0x0030
#define TXPLL_ANAPLLSTATUS_RESERVED2_ALIGN                         0
#define TXPLL_ANAPLLSTATUS_RESERVED2_BITS                          2
#define TXPLL_ANAPLLSTATUS_RESERVED2_SHIFT                         4

/* TxPll :: anaPllStatus :: pll_mode_afe [03:00] */
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_MASK                       0x000f
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_ALIGN                      0
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_BITS                       4
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_SHIFT                      0
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div16                      0
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div20                      1
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div24                      2
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div26                      3
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div30                      4
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div32                      5
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div36                      6
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div40                      7
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div42                      8
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div48                      9
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div50                      10
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div52                      11
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div60                      12
#define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div64                      13


/****************************************************************************
 * TxPll :: anaPllControl
 ***************************************************************************/
/* TxPll :: anaPllControl :: pllRestart [15:15] */
#define TXPLL_ANAPLLCONTROL_PLLRESTART_MASK                        0x8000
#define TXPLL_ANAPLLCONTROL_PLLRESTART_ALIGN                       0
#define TXPLL_ANAPLLCONTROL_PLLRESTART_BITS                        1
#define TXPLL_ANAPLLCONTROL_PLLRESTART_SHIFT                       15

/* TxPll :: anaPllControl :: FreqDetRetry_en [14:14] */
#define TXPLL_ANAPLLCONTROL_FREQDETRETRY_EN_MASK                   0x4000
#define TXPLL_ANAPLLCONTROL_FREQDETRETRY_EN_ALIGN                  0
#define TXPLL_ANAPLLCONTROL_FREQDETRETRY_EN_BITS                   1
#define TXPLL_ANAPLLCONTROL_FREQDETRETRY_EN_SHIFT                  14

/* TxPll :: anaPllControl :: FreqDetRestart_en [13:13] */
#define TXPLL_ANAPLLCONTROL_FREQDETRESTART_EN_MASK                 0x2000
#define TXPLL_ANAPLLCONTROL_FREQDETRESTART_EN_ALIGN                0
#define TXPLL_ANAPLLCONTROL_FREQDETRESTART_EN_BITS                 1
#define TXPLL_ANAPLLCONTROL_FREQDETRESTART_EN_SHIFT                13

/* TxPll :: anaPllControl :: FreqMonitor_en [12:12] */
#define TXPLL_ANAPLLCONTROL_FREQMONITOR_EN_MASK                    0x1000
#define TXPLL_ANAPLLCONTROL_FREQMONITOR_EN_ALIGN                   0
#define TXPLL_ANAPLLCONTROL_FREQMONITOR_EN_BITS                    1
#define TXPLL_ANAPLLCONTROL_FREQMONITOR_EN_SHIFT                   12

/* TxPll :: anaPllControl :: VcopRetry_en [11:11] */
#define TXPLL_ANAPLLCONTROL_VCOPRETRY_EN_MASK                      0x0800
#define TXPLL_ANAPLLCONTROL_VCOPRETRY_EN_ALIGN                     0
#define TXPLL_ANAPLLCONTROL_VCOPRETRY_EN_BITS                      1
#define TXPLL_ANAPLLCONTROL_VCOPRETRY_EN_SHIFT                     11

/* TxPll :: anaPllControl :: VcoDone_en [10:10] */
#define TXPLL_ANAPLLCONTROL_VCODONE_EN_MASK                        0x0400
#define TXPLL_ANAPLLCONTROL_VCODONE_EN_ALIGN                       0
#define TXPLL_ANAPLLCONTROL_VCODONE_EN_BITS                        1
#define TXPLL_ANAPLLCONTROL_VCODONE_EN_SHIFT                       10

/* TxPll :: anaPllControl :: LinkRestart_en [09:09] */
#define TXPLL_ANAPLLCONTROL_LINKRESTART_EN_MASK                    0x0200
#define TXPLL_ANAPLLCONTROL_LINKRESTART_EN_ALIGN                   0
#define TXPLL_ANAPLLCONTROL_LINKRESTART_EN_BITS                    1
#define TXPLL_ANAPLLCONTROL_LINKRESTART_EN_SHIFT                   9

/* TxPll :: anaPllControl :: ByteSyncRestart_en [08:08] */
#define TXPLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_MASK                0x0100
#define TXPLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_ALIGN               0
#define TXPLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_BITS                1
#define TXPLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_SHIFT               8

/* TxPll :: anaPllControl :: PllForceDone_en [07:07] */
#define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_EN_MASK                   0x0080
#define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_EN_ALIGN                  0
#define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_EN_BITS                   1
#define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_EN_SHIFT                  7

/* TxPll :: anaPllControl :: PllForceDone [06:06] */
#define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_MASK                      0x0040
#define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_ALIGN                     0
#define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_BITS                      1
#define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_SHIFT                     6

/* TxPll :: anaPllControl :: PllForcePass [05:05] */
#define TXPLL_ANAPLLCONTROL_PLLFORCEPASS_MASK                      0x0020
#define TXPLL_ANAPLLCONTROL_PLLFORCEPASS_ALIGN                     0
#define TXPLL_ANAPLLCONTROL_PLLFORCEPASS_BITS                      1
#define TXPLL_ANAPLLCONTROL_PLLFORCEPASS_SHIFT                     5

/* TxPll :: anaPllControl :: PllForceVcoDone_en [04:04] */
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_MASK                0x0010
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_ALIGN               0
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_BITS                1
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_SHIFT               4

/* TxPll :: anaPllControl :: PllForceVcoDone [03:03] */
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_MASK                   0x0008
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_ALIGN                  0
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_BITS                   1
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_SHIFT                  3

/* TxPll :: anaPllControl :: PllForceVcoPass_en [02:02] */
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_MASK                0x0004
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_ALIGN               0
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_BITS                1
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_SHIFT               2

/* TxPll :: anaPllControl :: PllForceVcoPass [01:01] */
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_MASK                   0x0002
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_ALIGN                  0
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_BITS                   1
#define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_SHIFT                  1

/* TxPll :: anaPllControl :: PllForcePllLock [00:00] */
#define TXPLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_MASK                   0x0001
#define TXPLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_ALIGN                  0
#define TXPLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_BITS                   1
#define TXPLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_SHIFT                  0


/****************************************************************************
 * TxPll :: anaPllTimer1
 ***************************************************************************/
/* TxPll :: anaPllTimer1 :: VcoStepTime [15:08] */
#define TXPLL_ANAPLLTIMER1_VCOSTEPTIME_MASK                        0xff00
#define TXPLL_ANAPLLTIMER1_VCOSTEPTIME_ALIGN                       0
#define TXPLL_ANAPLLTIMER1_VCOSTEPTIME_BITS                        8
#define TXPLL_ANAPLLTIMER1_VCOSTEPTIME_SHIFT                       8

/* TxPll :: anaPllTimer1 :: VcoStartTime [07:00] */
#define TXPLL_ANAPLLTIMER1_VCOSTARTTIME_MASK                       0x00ff
#define TXPLL_ANAPLLTIMER1_VCOSTARTTIME_ALIGN                      0
#define TXPLL_ANAPLLTIMER1_VCOSTARTTIME_BITS                       8
#define TXPLL_ANAPLLTIMER1_VCOSTARTTIME_SHIFT                      0


/****************************************************************************
 * TxPll :: anaPllTimer2
 ***************************************************************************/
/* TxPll :: anaPllTimer2 :: reserved0 [15:15] */
#define TXPLL_ANAPLLTIMER2_RESERVED0_MASK                          0x8000
#define TXPLL_ANAPLLTIMER2_RESERVED0_ALIGN                         0
#define TXPLL_ANAPLLTIMER2_RESERVED0_BITS                          1
#define TXPLL_ANAPLLTIMER2_RESERVED0_SHIFT                         15

/* TxPll :: anaPllTimer2 :: lfckSingleStep_en [14:14] */
#define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_MASK                  0x4000
#define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_ALIGN                 0
#define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_BITS                  1
#define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_SHIFT                 14

/* TxPll :: anaPllTimer2 :: lfckSingleStep [13:13] */
#define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_MASK                     0x2000
#define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_ALIGN                    0
#define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_BITS                     1
#define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_SHIFT                    13

/* TxPll :: anaPllTimer2 :: testMuxSel [12:08] */
#define TXPLL_ANAPLLTIMER2_TESTMUXSEL_MASK                         0x1f00
#define TXPLL_ANAPLLTIMER2_TESTMUXSEL_ALIGN                        0
#define TXPLL_ANAPLLTIMER2_TESTMUXSEL_BITS                         5
#define TXPLL_ANAPLLTIMER2_TESTMUXSEL_SHIFT                        8

/* TxPll :: anaPllTimer2 :: retryTime [07:00] */
#define TXPLL_ANAPLLTIMER2_RETRYTIME_MASK                          0x00ff
#define TXPLL_ANAPLLTIMER2_RETRYTIME_ALIGN                         0
#define TXPLL_ANAPLLTIMER2_RETRYTIME_BITS                          8
#define TXPLL_ANAPLLTIMER2_RETRYTIME_SHIFT                         0


/****************************************************************************
 * TxPll :: anaPllTimer3
 ***************************************************************************/
/* TxPll :: anaPllTimer3 :: reserved0 [15:08] */
#define TXPLL_ANAPLLTIMER3_RESERVED0_MASK                          0xff00
#define TXPLL_ANAPLLTIMER3_RESERVED0_ALIGN                         0
#define TXPLL_ANAPLLTIMER3_RESERVED0_BITS                          8
#define TXPLL_ANAPLLTIMER3_RESERVED0_SHIFT                         8

/* TxPll :: anaPllTimer3 :: freqDetTime [07:00] */
#define TXPLL_ANAPLLTIMER3_FREQDETTIME_MASK                        0x00ff
#define TXPLL_ANAPLLTIMER3_FREQDETTIME_ALIGN                       0
#define TXPLL_ANAPLLTIMER3_FREQDETTIME_BITS                        8
#define TXPLL_ANAPLLTIMER3_FREQDETTIME_SHIFT                       0


/****************************************************************************
 * TxPll :: anaCapControl
 ***************************************************************************/
/* TxPll :: anaCapControl :: StatusControl [15:15] */
#define TXPLL_ANACAPCONTROL_STATUSCONTROL_MASK                     0x8000
#define TXPLL_ANACAPCONTROL_STATUSCONTROL_ALIGN                    0
#define TXPLL_ANACAPCONTROL_STATUSCONTROL_BITS                     1
#define TXPLL_ANACAPCONTROL_STATUSCONTROL_SHIFT                    15

/* TxPll :: anaCapControl :: vcoRestart [14:14] */
#define TXPLL_ANACAPCONTROL_VCORESTART_MASK                        0x4000
#define TXPLL_ANACAPCONTROL_VCORESTART_ALIGN                       0
#define TXPLL_ANACAPCONTROL_VCORESTART_BITS                        1
#define TXPLL_ANACAPCONTROL_VCORESTART_SHIFT                       14

/* TxPll :: anaCapControl :: vcoForceRange_en [13:13] */
#define TXPLL_ANACAPCONTROL_VCOFORCERANGE_EN_MASK                  0x2000
#define TXPLL_ANACAPCONTROL_VCOFORCERANGE_EN_ALIGN                 0
#define TXPLL_ANACAPCONTROL_VCOFORCERANGE_EN_BITS                  1
#define TXPLL_ANACAPCONTROL_VCOFORCERANGE_EN_SHIFT                 13

/* TxPll :: anaCapControl :: vcoForceSlowdn_en [12:12] */
#define TXPLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_MASK                 0x1000
#define TXPLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_ALIGN                0
#define TXPLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_BITS                 1
#define TXPLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_SHIFT                12

/* TxPll :: anaCapControl :: reserved0 [11:10] */
#define TXPLL_ANACAPCONTROL_RESERVED0_MASK                         0x0c00
#define TXPLL_ANACAPCONTROL_RESERVED0_ALIGN                        0
#define TXPLL_ANACAPCONTROL_RESERVED0_BITS                         2
#define TXPLL_ANACAPCONTROL_RESERVED0_SHIFT                        10

/* TxPll :: anaCapControl :: slowdn_xor [09:09] */
#define TXPLL_ANACAPCONTROL_SLOWDN_XOR_MASK                        0x0200
#define TXPLL_ANACAPCONTROL_SLOWDN_XOR_ALIGN                       0
#define TXPLL_ANACAPCONTROL_SLOWDN_XOR_BITS                        1
#define TXPLL_ANACAPCONTROL_SLOWDN_XOR_SHIFT                       9

/* union - case Status [08:00] */
/* TxPll :: anaCapControl :: Slowdn [08:08] */
#define TXPLL_ANACAPCONTROL_STATUS_SLOWDN_MASK                     0x0100
#define TXPLL_ANACAPCONTROL_STATUS_SLOWDN_ALIGN                    0
#define TXPLL_ANACAPCONTROL_STATUS_SLOWDN_BITS                     1
#define TXPLL_ANACAPCONTROL_STATUS_SLOWDN_SHIFT                    8

/* TxPll :: anaCapControl :: reserved0 [07:07] */
#define TXPLL_ANACAPCONTROL_STATUS_RESERVED0_MASK                  0x0080
#define TXPLL_ANACAPCONTROL_STATUS_RESERVED0_ALIGN                 0
#define TXPLL_ANACAPCONTROL_STATUS_RESERVED0_BITS                  1
#define TXPLL_ANACAPCONTROL_STATUS_RESERVED0_SHIFT                 7

/* TxPll :: anaCapControl :: vcoRange [06:00] */
#define TXPLL_ANACAPCONTROL_STATUS_VCORANGE_MASK                   0x007f
#define TXPLL_ANACAPCONTROL_STATUS_VCORANGE_ALIGN                  0
#define TXPLL_ANACAPCONTROL_STATUS_VCORANGE_BITS                   7
#define TXPLL_ANACAPCONTROL_STATUS_VCORANGE_SHIFT                  0


/* union - case Control [08:00] */
/* TxPll :: anaCapControl :: vcoForceSlowdn [08:08] */
#define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCESLOWDN_MASK            0x0100
#define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCESLOWDN_ALIGN           0
#define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCESLOWDN_BITS            1
#define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCESLOWDN_SHIFT           8

/* TxPll :: anaCapControl :: reserved0 [07:07] */
#define TXPLL_ANACAPCONTROL_CONTROL_RESERVED0_MASK                 0x0080
#define TXPLL_ANACAPCONTROL_CONTROL_RESERVED0_ALIGN                0
#define TXPLL_ANACAPCONTROL_CONTROL_RESERVED0_BITS                 1
#define TXPLL_ANACAPCONTROL_CONTROL_RESERVED0_SHIFT                7

/* TxPll :: anaCapControl :: vcoForceRange [06:00] */
#define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCERANGE_MASK             0x007f
#define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCERANGE_ALIGN            0
#define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCERANGE_BITS             7
#define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCERANGE_SHIFT            0



/****************************************************************************
 * TxPll :: anaFreqDetCntr
 ***************************************************************************/
/* TxPll :: anaFreqDetCntr :: resolution [15:08] */
#define TXPLL_ANAFREQDETCNTR_RESOLUTION_MASK                       0xff00
#define TXPLL_ANAFREQDETCNTR_RESOLUTION_ALIGN                      0
#define TXPLL_ANAFREQDETCNTR_RESOLUTION_BITS                       8
#define TXPLL_ANAFREQDETCNTR_RESOLUTION_SHIFT                      8

/* TxPll :: anaFreqDetCntr :: window [07:00] */
#define TXPLL_ANAFREQDETCNTR_WINDOW_MASK                           0x00ff
#define TXPLL_ANAFREQDETCNTR_WINDOW_ALIGN                          0
#define TXPLL_ANAFREQDETCNTR_WINDOW_BITS                           8
#define TXPLL_ANAFREQDETCNTR_WINDOW_SHIFT                          0


/****************************************************************************
 * TxPll :: anaPllAStatus1
 ***************************************************************************/
/* TxPll :: anaPllAStatus1 :: reserved0 [15:14] */
#define TXPLL_ANAPLLASTATUS1_RESERVED0_MASK                        0xc000
#define TXPLL_ANAPLLASTATUS1_RESERVED0_ALIGN                       0
#define TXPLL_ANAPLLASTATUS1_RESERVED0_BITS                        2
#define TXPLL_ANAPLLASTATUS1_RESERVED0_SHIFT                       14

/* TxPll :: anaPllAStatus1 :: kvh [13:12] */
#define TXPLL_ANAPLLASTATUS1_KVH_MASK                              0x3000
#define TXPLL_ANAPLLASTATUS1_KVH_ALIGN                             0
#define TXPLL_ANAPLLASTATUS1_KVH_BITS                              2
#define TXPLL_ANAPLLASTATUS1_KVH_SHIFT                             12

/* TxPll :: anaPllAStatus1 :: pll_range [11:08] */
#define TXPLL_ANAPLLASTATUS1_PLL_RANGE_MASK                        0x0f00
#define TXPLL_ANAPLLASTATUS1_PLL_RANGE_ALIGN                       0
#define TXPLL_ANAPLLASTATUS1_PLL_RANGE_BITS                        4
#define TXPLL_ANAPLLASTATUS1_PLL_RANGE_SHIFT                       8

/* TxPll :: anaPllAStatus1 :: pll_low [07:07] */
#define TXPLL_ANAPLLASTATUS1_PLL_LOW_MASK                          0x0080
#define TXPLL_ANAPLLASTATUS1_PLL_LOW_ALIGN                         0
#define TXPLL_ANAPLLASTATUS1_PLL_LOW_BITS                          1
#define TXPLL_ANAPLLASTATUS1_PLL_LOW_SHIFT                         7

/* TxPll :: anaPllAStatus1 :: reserved1 [06:04] */
#define TXPLL_ANAPLLASTATUS1_RESERVED1_MASK                        0x0070
#define TXPLL_ANAPLLASTATUS1_RESERVED1_ALIGN                       0
#define TXPLL_ANAPLLASTATUS1_RESERVED1_BITS                        3
#define TXPLL_ANAPLLASTATUS1_RESERVED1_SHIFT                       4

/* TxPll :: anaPllAStatus1 :: pll_Ndiv [03:00] */
#define TXPLL_ANAPLLASTATUS1_PLL_NDIV_MASK                         0x000f
#define TXPLL_ANAPLLASTATUS1_PLL_NDIV_ALIGN                        0
#define TXPLL_ANAPLLASTATUS1_PLL_NDIV_BITS                         4
#define TXPLL_ANAPLLASTATUS1_PLL_NDIV_SHIFT                        0


/****************************************************************************
 * TxPll :: anaPllAControl0
 ***************************************************************************/
/* TxPll :: anaPllAControl0 :: refl_clkgen [15:15] */
#define TXPLL_ANAPLLACONTROL0_REFL_CLKGEN_MASK                     0x8000
#define TXPLL_ANAPLLACONTROL0_REFL_CLKGEN_ALIGN                    0
#define TXPLL_ANAPLLACONTROL0_REFL_CLKGEN_BITS                     1
#define TXPLL_ANAPLLACONTROL0_REFL_CLKGEN_SHIFT                    15

/* TxPll :: anaPllAControl0 :: iclkidrv1 [14:12] */
#define TXPLL_ANAPLLACONTROL0_ICLKIDRV1_MASK                       0x7000
#define TXPLL_ANAPLLACONTROL0_ICLKIDRV1_ALIGN                      0
#define TXPLL_ANAPLLACONTROL0_ICLKIDRV1_BITS                       3
#define TXPLL_ANAPLLACONTROL0_ICLKIDRV1_SHIFT                      12

/* TxPll :: anaPllAControl0 :: iclkodrv1 [11:09] */
#define TXPLL_ANAPLLACONTROL0_ICLKODRV1_MASK                       0x0e00
#define TXPLL_ANAPLLACONTROL0_ICLKODRV1_ALIGN                      0
#define TXPLL_ANAPLLACONTROL0_ICLKODRV1_BITS                       3
#define TXPLL_ANAPLLACONTROL0_ICLKODRV1_SHIFT                      9

/* TxPll :: anaPllAControl0 :: iclkodrv2 [08:06] */
#define TXPLL_ANAPLLACONTROL0_ICLKODRV2_MASK                       0x01c0
#define TXPLL_ANAPLLACONTROL0_ICLKODRV2_ALIGN                      0
#define TXPLL_ANAPLLACONTROL0_ICLKODRV2_BITS                       3
#define TXPLL_ANAPLLACONTROL0_ICLKODRV2_SHIFT                      6

/* TxPll :: anaPllAControl0 :: iclkdiv2 [05:03] */
#define TXPLL_ANAPLLACONTROL0_ICLKDIV2_MASK                        0x0038
#define TXPLL_ANAPLLACONTROL0_ICLKDIV2_ALIGN                       0
#define TXPLL_ANAPLLACONTROL0_ICLKDIV2_BITS                        3
#define TXPLL_ANAPLLACONTROL0_ICLKDIV2_SHIFT                       3

/* TxPll :: anaPllAControl0 :: reserved0 [02:02] */
#define TXPLL_ANAPLLACONTROL0_RESERVED0_MASK                       0x0004
#define TXPLL_ANAPLLACONTROL0_RESERVED0_ALIGN                      0
#define TXPLL_ANAPLLACONTROL0_RESERVED0_BITS                       1
#define TXPLL_ANAPLLACONTROL0_RESERVED0_SHIFT                      2

/* TxPll :: anaPllAControl0 :: vddr_bgb [01:01] */
#define TXPLL_ANAPLLACONTROL0_VDDR_BGB_MASK                        0x0002
#define TXPLL_ANAPLLACONTROL0_VDDR_BGB_ALIGN                       0
#define TXPLL_ANAPLLACONTROL0_VDDR_BGB_BITS                        1
#define TXPLL_ANAPLLACONTROL0_VDDR_BGB_SHIFT                       1

/* TxPll :: anaPllAControl0 :: clksel_halfrate [00:00] */
#define TXPLL_ANAPLLACONTROL0_CLKSEL_HALFRATE_MASK                 0x0001
#define TXPLL_ANAPLLACONTROL0_CLKSEL_HALFRATE_ALIGN                0
#define TXPLL_ANAPLLACONTROL0_CLKSEL_HALFRATE_BITS                 1
#define TXPLL_ANAPLLACONTROL0_CLKSEL_HALFRATE_SHIFT                0


/****************************************************************************
 * TxPll :: anaPllAControl1
 ***************************************************************************/
/* TxPll :: anaPllAControl1 :: kvhce [15:15] */
#define TXPLL_ANAPLLACONTROL1_KVHCE_MASK                           0x8000
#define TXPLL_ANAPLLACONTROL1_KVHCE_ALIGN                          0
#define TXPLL_ANAPLLACONTROL1_KVHCE_BITS                           1
#define TXPLL_ANAPLLACONTROL1_KVHCE_SHIFT                          15

/* TxPll :: anaPllAControl1 :: reserved0 [14:11] */
#define TXPLL_ANAPLLACONTROL1_RESERVED0_MASK                       0x7800
#define TXPLL_ANAPLLACONTROL1_RESERVED0_ALIGN                      0
#define TXPLL_ANAPLLACONTROL1_RESERVED0_BITS                       4
#define TXPLL_ANAPLLACONTROL1_RESERVED0_SHIFT                      11

/* TxPll :: anaPllAControl1 :: iclkibuf4 [10:08] */
#define TXPLL_ANAPLLACONTROL1_ICLKIBUF4_MASK                       0x0700
#define TXPLL_ANAPLLACONTROL1_ICLKIBUF4_ALIGN                      0
#define TXPLL_ANAPLLACONTROL1_ICLKIBUF4_BITS                       3
#define TXPLL_ANAPLLACONTROL1_ICLKIBUF4_SHIFT                      8

/* TxPll :: anaPllAControl1 :: ibias_all [07:05] */
#define TXPLL_ANAPLLACONTROL1_IBIAS_ALL_MASK                       0x00e0
#define TXPLL_ANAPLLACONTROL1_IBIAS_ALL_ALIGN                      0
#define TXPLL_ANAPLLACONTROL1_IBIAS_ALL_BITS                       3
#define TXPLL_ANAPLLACONTROL1_IBIAS_ALL_SHIFT                      5

/* TxPll :: anaPllAControl1 :: reserved1 [04:03] */
#define TXPLL_ANAPLLACONTROL1_RESERVED1_MASK                       0x0018
#define TXPLL_ANAPLLACONTROL1_RESERVED1_ALIGN                      0
#define TXPLL_ANAPLLACONTROL1_RESERVED1_BITS                       2
#define TXPLL_ANAPLLACONTROL1_RESERVED1_SHIFT                      3

/* TxPll :: anaPllAControl1 :: pll2rx_clkbw [02:01] */
#define TXPLL_ANAPLLACONTROL1_PLL2RX_CLKBW_MASK                    0x0006
#define TXPLL_ANAPLLACONTROL1_PLL2RX_CLKBW_ALIGN                   0
#define TXPLL_ANAPLLACONTROL1_PLL2RX_CLKBW_BITS                    2
#define TXPLL_ANAPLLACONTROL1_PLL2RX_CLKBW_SHIFT                   1

/* TxPll :: anaPllAControl1 :: refh_clkgen [00:00] */
#define TXPLL_ANAPLLACONTROL1_REFH_CLKGEN_MASK                     0x0001
#define TXPLL_ANAPLLACONTROL1_REFH_CLKGEN_ALIGN                    0
#define TXPLL_ANAPLLACONTROL1_REFH_CLKGEN_BITS                     1
#define TXPLL_ANAPLLACONTROL1_REFH_CLKGEN_SHIFT                    0


/****************************************************************************
 * TxPll :: anaPllAControl2
 ***************************************************************************/
/* TxPll :: anaPllAControl2 :: ick2 [15:15] */
#define TXPLL_ANAPLLACONTROL2_ICK2_MASK                            0x8000
#define TXPLL_ANAPLLACONTROL2_ICK2_ALIGN                           0
#define TXPLL_ANAPLLACONTROL2_ICK2_BITS                            1
#define TXPLL_ANAPLLACONTROL2_ICK2_SHIFT                           15

/* TxPll :: anaPllAControl2 :: ick0 [14:14] */
#define TXPLL_ANAPLLACONTROL2_ICK0_MASK                            0x4000
#define TXPLL_ANAPLLACONTROL2_ICK0_ALIGN                           0
#define TXPLL_ANAPLLACONTROL2_ICK0_BITS                            1
#define TXPLL_ANAPLLACONTROL2_ICK0_SHIFT                           14

/* TxPll :: anaPllAControl2 :: ick1 [13:13] */
#define TXPLL_ANAPLLACONTROL2_ICK1_MASK                            0x2000
#define TXPLL_ANAPLLACONTROL2_ICK1_ALIGN                           0
#define TXPLL_ANAPLLACONTROL2_ICK1_BITS                            1
#define TXPLL_ANAPLLACONTROL2_ICK1_SHIFT                           13

/* TxPll :: anaPllAControl2 :: icp2 [12:12] */
#define TXPLL_ANAPLLACONTROL2_ICP2_MASK                            0x1000
#define TXPLL_ANAPLLACONTROL2_ICP2_ALIGN                           0
#define TXPLL_ANAPLLACONTROL2_ICP2_BITS                            1
#define TXPLL_ANAPLLACONTROL2_ICP2_SHIFT                           12

/* TxPll :: anaPllAControl2 :: icp0 [11:11] */
#define TXPLL_ANAPLLACONTROL2_ICP0_MASK                            0x0800
#define TXPLL_ANAPLLACONTROL2_ICP0_ALIGN                           0
#define TXPLL_ANAPLLACONTROL2_ICP0_BITS                            1
#define TXPLL_ANAPLLACONTROL2_ICP0_SHIFT                           11

/* TxPll :: anaPllAControl2 :: icp1 [10:10] */
#define TXPLL_ANAPLLACONTROL2_ICP1_MASK                            0x0400
#define TXPLL_ANAPLLACONTROL2_ICP1_ALIGN                           0
#define TXPLL_ANAPLLACONTROL2_ICP1_BITS                            1
#define TXPLL_ANAPLLACONTROL2_ICP1_SHIFT                           10

/* TxPll :: anaPllAControl2 :: ibmax [09:09] */
#define TXPLL_ANAPLLACONTROL2_IBMAX_MASK                           0x0200
#define TXPLL_ANAPLLACONTROL2_IBMAX_ALIGN                          0
#define TXPLL_ANAPLLACONTROL2_IBMAX_BITS                           1
#define TXPLL_ANAPLLACONTROL2_IBMAX_SHIFT                          9

/* TxPll :: anaPllAControl2 :: ibmode [08:08] */
#define TXPLL_ANAPLLACONTROL2_IBMODE_MASK                          0x0100
#define TXPLL_ANAPLLACONTROL2_IBMODE_ALIGN                         0
#define TXPLL_ANAPLLACONTROL2_IBMODE_BITS                          1
#define TXPLL_ANAPLLACONTROL2_IBMODE_SHIFT                         8

/* TxPll :: anaPllAControl2 :: ibmin [07:07] */
#define TXPLL_ANAPLLACONTROL2_IBMIN_MASK                           0x0080
#define TXPLL_ANAPLLACONTROL2_IBMIN_ALIGN                          0
#define TXPLL_ANAPLLACONTROL2_IBMIN_BITS                           1
#define TXPLL_ANAPLLACONTROL2_IBMIN_SHIFT                          7

/* TxPll :: anaPllAControl2 :: refh_pll [06:06] */
#define TXPLL_ANAPLLACONTROL2_REFH_PLL_MASK                        0x0040
#define TXPLL_ANAPLLACONTROL2_REFH_PLL_ALIGN                       0
#define TXPLL_ANAPLLACONTROL2_REFH_PLL_BITS                        1
#define TXPLL_ANAPLLACONTROL2_REFH_PLL_SHIFT                       6

/* TxPll :: anaPllAControl2 :: refl_pll [05:05] */
#define TXPLL_ANAPLLACONTROL2_REFL_PLL_MASK                        0x0020
#define TXPLL_ANAPLLACONTROL2_REFL_PLL_ALIGN                       0
#define TXPLL_ANAPLLACONTROL2_REFL_PLL_BITS                        1
#define TXPLL_ANAPLLACONTROL2_REFL_PLL_SHIFT                       5

/* TxPll :: anaPllAControl2 :: iqp [04:02] */
#define TXPLL_ANAPLLACONTROL2_IQP_MASK                             0x001c
#define TXPLL_ANAPLLACONTROL2_IQP_ALIGN                            0
#define TXPLL_ANAPLLACONTROL2_IQP_BITS                             3
#define TXPLL_ANAPLLACONTROL2_IQP_SHIFT                            2

/* TxPll :: anaPllAControl2 :: en_p3 [01:01] */
#define TXPLL_ANAPLLACONTROL2_EN_P3_MASK                           0x0002
#define TXPLL_ANAPLLACONTROL2_EN_P3_ALIGN                          0
#define TXPLL_ANAPLLACONTROL2_EN_P3_BITS                           1
#define TXPLL_ANAPLLACONTROL2_EN_P3_SHIFT                          1

/* TxPll :: anaPllAControl2 :: enable_ftune [00:00] */
#define TXPLL_ANAPLLACONTROL2_ENABLE_FTUNE_MASK                    0x0001
#define TXPLL_ANAPLLACONTROL2_ENABLE_FTUNE_ALIGN                   0
#define TXPLL_ANAPLLACONTROL2_ENABLE_FTUNE_BITS                    1
#define TXPLL_ANAPLLACONTROL2_ENABLE_FTUNE_SHIFT                   0


/****************************************************************************
 * TxPll :: anaPllAControl3
 ***************************************************************************/
/* TxPll :: anaPllAControl3 :: test_rx [15:15] */
#define TXPLL_ANAPLLACONTROL3_TEST_RX_MASK                         0x8000
#define TXPLL_ANAPLLACONTROL3_TEST_RX_ALIGN                        0
#define TXPLL_ANAPLLACONTROL3_TEST_RX_BITS                         1
#define TXPLL_ANAPLLACONTROL3_TEST_RX_SHIFT                        15

/* TxPll :: anaPllAControl3 :: test_pll [14:14] */
#define TXPLL_ANAPLLACONTROL3_TEST_PLL_MASK                        0x4000
#define TXPLL_ANAPLLACONTROL3_TEST_PLL_ALIGN                       0
#define TXPLL_ANAPLLACONTROL3_TEST_PLL_BITS                        1
#define TXPLL_ANAPLLACONTROL3_TEST_PLL_SHIFT                       14

/* TxPll :: anaPllAControl3 :: test_vc [13:13] */
#define TXPLL_ANAPLLACONTROL3_TEST_VC_MASK                         0x2000
#define TXPLL_ANAPLLACONTROL3_TEST_VC_ALIGN                        0
#define TXPLL_ANAPLLACONTROL3_TEST_VC_BITS                         1
#define TXPLL_ANAPLLACONTROL3_TEST_VC_SHIFT                        13

/* TxPll :: anaPllAControl3 :: test_vref [12:12] */
#define TXPLL_ANAPLLACONTROL3_TEST_VREF_MASK                       0x1000
#define TXPLL_ANAPLLACONTROL3_TEST_VREF_ALIGN                      0
#define TXPLL_ANAPLLACONTROL3_TEST_VREF_BITS                       1
#define TXPLL_ANAPLLACONTROL3_TEST_VREF_SHIFT                      12

/* TxPll :: anaPllAControl3 :: iop2 [11:11] */
#define TXPLL_ANAPLLACONTROL3_IOP2_MASK                            0x0800
#define TXPLL_ANAPLLACONTROL3_IOP2_ALIGN                           0
#define TXPLL_ANAPLLACONTROL3_IOP2_BITS                            1
#define TXPLL_ANAPLLACONTROL3_IOP2_SHIFT                           11

/* TxPll :: anaPllAControl3 :: iop0 [10:10] */
#define TXPLL_ANAPLLACONTROL3_IOP0_MASK                            0x0400
#define TXPLL_ANAPLLACONTROL3_IOP0_ALIGN                           0
#define TXPLL_ANAPLLACONTROL3_IOP0_BITS                            1
#define TXPLL_ANAPLLACONTROL3_IOP0_SHIFT                           10

/* TxPll :: anaPllAControl3 :: iop1 [09:09] */
#define TXPLL_ANAPLLACONTROL3_IOP1_MASK                            0x0200
#define TXPLL_ANAPLLACONTROL3_IOP1_ALIGN                           0
#define TXPLL_ANAPLLACONTROL3_IOP1_BITS                            1
#define TXPLL_ANAPLLACONTROL3_IOP1_SHIFT                           9

/* TxPll :: anaPllAControl3 :: icomp2 [08:08] */
#define TXPLL_ANAPLLACONTROL3_ICOMP2_MASK                          0x0100
#define TXPLL_ANAPLLACONTROL3_ICOMP2_ALIGN                         0
#define TXPLL_ANAPLLACONTROL3_ICOMP2_BITS                          1
#define TXPLL_ANAPLLACONTROL3_ICOMP2_SHIFT                         8

/* TxPll :: anaPllAControl3 :: icomp0 [07:07] */
#define TXPLL_ANAPLLACONTROL3_ICOMP0_MASK                          0x0080
#define TXPLL_ANAPLLACONTROL3_ICOMP0_ALIGN                         0
#define TXPLL_ANAPLLACONTROL3_ICOMP0_BITS                          1
#define TXPLL_ANAPLLACONTROL3_ICOMP0_SHIFT                         7

/* TxPll :: anaPllAControl3 :: icomp1 [06:06] */
#define TXPLL_ANAPLLACONTROL3_ICOMP1_MASK                          0x0040
#define TXPLL_ANAPLLACONTROL3_ICOMP1_ALIGN                         0
#define TXPLL_ANAPLLACONTROL3_ICOMP1_BITS                          1
#define TXPLL_ANAPLLACONTROL3_ICOMP1_SHIFT                         6

/* TxPll :: anaPllAControl3 :: icml2 [05:05] */
#define TXPLL_ANAPLLACONTROL3_ICML2_MASK                           0x0020
#define TXPLL_ANAPLLACONTROL3_ICML2_ALIGN                          0
#define TXPLL_ANAPLLACONTROL3_ICML2_BITS                           1
#define TXPLL_ANAPLLACONTROL3_ICML2_SHIFT                          5

/* TxPll :: anaPllAControl3 :: icml0 [04:04] */
#define TXPLL_ANAPLLACONTROL3_ICML0_MASK                           0x0010
#define TXPLL_ANAPLLACONTROL3_ICML0_ALIGN                          0
#define TXPLL_ANAPLLACONTROL3_ICML0_BITS                           1
#define TXPLL_ANAPLLACONTROL3_ICML0_SHIFT                          4

/* TxPll :: anaPllAControl3 :: icml1 [03:03] */
#define TXPLL_ANAPLLACONTROL3_ICML1_MASK                           0x0008
#define TXPLL_ANAPLLACONTROL3_ICML1_ALIGN                          0
#define TXPLL_ANAPLLACONTROL3_ICML1_BITS                           1
#define TXPLL_ANAPLLACONTROL3_ICML1_SHIFT                          3

/* TxPll :: anaPllAControl3 :: ivco2 [02:02] */
#define TXPLL_ANAPLLACONTROL3_IVCO2_MASK                           0x0004
#define TXPLL_ANAPLLACONTROL3_IVCO2_ALIGN                          0
#define TXPLL_ANAPLLACONTROL3_IVCO2_BITS                           1
#define TXPLL_ANAPLLACONTROL3_IVCO2_SHIFT                          2

/* TxPll :: anaPllAControl3 :: ivco0 [01:01] */
#define TXPLL_ANAPLLACONTROL3_IVCO0_MASK                           0x0002
#define TXPLL_ANAPLLACONTROL3_IVCO0_ALIGN                          0
#define TXPLL_ANAPLLACONTROL3_IVCO0_BITS                           1
#define TXPLL_ANAPLLACONTROL3_IVCO0_SHIFT                          1

/* TxPll :: anaPllAControl3 :: ivco1 [00:00] */
#define TXPLL_ANAPLLACONTROL3_IVCO1_MASK                           0x0001
#define TXPLL_ANAPLLACONTROL3_IVCO1_ALIGN                          0
#define TXPLL_ANAPLLACONTROL3_IVCO1_BITS                           1
#define TXPLL_ANAPLLACONTROL3_IVCO1_SHIFT                          0


/****************************************************************************
 * TxPll :: anaPllAControl4
 ***************************************************************************/
/* TxPll :: anaPllAControl4 :: en65g [15:15] */
#define TXPLL_ANAPLLACONTROL4_EN65G_MASK                           0x8000
#define TXPLL_ANAPLLACONTROL4_EN65G_ALIGN                          0
#define TXPLL_ANAPLLACONTROL4_EN65G_BITS                           1
#define TXPLL_ANAPLLACONTROL4_EN65G_SHIFT                          15

/* TxPll :: anaPllAControl4 :: kvh_force [14:12] */
#define TXPLL_ANAPLLACONTROL4_KVH_FORCE_MASK                       0x7000
#define TXPLL_ANAPLLACONTROL4_KVH_FORCE_ALIGN                      0
#define TXPLL_ANAPLLACONTROL4_KVH_FORCE_BITS                       3
#define TXPLL_ANAPLLACONTROL4_KVH_FORCE_SHIFT                      12

/* TxPll :: anaPllAControl4 :: vddr_bgb [11:11] */
#define TXPLL_ANAPLLACONTROL4_VDDR_BGB_MASK                        0x0800
#define TXPLL_ANAPLLACONTROL4_VDDR_BGB_ALIGN                       0
#define TXPLL_ANAPLLACONTROL4_VDDR_BGB_BITS                        1
#define TXPLL_ANAPLLACONTROL4_VDDR_BGB_SHIFT                       11

/* TxPll :: anaPllAControl4 :: comp_vth [10:10] */
#define TXPLL_ANAPLLACONTROL4_COMP_VTH_MASK                        0x0400
#define TXPLL_ANAPLLACONTROL4_COMP_VTH_ALIGN                       0
#define TXPLL_ANAPLLACONTROL4_COMP_VTH_BITS                        1
#define TXPLL_ANAPLLACONTROL4_COMP_VTH_SHIFT                       10

/* TxPll :: anaPllAControl4 :: actrl [09:08] */
#define TXPLL_ANAPLLACONTROL4_ACTRL_MASK                           0x0300
#define TXPLL_ANAPLLACONTROL4_ACTRL_ALIGN                          0
#define TXPLL_ANAPLLACONTROL4_ACTRL_BITS                           2
#define TXPLL_ANAPLLACONTROL4_ACTRL_SHIFT                          8

/* TxPll :: anaPllAControl4 :: ctatadj [07:04] */
#define TXPLL_ANAPLLACONTROL4_CTATADJ_MASK                         0x00f0
#define TXPLL_ANAPLLACONTROL4_CTATADJ_ALIGN                        0
#define TXPLL_ANAPLLACONTROL4_CTATADJ_BITS                         4
#define TXPLL_ANAPLLACONTROL4_CTATADJ_SHIFT                        4

/* TxPll :: anaPllAControl4 :: ptatadj [03:00] */
#define TXPLL_ANAPLLACONTROL4_PTATADJ_MASK                         0x000f
#define TXPLL_ANAPLLACONTROL4_PTATADJ_ALIGN                        0
#define TXPLL_ANAPLLACONTROL4_PTATADJ_BITS                         4
#define TXPLL_ANAPLLACONTROL4_PTATADJ_SHIFT                        0


/****************************************************************************
 * Hypercore_USER_Tx0
 ***************************************************************************/
/****************************************************************************
 * Tx0 :: anaTxAStatus0
 ***************************************************************************/
/* Tx0 :: anaTxAStatus0 :: reserved0 [15:07] */
#define TX0_ANATXASTATUS0_RESERVED0_MASK                           0xff80
#define TX0_ANATXASTATUS0_RESERVED0_ALIGN                          0
#define TX0_ANATXASTATUS0_RESERVED0_BITS                           9
#define TX0_ANATXASTATUS0_RESERVED0_SHIFT                          7

/* Tx0 :: anaTxAStatus0 :: txdisable_ln [06:06] */
#define TX0_ANATXASTATUS0_TXDISABLE_LN_MASK                        0x0040
#define TX0_ANATXASTATUS0_TXDISABLE_LN_ALIGN                       0
#define TX0_ANATXASTATUS0_TXDISABLE_LN_BITS                        1
#define TX0_ANATXASTATUS0_TXDISABLE_LN_SHIFT                       6

/* Tx0 :: anaTxAStatus0 :: txferr_stky [05:05] */
#define TX0_ANATXASTATUS0_TXFERR_STKY_MASK                         0x0020
#define TX0_ANATXASTATUS0_TXFERR_STKY_ALIGN                        0
#define TX0_ANATXASTATUS0_TXFERR_STKY_BITS                         1
#define TX0_ANATXASTATUS0_TXFERR_STKY_SHIFT                        5

/* Tx0 :: anaTxAStatus0 :: tbi_mode [04:04] */
#define TX0_ANATXASTATUS0_TBI_MODE_MASK                            0x0010
#define TX0_ANATXASTATUS0_TBI_MODE_ALIGN                           0
#define TX0_ANATXASTATUS0_TBI_MODE_BITS                            1
#define TX0_ANATXASTATUS0_TBI_MODE_SHIFT                           4

/* Tx0 :: anaTxAStatus0 :: tx_reset [03:03] */
#define TX0_ANATXASTATUS0_TX_RESET_MASK                            0x0008
#define TX0_ANATXASTATUS0_TX_RESET_ALIGN                           0
#define TX0_ANATXASTATUS0_TX_RESET_BITS                            1
#define TX0_ANATXASTATUS0_TX_RESET_SHIFT                           3

/* Tx0 :: anaTxAStatus0 :: tx_pwrdn [02:02] */
#define TX0_ANATXASTATUS0_TX_PWRDN_MASK                            0x0004
#define TX0_ANATXASTATUS0_TX_PWRDN_ALIGN                           0
#define TX0_ANATXASTATUS0_TX_PWRDN_BITS                            1
#define TX0_ANATXASTATUS0_TX_PWRDN_SHIFT                           2

/* Tx0 :: anaTxAStatus0 :: rltxferr_stky [01:01] */
#define TX0_ANATXASTATUS0_RLTXFERR_STKY_MASK                       0x0002
#define TX0_ANATXASTATUS0_RLTXFERR_STKY_ALIGN                      0
#define TX0_ANATXASTATUS0_RLTXFERR_STKY_BITS                       1
#define TX0_ANATXASTATUS0_RLTXFERR_STKY_SHIFT                      1

/* Tx0 :: anaTxAStatus0 :: txpll_lock [00:00] */
#define TX0_ANATXASTATUS0_TXPLL_LOCK_MASK                          0x0001
#define TX0_ANATXASTATUS0_TXPLL_LOCK_ALIGN                         0
#define TX0_ANATXASTATUS0_TXPLL_LOCK_BITS                          1
#define TX0_ANATXASTATUS0_TXPLL_LOCK_SHIFT                         0


/****************************************************************************
 * Tx0 :: anaTxAControl0
 ***************************************************************************/
/* Tx0 :: anaTxAControl0 :: reserved0 [15:15] */
#define TX0_ANATXACONTROL0_RESERVED0_MASK                          0x8000
#define TX0_ANATXACONTROL0_RESERVED0_ALIGN                         0
#define TX0_ANATXACONTROL0_RESERVED0_BITS                          1
#define TX0_ANATXACONTROL0_RESERVED0_SHIFT                         15

/* Tx0 :: anaTxAControl0 :: force_txclk [14:14] */
#define TX0_ANATXACONTROL0_FORCE_TXCLK_MASK                        0x4000
#define TX0_ANATXACONTROL0_FORCE_TXCLK_ALIGN                       0
#define TX0_ANATXACONTROL0_FORCE_TXCLK_BITS                        1
#define TX0_ANATXACONTROL0_FORCE_TXCLK_SHIFT                       14

/* Tx0 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */
#define TX0_ANATXACONTROL0_TX1G_FIFO_RST_MASK                      0x2000
#define TX0_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN                     0
#define TX0_ANATXACONTROL0_TX1G_FIFO_RST_BITS                      1
#define TX0_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT                     13

/* Tx0 :: anaTxAControl0 :: gloopOutEn [12:12] */
#define TX0_ANATXACONTROL0_GLOOPOUTEN_MASK                         0x1000
#define TX0_ANATXACONTROL0_GLOOPOUTEN_ALIGN                        0
#define TX0_ANATXACONTROL0_GLOOPOUTEN_BITS                         1
#define TX0_ANATXACONTROL0_GLOOPOUTEN_SHIFT                        12

/* Tx0 :: anaTxAControl0 :: reserved1 [11:09] */
#define TX0_ANATXACONTROL0_RESERVED1_MASK                          0x0e00
#define TX0_ANATXACONTROL0_RESERVED1_ALIGN                         0
#define TX0_ANATXACONTROL0_RESERVED1_BITS                          3
#define TX0_ANATXACONTROL0_RESERVED1_SHIFT                         9

/* Tx0 :: anaTxAControl0 :: prbs_en [08:08] */
#define TX0_ANATXACONTROL0_PRBS_EN_MASK                            0x0100
#define TX0_ANATXACONTROL0_PRBS_EN_ALIGN                           0
#define TX0_ANATXACONTROL0_PRBS_EN_BITS                            1
#define TX0_ANATXACONTROL0_PRBS_EN_SHIFT                           8

/* Tx0 :: anaTxAControl0 :: pckt_en [07:07] */
#define TX0_ANATXACONTROL0_PCKT_EN_MASK                            0x0080
#define TX0_ANATXACONTROL0_PCKT_EN_ALIGN                           0
#define TX0_ANATXACONTROL0_PCKT_EN_BITS                            1
#define TX0_ANATXACONTROL0_PCKT_EN_SHIFT                           7

/* Tx0 :: anaTxAControl0 :: pckt_strt [06:06] */
#define TX0_ANATXACONTROL0_PCKT_STRT_MASK                          0x0040
#define TX0_ANATXACONTROL0_PCKT_STRT_ALIGN                         0
#define TX0_ANATXACONTROL0_PCKT_STRT_BITS                          1
#define TX0_ANATXACONTROL0_PCKT_STRT_SHIFT                         6

/* Tx0 :: anaTxAControl0 :: txpol_flip [05:05] */
#define TX0_ANATXACONTROL0_TXPOL_FLIP_MASK                         0x0020
#define TX0_ANATXACONTROL0_TXPOL_FLIP_ALIGN                        0
#define TX0_ANATXACONTROL0_TXPOL_FLIP_BITS                         1
#define TX0_ANATXACONTROL0_TXPOL_FLIP_SHIFT                        5

/* Tx0 :: anaTxAControl0 :: rtbi_flip [04:04] */
#define TX0_ANATXACONTROL0_RTBI_FLIP_MASK                          0x0010
#define TX0_ANATXACONTROL0_RTBI_FLIP_ALIGN                         0
#define TX0_ANATXACONTROL0_RTBI_FLIP_BITS                          1
#define TX0_ANATXACONTROL0_RTBI_FLIP_SHIFT                         4

/* Tx0 :: anaTxAControl0 :: eden_r [03:03] */
#define TX0_ANATXACONTROL0_EDEN_R_MASK                             0x0008
#define TX0_ANATXACONTROL0_EDEN_R_ALIGN                            0
#define TX0_ANATXACONTROL0_EDEN_R_BITS                             1
#define TX0_ANATXACONTROL0_EDEN_R_SHIFT                            3

/* Tx0 :: anaTxAControl0 :: eden_force_r [02:02] */
#define TX0_ANATXACONTROL0_EDEN_FORCE_R_MASK                       0x0004
#define TX0_ANATXACONTROL0_EDEN_FORCE_R_ALIGN                      0
#define TX0_ANATXACONTROL0_EDEN_FORCE_R_BITS                       1
#define TX0_ANATXACONTROL0_EDEN_FORCE_R_SHIFT                      2

/* Tx0 :: anaTxAControl0 :: txpat_en [01:01] */
#define TX0_ANATXACONTROL0_TXPAT_EN_MASK                           0x0002
#define TX0_ANATXACONTROL0_TXPAT_EN_ALIGN                          0
#define TX0_ANATXACONTROL0_TXPAT_EN_BITS                           1
#define TX0_ANATXACONTROL0_TXPAT_EN_SHIFT                          1

/* Tx0 :: anaTxAControl0 :: tx_mdata_en [00:00] */
#define TX0_ANATXACONTROL0_TX_MDATA_EN_MASK                        0x0001
#define TX0_ANATXACONTROL0_TX_MDATA_EN_ALIGN                       0
#define TX0_ANATXACONTROL0_TX_MDATA_EN_BITS                        1
#define TX0_ANATXACONTROL0_TX_MDATA_EN_SHIFT                       0


/****************************************************************************
 * Tx0 :: anaTxmdata0
 ***************************************************************************/
/* Tx0 :: anaTxmdata0 :: txTestMuxSel [15:13] */
#define TX0_ANATXMDATA0_TXTESTMUXSEL_MASK                          0xe000
#define TX0_ANATXMDATA0_TXTESTMUXSEL_ALIGN                         0
#define TX0_ANATXMDATA0_TXTESTMUXSEL_BITS                          3
#define TX0_ANATXMDATA0_TXTESTMUXSEL_SHIFT                         13

/* Tx0 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */
#define TX0_ANATXMDATA0_RLFIFO_TSTSEL_MASK                         0x1c00
#define TX0_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN                        0
#define TX0_ANATXMDATA0_RLFIFO_TSTSEL_BITS                         3
#define TX0_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT                        10

/* Tx0 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */
#define TX0_ANATXMDATA0_TXMDIOTSTDATAL_MASK                        0x03ff
#define TX0_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN                       0
#define TX0_ANATXMDATA0_TXMDIOTSTDATAL_BITS                        10
#define TX0_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT                       0


/****************************************************************************
 * Tx0 :: anaTxmdata1
 ***************************************************************************/
/* Tx0 :: anaTxmdata1 :: reserved0 [15:10] */
#define TX0_ANATXMDATA1_RESERVED0_MASK                             0xfc00
#define TX0_ANATXMDATA1_RESERVED0_ALIGN                            0
#define TX0_ANATXMDATA1_RESERVED0_BITS                             6
#define TX0_ANATXMDATA1_RESERVED0_SHIFT                            10

/* Tx0 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */
#define TX0_ANATXMDATA1_TXMDIOTSTDATAH_MASK                        0x03ff
#define TX0_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN                       0
#define TX0_ANATXMDATA1_TXMDIOTSTDATAH_BITS                        10
#define TX0_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT                       0


/****************************************************************************
 * Tx0 :: anaTxAStatus1
 ***************************************************************************/
/* Tx0 :: anaTxAStatus1 :: tx_id [15:14] */
#define TX0_ANATXASTATUS1_TX_ID_MASK                               0xc000
#define TX0_ANATXASTATUS1_TX_ID_ALIGN                              0
#define TX0_ANATXASTATUS1_TX_ID_BITS                               2
#define TX0_ANATXASTATUS1_TX_ID_SHIFT                              14

/* Tx0 :: anaTxAStatus1 :: reserved0 [13:00] */
#define TX0_ANATXASTATUS1_RESERVED0_MASK                           0x3fff
#define TX0_ANATXASTATUS1_RESERVED0_ALIGN                          0
#define TX0_ANATXASTATUS1_RESERVED0_BITS                           14
#define TX0_ANATXASTATUS1_RESERVED0_SHIFT                          0


/****************************************************************************
 * Tx0 :: anaTxAControl1
 ***************************************************************************/
/* Tx0 :: anaTxAControl1 :: id2c [15:13] */
#define TX0_ANATXACONTROL1_ID2C_MASK                               0xe000
#define TX0_ANATXACONTROL1_ID2C_ALIGN                              0
#define TX0_ANATXACONTROL1_ID2C_BITS                               3
#define TX0_ANATXACONTROL1_ID2C_SHIFT                              13

/* Tx0 :: anaTxAControl1 :: refl_tx [12:12] */
#define TX0_ANATXACONTROL1_REFL_TX_MASK                            0x1000
#define TX0_ANATXACONTROL1_REFL_TX_ALIGN                           0
#define TX0_ANATXACONTROL1_REFL_TX_BITS                            1
#define TX0_ANATXACONTROL1_REFL_TX_SHIFT                           12

/* Tx0 :: anaTxAControl1 :: refh_tx [11:11] */
#define TX0_ANATXACONTROL1_REFH_TX_MASK                            0x0800
#define TX0_ANATXACONTROL1_REFH_TX_ALIGN                           0
#define TX0_ANATXACONTROL1_REFH_TX_BITS                            1
#define TX0_ANATXACONTROL1_REFH_TX_SHIFT                           11

/* Tx0 :: anaTxAControl1 :: newbias_en [10:10] */
#define TX0_ANATXACONTROL1_NEWBIAS_EN_MASK                         0x0400
#define TX0_ANATXACONTROL1_NEWBIAS_EN_ALIGN                        0
#define TX0_ANATXACONTROL1_NEWBIAS_EN_BITS                         1
#define TX0_ANATXACONTROL1_NEWBIAS_EN_SHIFT                        10

/* Tx0 :: anaTxAControl1 :: drivermode [09:09] */
#define TX0_ANATXACONTROL1_DRIVERMODE_MASK                         0x0200
#define TX0_ANATXACONTROL1_DRIVERMODE_ALIGN                        0
#define TX0_ANATXACONTROL1_DRIVERMODE_BITS                         1
#define TX0_ANATXACONTROL1_DRIVERMODE_SHIFT                        9

/* Tx0 :: anaTxAControl1 :: vddr_bgb [08:08] */
#define TX0_ANATXACONTROL1_VDDR_BGB_MASK                           0x0100
#define TX0_ANATXACONTROL1_VDDR_BGB_ALIGN                          0
#define TX0_ANATXACONTROL1_VDDR_BGB_BITS                           1
#define TX0_ANATXACONTROL1_VDDR_BGB_SHIFT                          8

/* Tx0 :: anaTxAControl1 :: ticksel [07:06] */
#define TX0_ANATXACONTROL1_TICKSEL_MASK                            0x00c0
#define TX0_ANATXACONTROL1_TICKSEL_ALIGN                           0
#define TX0_ANATXACONTROL1_TICKSEL_BITS                            2
#define TX0_ANATXACONTROL1_TICKSEL_SHIFT                           6

/* Tx0 :: anaTxAControl1 :: driver_vcm [05:04] */
#define TX0_ANATXACONTROL1_DRIVER_VCM_MASK                         0x0030
#define TX0_ANATXACONTROL1_DRIVER_VCM_ALIGN                        0
#define TX0_ANATXACONTROL1_DRIVER_VCM_BITS                         2
#define TX0_ANATXACONTROL1_DRIVER_VCM_SHIFT                        4

/* Tx0 :: anaTxAControl1 :: tx_sel_halfrate [03:03] */
#define TX0_ANATXACONTROL1_TX_SEL_HALFRATE_MASK                    0x0008
#define TX0_ANATXACONTROL1_TX_SEL_HALFRATE_ALIGN                   0
#define TX0_ANATXACONTROL1_TX_SEL_HALFRATE_BITS                    1
#define TX0_ANATXACONTROL1_TX_SEL_HALFRATE_SHIFT                   3

/* Tx0 :: anaTxAControl1 :: ifullspd [02:00] */
#define TX0_ANATXACONTROL1_IFULLSPD_MASK                           0x0007
#define TX0_ANATXACONTROL1_IFULLSPD_ALIGN                          0
#define TX0_ANATXACONTROL1_IFULLSPD_BITS                           3
#define TX0_ANATXACONTROL1_IFULLSPD_SHIFT                          0


/****************************************************************************
 * Tx0 :: anaTxAControl2
 ***************************************************************************/
/* Tx0 :: anaTxAControl2 :: icbuf1t [15:14] */
#define TX0_ANATXACONTROL2_ICBUF1T_MASK                            0xc000
#define TX0_ANATXACONTROL2_ICBUF1T_ALIGN                           0
#define TX0_ANATXACONTROL2_ICBUF1T_BITS                            2
#define TX0_ANATXACONTROL2_ICBUF1T_SHIFT                           14

/* Tx0 :: anaTxAControl2 :: icbuf2t [13:11] */
#define TX0_ANATXACONTROL2_ICBUF2T_MASK                            0x3800
#define TX0_ANATXACONTROL2_ICBUF2T_ALIGN                           0
#define TX0_ANATXACONTROL2_ICBUF2T_BITS                            3
#define TX0_ANATXACONTROL2_ICBUF2T_SHIFT                           11

/* Tx0 :: anaTxAControl2 :: imin_predrv [10:10] */
#define TX0_ANATXACONTROL2_IMIN_PREDRV_MASK                        0x0400
#define TX0_ANATXACONTROL2_IMIN_PREDRV_ALIGN                       0
#define TX0_ANATXACONTROL2_IMIN_PREDRV_BITS                        1
#define TX0_ANATXACONTROL2_IMIN_PREDRV_SHIFT                       10

/* Tx0 :: anaTxAControl2 :: imax_predrv [09:09] */
#define TX0_ANATXACONTROL2_IMAX_PREDRV_MASK                        0x0200
#define TX0_ANATXACONTROL2_IMAX_PREDRV_ALIGN                       0
#define TX0_ANATXACONTROL2_IMAX_PREDRV_BITS                        1
#define TX0_ANATXACONTROL2_IMAX_PREDRV_SHIFT                       9

/* Tx0 :: anaTxAControl2 :: imode_predrv [08:08] */
#define TX0_ANATXACONTROL2_IMODE_PREDRV_MASK                       0x0100
#define TX0_ANATXACONTROL2_IMODE_PREDRV_ALIGN                      0
#define TX0_ANATXACONTROL2_IMODE_PREDRV_BITS                       1
#define TX0_ANATXACONTROL2_IMODE_PREDRV_SHIFT                      8

/* Tx0 :: anaTxAControl2 :: i21mux [07:05] */
#define TX0_ANATXACONTROL2_I21MUX_MASK                             0x00e0
#define TX0_ANATXACONTROL2_I21MUX_ALIGN                            0
#define TX0_ANATXACONTROL2_I21MUX_BITS                             3
#define TX0_ANATXACONTROL2_I21MUX_SHIFT                            5

/* Tx0 :: anaTxAControl2 :: imin_drvr [04:04] */
#define TX0_ANATXACONTROL2_IMIN_DRVR_MASK                          0x0010
#define TX0_ANATXACONTROL2_IMIN_DRVR_ALIGN                         0
#define TX0_ANATXACONTROL2_IMIN_DRVR_BITS                          1
#define TX0_ANATXACONTROL2_IMIN_DRVR_SHIFT                         4

/* Tx0 :: anaTxAControl2 :: imax_drvr [03:03] */
#define TX0_ANATXACONTROL2_IMAX_DRVR_MASK                          0x0008
#define TX0_ANATXACONTROL2_IMAX_DRVR_ALIGN                         0
#define TX0_ANATXACONTROL2_IMAX_DRVR_BITS                          1
#define TX0_ANATXACONTROL2_IMAX_DRVR_SHIFT                         3

/* Tx0 :: anaTxAControl2 :: imode_drvr [02:02] */
#define TX0_ANATXACONTROL2_IMODE_DRVR_MASK                         0x0004
#define TX0_ANATXACONTROL2_IMODE_DRVR_ALIGN                        0
#define TX0_ANATXACONTROL2_IMODE_DRVR_BITS                         1
#define TX0_ANATXACONTROL2_IMODE_DRVR_SHIFT                        2

/* Tx0 :: anaTxAControl2 :: reserved0 [01:00] */
#define TX0_ANATXACONTROL2_RESERVED0_MASK                          0x0003
#define TX0_ANATXACONTROL2_RESERVED0_ALIGN                         0
#define TX0_ANATXACONTROL2_RESERVED0_BITS                          2
#define TX0_ANATXACONTROL2_RESERVED0_SHIFT                         0


/****************************************************************************
 * Tx0 :: Tx_OS_Driver
 ***************************************************************************/
/* Tx0 :: Tx_OS_Driver :: preemphasis_post [15:12] */
#define TX0_TX_OS_DRIVER_PREEMPHASIS_POST_MASK                     0xf000
#define TX0_TX_OS_DRIVER_PREEMPHASIS_POST_ALIGN                    0
#define TX0_TX_OS_DRIVER_PREEMPHASIS_POST_BITS                     4
#define TX0_TX_OS_DRIVER_PREEMPHASIS_POST_SHIFT                    12

/* Tx0 :: Tx_OS_Driver :: Idriver [11:08] */
#define TX0_TX_OS_DRIVER_IDRIVER_MASK                              0x0f00
#define TX0_TX_OS_DRIVER_IDRIVER_ALIGN                             0
#define TX0_TX_OS_DRIVER_IDRIVER_BITS                              4
#define TX0_TX_OS_DRIVER_IDRIVER_SHIFT                             8

/* Tx0 :: Tx_OS_Driver :: Ipredriver [07:04] */
#define TX0_TX_OS_DRIVER_IPREDRIVER_MASK                           0x00f0
#define TX0_TX_OS_DRIVER_IPREDRIVER_ALIGN                          0
#define TX0_TX_OS_DRIVER_IPREDRIVER_BITS                           4
#define TX0_TX_OS_DRIVER_IPREDRIVER_SHIFT                          4

/* Tx0 :: Tx_OS_Driver :: preemphasis_pre [03:01] */
#define TX0_TX_OS_DRIVER_PREEMPHASIS_PRE_MASK                      0x000e
#define TX0_TX_OS_DRIVER_PREEMPHASIS_PRE_ALIGN                     0
#define TX0_TX_OS_DRIVER_PREEMPHASIS_PRE_BITS                      3
#define TX0_TX_OS_DRIVER_PREEMPHASIS_PRE_SHIFT                     1

/* Tx0 :: Tx_OS_Driver :: icbuf1t0 [00:00] */
#define TX0_TX_OS_DRIVER_ICBUF1T0_MASK                             0x0001
#define TX0_TX_OS_DRIVER_ICBUF1T0_ALIGN                            0
#define TX0_TX_OS_DRIVER_ICBUF1T0_BITS                             1
#define TX0_TX_OS_DRIVER_ICBUF1T0_SHIFT                            0


/****************************************************************************
 * Tx0 :: Tx_BR_Driver
 ***************************************************************************/
/* Tx0 :: Tx_BR_Driver :: preemphasis_post [15:12] */
#define TX0_TX_BR_DRIVER_PREEMPHASIS_POST_MASK                     0xf000
#define TX0_TX_BR_DRIVER_PREEMPHASIS_POST_ALIGN                    0
#define TX0_TX_BR_DRIVER_PREEMPHASIS_POST_BITS                     4
#define TX0_TX_BR_DRIVER_PREEMPHASIS_POST_SHIFT                    12

/* Tx0 :: Tx_BR_Driver :: Idriver [11:08] */
#define TX0_TX_BR_DRIVER_IDRIVER_MASK                              0x0f00
#define TX0_TX_BR_DRIVER_IDRIVER_ALIGN                             0
#define TX0_TX_BR_DRIVER_IDRIVER_BITS                              4
#define TX0_TX_BR_DRIVER_IDRIVER_SHIFT                             8

/* Tx0 :: Tx_BR_Driver :: Ipredriver [07:04] */
#define TX0_TX_BR_DRIVER_IPREDRIVER_MASK                           0x00f0
#define TX0_TX_BR_DRIVER_IPREDRIVER_ALIGN                          0
#define TX0_TX_BR_DRIVER_IPREDRIVER_BITS                           4
#define TX0_TX_BR_DRIVER_IPREDRIVER_SHIFT                          4

/* Tx0 :: Tx_BR_Driver :: preemphasis_pre [03:01] */
#define TX0_TX_BR_DRIVER_PREEMPHASIS_PRE_MASK                      0x000e
#define TX0_TX_BR_DRIVER_PREEMPHASIS_PRE_ALIGN                     0
#define TX0_TX_BR_DRIVER_PREEMPHASIS_PRE_BITS                      3
#define TX0_TX_BR_DRIVER_PREEMPHASIS_PRE_SHIFT                     1

/* Tx0 :: Tx_BR_Driver :: icbuf1t0 [00:00] */
#define TX0_TX_BR_DRIVER_ICBUF1T0_MASK                             0x0001
#define TX0_TX_BR_DRIVER_ICBUF1T0_ALIGN                            0
#define TX0_TX_BR_DRIVER_ICBUF1T0_BITS                             1
#define TX0_TX_BR_DRIVER_ICBUF1T0_SHIFT                            0


/****************************************************************************
 * Hypercore_USER_Tx1
 ***************************************************************************/
/****************************************************************************
 * Tx1 :: anaTxAStatus0
 ***************************************************************************/
/* Tx1 :: anaTxAStatus0 :: reserved0 [15:07] */
#define TX1_ANATXASTATUS0_RESERVED0_MASK                           0xff80
#define TX1_ANATXASTATUS0_RESERVED0_ALIGN                          0
#define TX1_ANATXASTATUS0_RESERVED0_BITS                           9
#define TX1_ANATXASTATUS0_RESERVED0_SHIFT                          7

/* Tx1 :: anaTxAStatus0 :: txdisable_ln [06:06] */
#define TX1_ANATXASTATUS0_TXDISABLE_LN_MASK                        0x0040
#define TX1_ANATXASTATUS0_TXDISABLE_LN_ALIGN                       0
#define TX1_ANATXASTATUS0_TXDISABLE_LN_BITS                        1
#define TX1_ANATXASTATUS0_TXDISABLE_LN_SHIFT                       6

/* Tx1 :: anaTxAStatus0 :: txferr_stky [05:05] */
#define TX1_ANATXASTATUS0_TXFERR_STKY_MASK                         0x0020
#define TX1_ANATXASTATUS0_TXFERR_STKY_ALIGN                        0
#define TX1_ANATXASTATUS0_TXFERR_STKY_BITS                         1
#define TX1_ANATXASTATUS0_TXFERR_STKY_SHIFT                        5

/* Tx1 :: anaTxAStatus0 :: tbi_mode [04:04] */
#define TX1_ANATXASTATUS0_TBI_MODE_MASK                            0x0010
#define TX1_ANATXASTATUS0_TBI_MODE_ALIGN                           0
#define TX1_ANATXASTATUS0_TBI_MODE_BITS                            1
#define TX1_ANATXASTATUS0_TBI_MODE_SHIFT                           4

/* Tx1 :: anaTxAStatus0 :: tx_reset [03:03] */
#define TX1_ANATXASTATUS0_TX_RESET_MASK                            0x0008
#define TX1_ANATXASTATUS0_TX_RESET_ALIGN                           0
#define TX1_ANATXASTATUS0_TX_RESET_BITS                            1
#define TX1_ANATXASTATUS0_TX_RESET_SHIFT                           3

/* Tx1 :: anaTxAStatus0 :: tx_pwrdn [02:02] */
#define TX1_ANATXASTATUS0_TX_PWRDN_MASK                            0x0004
#define TX1_ANATXASTATUS0_TX_PWRDN_ALIGN                           0
#define TX1_ANATXASTATUS0_TX_PWRDN_BITS                            1
#define TX1_ANATXASTATUS0_TX_PWRDN_SHIFT                           2

/* Tx1 :: anaTxAStatus0 :: rltxferr_stky [01:01] */
#define TX1_ANATXASTATUS0_RLTXFERR_STKY_MASK                       0x0002
#define TX1_ANATXASTATUS0_RLTXFERR_STKY_ALIGN                      0
#define TX1_ANATXASTATUS0_RLTXFERR_STKY_BITS                       1
#define TX1_ANATXASTATUS0_RLTXFERR_STKY_SHIFT                      1

/* Tx1 :: anaTxAStatus0 :: txpll_lock [00:00] */
#define TX1_ANATXASTATUS0_TXPLL_LOCK_MASK                          0x0001
#define TX1_ANATXASTATUS0_TXPLL_LOCK_ALIGN                         0
#define TX1_ANATXASTATUS0_TXPLL_LOCK_BITS                          1
#define TX1_ANATXASTATUS0_TXPLL_LOCK_SHIFT                         0


/****************************************************************************
 * Tx1 :: anaTxAControl0
 ***************************************************************************/
/* Tx1 :: anaTxAControl0 :: reserved0 [15:15] */
#define TX1_ANATXACONTROL0_RESERVED0_MASK                          0x8000
#define TX1_ANATXACONTROL0_RESERVED0_ALIGN                         0
#define TX1_ANATXACONTROL0_RESERVED0_BITS                          1
#define TX1_ANATXACONTROL0_RESERVED0_SHIFT                         15

/* Tx1 :: anaTxAControl0 :: force_txclk [14:14] */
#define TX1_ANATXACONTROL0_FORCE_TXCLK_MASK                        0x4000
#define TX1_ANATXACONTROL0_FORCE_TXCLK_ALIGN                       0
#define TX1_ANATXACONTROL0_FORCE_TXCLK_BITS                        1
#define TX1_ANATXACONTROL0_FORCE_TXCLK_SHIFT                       14

/* Tx1 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */
#define TX1_ANATXACONTROL0_TX1G_FIFO_RST_MASK                      0x2000
#define TX1_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN                     0
#define TX1_ANATXACONTROL0_TX1G_FIFO_RST_BITS                      1
#define TX1_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT                     13

/* Tx1 :: anaTxAControl0 :: gloopOutEn [12:12] */
#define TX1_ANATXACONTROL0_GLOOPOUTEN_MASK                         0x1000
#define TX1_ANATXACONTROL0_GLOOPOUTEN_ALIGN                        0
#define TX1_ANATXACONTROL0_GLOOPOUTEN_BITS                         1
#define TX1_ANATXACONTROL0_GLOOPOUTEN_SHIFT                        12

/* Tx1 :: anaTxAControl0 :: reserved1 [11:09] */
#define TX1_ANATXACONTROL0_RESERVED1_MASK                          0x0e00
#define TX1_ANATXACONTROL0_RESERVED1_ALIGN                         0
#define TX1_ANATXACONTROL0_RESERVED1_BITS                          3
#define TX1_ANATXACONTROL0_RESERVED1_SHIFT                         9

/* Tx1 :: anaTxAControl0 :: prbs_en [08:08] */
#define TX1_ANATXACONTROL0_PRBS_EN_MASK                            0x0100
#define TX1_ANATXACONTROL0_PRBS_EN_ALIGN                           0
#define TX1_ANATXACONTROL0_PRBS_EN_BITS                            1
#define TX1_ANATXACONTROL0_PRBS_EN_SHIFT                           8

/* Tx1 :: anaTxAControl0 :: pckt_en [07:07] */
#define TX1_ANATXACONTROL0_PCKT_EN_MASK                            0x0080
#define TX1_ANATXACONTROL0_PCKT_EN_ALIGN                           0
#define TX1_ANATXACONTROL0_PCKT_EN_BITS                            1
#define TX1_ANATXACONTROL0_PCKT_EN_SHIFT                           7

/* Tx1 :: anaTxAControl0 :: pckt_strt [06:06] */
#define TX1_ANATXACONTROL0_PCKT_STRT_MASK                          0x0040
#define TX1_ANATXACONTROL0_PCKT_STRT_ALIGN                         0
#define TX1_ANATXACONTROL0_PCKT_STRT_BITS                          1
#define TX1_ANATXACONTROL0_PCKT_STRT_SHIFT                         6

/* Tx1 :: anaTxAControl0 :: txpol_flip [05:05] */
#define TX1_ANATXACONTROL0_TXPOL_FLIP_MASK                         0x0020
#define TX1_ANATXACONTROL0_TXPOL_FLIP_ALIGN                        0
#define TX1_ANATXACONTROL0_TXPOL_FLIP_BITS                         1
#define TX1_ANATXACONTROL0_TXPOL_FLIP_SHIFT                        5

/* Tx1 :: anaTxAControl0 :: rtbi_flip [04:04] */
#define TX1_ANATXACONTROL0_RTBI_FLIP_MASK                          0x0010
#define TX1_ANATXACONTROL0_RTBI_FLIP_ALIGN                         0
#define TX1_ANATXACONTROL0_RTBI_FLIP_BITS                          1
#define TX1_ANATXACONTROL0_RTBI_FLIP_SHIFT                         4

/* Tx1 :: anaTxAControl0 :: eden_r [03:03] */
#define TX1_ANATXACONTROL0_EDEN_R_MASK                             0x0008
#define TX1_ANATXACONTROL0_EDEN_R_ALIGN                            0
#define TX1_ANATXACONTROL0_EDEN_R_BITS                             1
#define TX1_ANATXACONTROL0_EDEN_R_SHIFT                            3

/* Tx1 :: anaTxAControl0 :: eden_force_r [02:02] */
#define TX1_ANATXACONTROL0_EDEN_FORCE_R_MASK                       0x0004
#define TX1_ANATXACONTROL0_EDEN_FORCE_R_ALIGN                      0
#define TX1_ANATXACONTROL0_EDEN_FORCE_R_BITS                       1
#define TX1_ANATXACONTROL0_EDEN_FORCE_R_SHIFT                      2

/* Tx1 :: anaTxAControl0 :: txpat_en [01:01] */
#define TX1_ANATXACONTROL0_TXPAT_EN_MASK                           0x0002
#define TX1_ANATXACONTROL0_TXPAT_EN_ALIGN                          0
#define TX1_ANATXACONTROL0_TXPAT_EN_BITS                           1
#define TX1_ANATXACONTROL0_TXPAT_EN_SHIFT                          1

/* Tx1 :: anaTxAControl0 :: tx_mdata_en [00:00] */
#define TX1_ANATXACONTROL0_TX_MDATA_EN_MASK                        0x0001
#define TX1_ANATXACONTROL0_TX_MDATA_EN_ALIGN                       0
#define TX1_ANATXACONTROL0_TX_MDATA_EN_BITS                        1
#define TX1_ANATXACONTROL0_TX_MDATA_EN_SHIFT                       0


/****************************************************************************
 * Tx1 :: anaTxmdata0
 ***************************************************************************/
/* Tx1 :: anaTxmdata0 :: txTestMuxSel [15:13] */
#define TX1_ANATXMDATA0_TXTESTMUXSEL_MASK                          0xe000
#define TX1_ANATXMDATA0_TXTESTMUXSEL_ALIGN                         0
#define TX1_ANATXMDATA0_TXTESTMUXSEL_BITS                          3
#define TX1_ANATXMDATA0_TXTESTMUXSEL_SHIFT                         13

/* Tx1 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */
#define TX1_ANATXMDATA0_RLFIFO_TSTSEL_MASK                         0x1c00
#define TX1_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN                        0
#define TX1_ANATXMDATA0_RLFIFO_TSTSEL_BITS                         3
#define TX1_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT                        10

/* Tx1 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */
#define TX1_ANATXMDATA0_TXMDIOTSTDATAL_MASK                        0x03ff
#define TX1_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN                       0
#define TX1_ANATXMDATA0_TXMDIOTSTDATAL_BITS                        10
#define TX1_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT                       0


/****************************************************************************
 * Tx1 :: anaTxmdata1
 ***************************************************************************/
/* Tx1 :: anaTxmdata1 :: reserved0 [15:10] */
#define TX1_ANATXMDATA1_RESERVED0_MASK                             0xfc00
#define TX1_ANATXMDATA1_RESERVED0_ALIGN                            0
#define TX1_ANATXMDATA1_RESERVED0_BITS                             6
#define TX1_ANATXMDATA1_RESERVED0_SHIFT                            10

/* Tx1 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */
#define TX1_ANATXMDATA1_TXMDIOTSTDATAH_MASK                        0x03ff
#define TX1_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN                       0
#define TX1_ANATXMDATA1_TXMDIOTSTDATAH_BITS                        10
#define TX1_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT                       0


/****************************************************************************
 * Tx1 :: anaTxAStatus1
 ***************************************************************************/
/* Tx1 :: anaTxAStatus1 :: tx_id [15:14] */
#define TX1_ANATXASTATUS1_TX_ID_MASK                               0xc000
#define TX1_ANATXASTATUS1_TX_ID_ALIGN                              0
#define TX1_ANATXASTATUS1_TX_ID_BITS                               2
#define TX1_ANATXASTATUS1_TX_ID_SHIFT                              14

/* Tx1 :: anaTxAStatus1 :: reserved0 [13:00] */
#define TX1_ANATXASTATUS1_RESERVED0_MASK                           0x3fff
#define TX1_ANATXASTATUS1_RESERVED0_ALIGN                          0
#define TX1_ANATXASTATUS1_RESERVED0_BITS                           14
#define TX1_ANATXASTATUS1_RESERVED0_SHIFT                          0


/****************************************************************************
 * Tx1 :: anaTxAControl1
 ***************************************************************************/
/* Tx1 :: anaTxAControl1 :: id2c [15:13] */
#define TX1_ANATXACONTROL1_ID2C_MASK                               0xe000
#define TX1_ANATXACONTROL1_ID2C_ALIGN                              0
#define TX1_ANATXACONTROL1_ID2C_BITS                               3
#define TX1_ANATXACONTROL1_ID2C_SHIFT                              13

/* Tx1 :: anaTxAControl1 :: refl_tx [12:12] */
#define TX1_ANATXACONTROL1_REFL_TX_MASK                            0x1000
#define TX1_ANATXACONTROL1_REFL_TX_ALIGN                           0
#define TX1_ANATXACONTROL1_REFL_TX_BITS                            1
#define TX1_ANATXACONTROL1_REFL_TX_SHIFT                           12

/* Tx1 :: anaTxAControl1 :: refh_tx [11:11] */
#define TX1_ANATXACONTROL1_REFH_TX_MASK                            0x0800
#define TX1_ANATXACONTROL1_REFH_TX_ALIGN                           0
#define TX1_ANATXACONTROL1_REFH_TX_BITS                            1
#define TX1_ANATXACONTROL1_REFH_TX_SHIFT                           11

/* Tx1 :: anaTxAControl1 :: newbias_en [10:10] */
#define TX1_ANATXACONTROL1_NEWBIAS_EN_MASK                         0x0400
#define TX1_ANATXACONTROL1_NEWBIAS_EN_ALIGN                        0
#define TX1_ANATXACONTROL1_NEWBIAS_EN_BITS                         1
#define TX1_ANATXACONTROL1_NEWBIAS_EN_SHIFT                        10

/* Tx1 :: anaTxAControl1 :: drivermode [09:09] */
#define TX1_ANATXACONTROL1_DRIVERMODE_MASK                         0x0200
#define TX1_ANATXACONTROL1_DRIVERMODE_ALIGN                        0
#define TX1_ANATXACONTROL1_DRIVERMODE_BITS                         1
#define TX1_ANATXACONTROL1_DRIVERMODE_SHIFT                        9

/* Tx1 :: anaTxAControl1 :: vddr_bgb [08:08] */
#define TX1_ANATXACONTROL1_VDDR_BGB_MASK                           0x0100
#define TX1_ANATXACONTROL1_VDDR_BGB_ALIGN                          0
#define TX1_ANATXACONTROL1_VDDR_BGB_BITS                           1
#define TX1_ANATXACONTROL1_VDDR_BGB_SHIFT                          8

/* Tx1 :: anaTxAControl1 :: ticksel [07:06] */
#define TX1_ANATXACONTROL1_TICKSEL_MASK                            0x00c0
#define TX1_ANATXACONTROL1_TICKSEL_ALIGN                           0
#define TX1_ANATXACONTROL1_TICKSEL_BITS                            2
#define TX1_ANATXACONTROL1_TICKSEL_SHIFT                           6

/* Tx1 :: anaTxAControl1 :: driver_vcm [05:04] */
#define TX1_ANATXACONTROL1_DRIVER_VCM_MASK                         0x0030
#define TX1_ANATXACONTROL1_DRIVER_VCM_ALIGN                        0
#define TX1_ANATXACONTROL1_DRIVER_VCM_BITS                         2
#define TX1_ANATXACONTROL1_DRIVER_VCM_SHIFT                        4

/* Tx1 :: anaTxAControl1 :: tx_sel_halfrate [03:03] */
#define TX1_ANATXACONTROL1_TX_SEL_HALFRATE_MASK                    0x0008
#define TX1_ANATXACONTROL1_TX_SEL_HALFRATE_ALIGN                   0
#define TX1_ANATXACONTROL1_TX_SEL_HALFRATE_BITS                    1
#define TX1_ANATXACONTROL1_TX_SEL_HALFRATE_SHIFT                   3

/* Tx1 :: anaTxAControl1 :: ifullspd [02:00] */
#define TX1_ANATXACONTROL1_IFULLSPD_MASK                           0x0007
#define TX1_ANATXACONTROL1_IFULLSPD_ALIGN                          0
#define TX1_ANATXACONTROL1_IFULLSPD_BITS                           3
#define TX1_ANATXACONTROL1_IFULLSPD_SHIFT                          0


/****************************************************************************
 * Tx1 :: anaTxAControl2
 ***************************************************************************/
/* Tx1 :: anaTxAControl2 :: icbuf1t [15:14] */
#define TX1_ANATXACONTROL2_ICBUF1T_MASK                            0xc000
#define TX1_ANATXACONTROL2_ICBUF1T_ALIGN                           0
#define TX1_ANATXACONTROL2_ICBUF1T_BITS                            2
#define TX1_ANATXACONTROL2_ICBUF1T_SHIFT                           14

/* Tx1 :: anaTxAControl2 :: icbuf2t [13:11] */
#define TX1_ANATXACONTROL2_ICBUF2T_MASK                            0x3800
#define TX1_ANATXACONTROL2_ICBUF2T_ALIGN                           0
#define TX1_ANATXACONTROL2_ICBUF2T_BITS                            3
#define TX1_ANATXACONTROL2_ICBUF2T_SHIFT                           11

/* Tx1 :: anaTxAControl2 :: imin_predrv [10:10] */
#define TX1_ANATXACONTROL2_IMIN_PREDRV_MASK                        0x0400
#define TX1_ANATXACONTROL2_IMIN_PREDRV_ALIGN                       0
#define TX1_ANATXACONTROL2_IMIN_PREDRV_BITS                        1
#define TX1_ANATXACONTROL2_IMIN_PREDRV_SHIFT                       10

/* Tx1 :: anaTxAControl2 :: imax_predrv [09:09] */
#define TX1_ANATXACONTROL2_IMAX_PREDRV_MASK                        0x0200
#define TX1_ANATXACONTROL2_IMAX_PREDRV_ALIGN                       0
#define TX1_ANATXACONTROL2_IMAX_PREDRV_BITS                        1
#define TX1_ANATXACONTROL2_IMAX_PREDRV_SHIFT                       9

/* Tx1 :: anaTxAControl2 :: imode_predrv [08:08] */
#define TX1_ANATXACONTROL2_IMODE_PREDRV_MASK                       0x0100
#define TX1_ANATXACONTROL2_IMODE_PREDRV_ALIGN                      0
#define TX1_ANATXACONTROL2_IMODE_PREDRV_BITS                       1
#define TX1_ANATXACONTROL2_IMODE_PREDRV_SHIFT                      8

/* Tx1 :: anaTxAControl2 :: i21mux [07:05] */
#define TX1_ANATXACONTROL2_I21MUX_MASK                             0x00e0
#define TX1_ANATXACONTROL2_I21MUX_ALIGN                            0
#define TX1_ANATXACONTROL2_I21MUX_BITS                             3
#define TX1_ANATXACONTROL2_I21MUX_SHIFT                            5

/* Tx1 :: anaTxAControl2 :: imin_drvr [04:04] */
#define TX1_ANATXACONTROL2_IMIN_DRVR_MASK                          0x0010
#define TX1_ANATXACONTROL2_IMIN_DRVR_ALIGN                         0
#define TX1_ANATXACONTROL2_IMIN_DRVR_BITS                          1
#define TX1_ANATXACONTROL2_IMIN_DRVR_SHIFT                         4

/* Tx1 :: anaTxAControl2 :: imax_drvr [03:03] */
#define TX1_ANATXACONTROL2_IMAX_DRVR_MASK                          0x0008
#define TX1_ANATXACONTROL2_IMAX_DRVR_ALIGN                         0
#define TX1_ANATXACONTROL2_IMAX_DRVR_BITS                          1
#define TX1_ANATXACONTROL2_IMAX_DRVR_SHIFT                         3

/* Tx1 :: anaTxAControl2 :: imode_drvr [02:02] */
#define TX1_ANATXACONTROL2_IMODE_DRVR_MASK                         0x0004
#define TX1_ANATXACONTROL2_IMODE_DRVR_ALIGN                        0
#define TX1_ANATXACONTROL2_IMODE_DRVR_BITS                         1
#define TX1_ANATXACONTROL2_IMODE_DRVR_SHIFT                        2

/* Tx1 :: anaTxAControl2 :: reserved0 [01:00] */
#define TX1_ANATXACONTROL2_RESERVED0_MASK                          0x0003
#define TX1_ANATXACONTROL2_RESERVED0_ALIGN                         0
#define TX1_ANATXACONTROL2_RESERVED0_BITS                          2
#define TX1_ANATXACONTROL2_RESERVED0_SHIFT                         0


/****************************************************************************
 * Tx1 :: Tx_OS_Driver
 ***************************************************************************/
/* Tx1 :: Tx_OS_Driver :: preemphasis_post [15:12] */
#define TX1_TX_OS_DRIVER_PREEMPHASIS_POST_MASK                     0xf000
#define TX1_TX_OS_DRIVER_PREEMPHASIS_POST_ALIGN                    0
#define TX1_TX_OS_DRIVER_PREEMPHASIS_POST_BITS                     4
#define TX1_TX_OS_DRIVER_PREEMPHASIS_POST_SHIFT                    12

/* Tx1 :: Tx_OS_Driver :: Idriver [11:08] */
#define TX1_TX_OS_DRIVER_IDRIVER_MASK                              0x0f00
#define TX1_TX_OS_DRIVER_IDRIVER_ALIGN                             0
#define TX1_TX_OS_DRIVER_IDRIVER_BITS                              4
#define TX1_TX_OS_DRIVER_IDRIVER_SHIFT                             8

/* Tx1 :: Tx_OS_Driver :: Ipredriver [07:04] */
#define TX1_TX_OS_DRIVER_IPREDRIVER_MASK                           0x00f0
#define TX1_TX_OS_DRIVER_IPREDRIVER_ALIGN                          0
#define TX1_TX_OS_DRIVER_IPREDRIVER_BITS                           4
#define TX1_TX_OS_DRIVER_IPREDRIVER_SHIFT                          4

/* Tx1 :: Tx_OS_Driver :: preemphasis_pre [03:01] */
#define TX1_TX_OS_DRIVER_PREEMPHASIS_PRE_MASK                      0x000e
#define TX1_TX_OS_DRIVER_PREEMPHASIS_PRE_ALIGN                     0
#define TX1_TX_OS_DRIVER_PREEMPHASIS_PRE_BITS                      3
#define TX1_TX_OS_DRIVER_PREEMPHASIS_PRE_SHIFT                     1

/* Tx1 :: Tx_OS_Driver :: icbuf1t0 [00:00] */
#define TX1_TX_OS_DRIVER_ICBUF1T0_MASK                             0x0001
#define TX1_TX_OS_DRIVER_ICBUF1T0_ALIGN                            0
#define TX1_TX_OS_DRIVER_ICBUF1T0_BITS                             1
#define TX1_TX_OS_DRIVER_ICBUF1T0_SHIFT                            0


/****************************************************************************
 * Tx1 :: Tx_BR_Driver
 ***************************************************************************/
/* Tx1 :: Tx_BR_Driver :: preemphasis_post [15:12] */
#define TX1_TX_BR_DRIVER_PREEMPHASIS_POST_MASK                     0xf000
#define TX1_TX_BR_DRIVER_PREEMPHASIS_POST_ALIGN                    0
#define TX1_TX_BR_DRIVER_PREEMPHASIS_POST_BITS                     4
#define TX1_TX_BR_DRIVER_PREEMPHASIS_POST_SHIFT                    12

/* Tx1 :: Tx_BR_Driver :: Idriver [11:08] */
#define TX1_TX_BR_DRIVER_IDRIVER_MASK                              0x0f00
#define TX1_TX_BR_DRIVER_IDRIVER_ALIGN                             0
#define TX1_TX_BR_DRIVER_IDRIVER_BITS                              4
#define TX1_TX_BR_DRIVER_IDRIVER_SHIFT                             8

/* Tx1 :: Tx_BR_Driver :: Ipredriver [07:04] */
#define TX1_TX_BR_DRIVER_IPREDRIVER_MASK                           0x00f0
#define TX1_TX_BR_DRIVER_IPREDRIVER_ALIGN                          0
#define TX1_TX_BR_DRIVER_IPREDRIVER_BITS                           4
#define TX1_TX_BR_DRIVER_IPREDRIVER_SHIFT                          4

/* Tx1 :: Tx_BR_Driver :: preemphasis_pre [03:01] */
#define TX1_TX_BR_DRIVER_PREEMPHASIS_PRE_MASK                      0x000e
#define TX1_TX_BR_DRIVER_PREEMPHASIS_PRE_ALIGN                     0
#define TX1_TX_BR_DRIVER_PREEMPHASIS_PRE_BITS                      3
#define TX1_TX_BR_DRIVER_PREEMPHASIS_PRE_SHIFT                     1

/* Tx1 :: Tx_BR_Driver :: icbuf1t0 [00:00] */
#define TX1_TX_BR_DRIVER_ICBUF1T0_MASK                             0x0001
#define TX1_TX_BR_DRIVER_ICBUF1T0_ALIGN                            0
#define TX1_TX_BR_DRIVER_ICBUF1T0_BITS                             1
#define TX1_TX_BR_DRIVER_ICBUF1T0_SHIFT                            0


/****************************************************************************
 * Hypercore_USER_Tx2
 ***************************************************************************/
/****************************************************************************
 * Tx2 :: anaTxAStatus0
 ***************************************************************************/
/* Tx2 :: anaTxAStatus0 :: reserved0 [15:07] */
#define TX2_ANATXASTATUS0_RESERVED0_MASK                           0xff80
#define TX2_ANATXASTATUS0_RESERVED0_ALIGN                          0
#define TX2_ANATXASTATUS0_RESERVED0_BITS                           9
#define TX2_ANATXASTATUS0_RESERVED0_SHIFT                          7

/* Tx2 :: anaTxAStatus0 :: txdisable_ln [06:06] */
#define TX2_ANATXASTATUS0_TXDISABLE_LN_MASK                        0x0040
#define TX2_ANATXASTATUS0_TXDISABLE_LN_ALIGN                       0
#define TX2_ANATXASTATUS0_TXDISABLE_LN_BITS                        1
#define TX2_ANATXASTATUS0_TXDISABLE_LN_SHIFT                       6

/* Tx2 :: anaTxAStatus0 :: txferr_stky [05:05] */
#define TX2_ANATXASTATUS0_TXFERR_STKY_MASK                         0x0020
#define TX2_ANATXASTATUS0_TXFERR_STKY_ALIGN                        0
#define TX2_ANATXASTATUS0_TXFERR_STKY_BITS                         1
#define TX2_ANATXASTATUS0_TXFERR_STKY_SHIFT                        5

/* Tx2 :: anaTxAStatus0 :: tbi_mode [04:04] */
#define TX2_ANATXASTATUS0_TBI_MODE_MASK                            0x0010
#define TX2_ANATXASTATUS0_TBI_MODE_ALIGN                           0
#define TX2_ANATXASTATUS0_TBI_MODE_BITS                            1
#define TX2_ANATXASTATUS0_TBI_MODE_SHIFT                           4

/* Tx2 :: anaTxAStatus0 :: tx_reset [03:03] */
#define TX2_ANATXASTATUS0_TX_RESET_MASK                            0x0008
#define TX2_ANATXASTATUS0_TX_RESET_ALIGN                           0
#define TX2_ANATXASTATUS0_TX_RESET_BITS                            1
#define TX2_ANATXASTATUS0_TX_RESET_SHIFT                           3

/* Tx2 :: anaTxAStatus0 :: tx_pwrdn [02:02] */
#define TX2_ANATXASTATUS0_TX_PWRDN_MASK                            0x0004
#define TX2_ANATXASTATUS0_TX_PWRDN_ALIGN                           0
#define TX2_ANATXASTATUS0_TX_PWRDN_BITS                            1
#define TX2_ANATXASTATUS0_TX_PWRDN_SHIFT                           2

/* Tx2 :: anaTxAStatus0 :: rltxferr_stky [01:01] */
#define TX2_ANATXASTATUS0_RLTXFERR_STKY_MASK                       0x0002
#define TX2_ANATXASTATUS0_RLTXFERR_STKY_ALIGN                      0
#define TX2_ANATXASTATUS0_RLTXFERR_STKY_BITS                       1
#define TX2_ANATXASTATUS0_RLTXFERR_STKY_SHIFT                      1

/* Tx2 :: anaTxAStatus0 :: txpll_lock [00:00] */
#define TX2_ANATXASTATUS0_TXPLL_LOCK_MASK                          0x0001
#define TX2_ANATXASTATUS0_TXPLL_LOCK_ALIGN                         0
#define TX2_ANATXASTATUS0_TXPLL_LOCK_BITS                          1
#define TX2_ANATXASTATUS0_TXPLL_LOCK_SHIFT                         0


/****************************************************************************
 * Tx2 :: anaTxAControl0
 ***************************************************************************/
/* Tx2 :: anaTxAControl0 :: reserved0 [15:15] */
#define TX2_ANATXACONTROL0_RESERVED0_MASK                          0x8000
#define TX2_ANATXACONTROL0_RESERVED0_ALIGN                         0
#define TX2_ANATXACONTROL0_RESERVED0_BITS                          1
#define TX2_ANATXACONTROL0_RESERVED0_SHIFT                         15

/* Tx2 :: anaTxAControl0 :: force_txclk [14:14] */
#define TX2_ANATXACONTROL0_FORCE_TXCLK_MASK                        0x4000
#define TX2_ANATXACONTROL0_FORCE_TXCLK_ALIGN                       0
#define TX2_ANATXACONTROL0_FORCE_TXCLK_BITS                        1
#define TX2_ANATXACONTROL0_FORCE_TXCLK_SHIFT                       14

/* Tx2 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */
#define TX2_ANATXACONTROL0_TX1G_FIFO_RST_MASK                      0x2000
#define TX2_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN                     0
#define TX2_ANATXACONTROL0_TX1G_FIFO_RST_BITS                      1
#define TX2_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT                     13

/* Tx2 :: anaTxAControl0 :: gloopOutEn [12:12] */
#define TX2_ANATXACONTROL0_GLOOPOUTEN_MASK                         0x1000
#define TX2_ANATXACONTROL0_GLOOPOUTEN_ALIGN                        0
#define TX2_ANATXACONTROL0_GLOOPOUTEN_BITS                         1
#define TX2_ANATXACONTROL0_GLOOPOUTEN_SHIFT                        12

/* Tx2 :: anaTxAControl0 :: reserved1 [11:09] */
#define TX2_ANATXACONTROL0_RESERVED1_MASK                          0x0e00
#define TX2_ANATXACONTROL0_RESERVED1_ALIGN                         0
#define TX2_ANATXACONTROL0_RESERVED1_BITS                          3
#define TX2_ANATXACONTROL0_RESERVED1_SHIFT                         9

/* Tx2 :: anaTxAControl0 :: prbs_en [08:08] */
#define TX2_ANATXACONTROL0_PRBS_EN_MASK                            0x0100
#define TX2_ANATXACONTROL0_PRBS_EN_ALIGN                           0
#define TX2_ANATXACONTROL0_PRBS_EN_BITS                            1
#define TX2_ANATXACONTROL0_PRBS_EN_SHIFT                           8

/* Tx2 :: anaTxAControl0 :: pckt_en [07:07] */
#define TX2_ANATXACONTROL0_PCKT_EN_MASK                            0x0080
#define TX2_ANATXACONTROL0_PCKT_EN_ALIGN                           0
#define TX2_ANATXACONTROL0_PCKT_EN_BITS                            1
#define TX2_ANATXACONTROL0_PCKT_EN_SHIFT                           7

/* Tx2 :: anaTxAControl0 :: pckt_strt [06:06] */
#define TX2_ANATXACONTROL0_PCKT_STRT_MASK                          0x0040
#define TX2_ANATXACONTROL0_PCKT_STRT_ALIGN                         0
#define TX2_ANATXACONTROL0_PCKT_STRT_BITS                          1
#define TX2_ANATXACONTROL0_PCKT_STRT_SHIFT                         6

/* Tx2 :: anaTxAControl0 :: txpol_flip [05:05] */
#define TX2_ANATXACONTROL0_TXPOL_FLIP_MASK                         0x0020
#define TX2_ANATXACONTROL0_TXPOL_FLIP_ALIGN                        0
#define TX2_ANATXACONTROL0_TXPOL_FLIP_BITS                         1
#define TX2_ANATXACONTROL0_TXPOL_FLIP_SHIFT                        5

/* Tx2 :: anaTxAControl0 :: rtbi_flip [04:04] */
#define TX2_ANATXACONTROL0_RTBI_FLIP_MASK                          0x0010
#define TX2_ANATXACONTROL0_RTBI_FLIP_ALIGN                         0
#define TX2_ANATXACONTROL0_RTBI_FLIP_BITS                          1
#define TX2_ANATXACONTROL0_RTBI_FLIP_SHIFT                         4

/* Tx2 :: anaTxAControl0 :: eden_r [03:03] */
#define TX2_ANATXACONTROL0_EDEN_R_MASK                             0x0008
#define TX2_ANATXACONTROL0_EDEN_R_ALIGN                            0
#define TX2_ANATXACONTROL0_EDEN_R_BITS                             1
#define TX2_ANATXACONTROL0_EDEN_R_SHIFT                            3

/* Tx2 :: anaTxAControl0 :: eden_force_r [02:02] */
#define TX2_ANATXACONTROL0_EDEN_FORCE_R_MASK                       0x0004
#define TX2_ANATXACONTROL0_EDEN_FORCE_R_ALIGN                      0
#define TX2_ANATXACONTROL0_EDEN_FORCE_R_BITS                       1
#define TX2_ANATXACONTROL0_EDEN_FORCE_R_SHIFT                      2

/* Tx2 :: anaTxAControl0 :: txpat_en [01:01] */
#define TX2_ANATXACONTROL0_TXPAT_EN_MASK                           0x0002
#define TX2_ANATXACONTROL0_TXPAT_EN_ALIGN                          0
#define TX2_ANATXACONTROL0_TXPAT_EN_BITS                           1
#define TX2_ANATXACONTROL0_TXPAT_EN_SHIFT                          1

/* Tx2 :: anaTxAControl0 :: tx_mdata_en [00:00] */
#define TX2_ANATXACONTROL0_TX_MDATA_EN_MASK                        0x0001
#define TX2_ANATXACONTROL0_TX_MDATA_EN_ALIGN                       0
#define TX2_ANATXACONTROL0_TX_MDATA_EN_BITS                        1
#define TX2_ANATXACONTROL0_TX_MDATA_EN_SHIFT                       0


/****************************************************************************
 * Tx2 :: anaTxmdata0
 ***************************************************************************/
/* Tx2 :: anaTxmdata0 :: txTestMuxSel [15:13] */
#define TX2_ANATXMDATA0_TXTESTMUXSEL_MASK                          0xe000
#define TX2_ANATXMDATA0_TXTESTMUXSEL_ALIGN                         0
#define TX2_ANATXMDATA0_TXTESTMUXSEL_BITS                          3
#define TX2_ANATXMDATA0_TXTESTMUXSEL_SHIFT                         13

/* Tx2 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */
#define TX2_ANATXMDATA0_RLFIFO_TSTSEL_MASK                         0x1c00
#define TX2_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN                        0
#define TX2_ANATXMDATA0_RLFIFO_TSTSEL_BITS                         3
#define TX2_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT                        10

/* Tx2 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */
#define TX2_ANATXMDATA0_TXMDIOTSTDATAL_MASK                        0x03ff
#define TX2_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN                       0
#define TX2_ANATXMDATA0_TXMDIOTSTDATAL_BITS                        10
#define TX2_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT                       0


/****************************************************************************
 * Tx2 :: anaTxmdata1
 ***************************************************************************/
/* Tx2 :: anaTxmdata1 :: reserved0 [15:10] */
#define TX2_ANATXMDATA1_RESERVED0_MASK                             0xfc00
#define TX2_ANATXMDATA1_RESERVED0_ALIGN                            0
#define TX2_ANATXMDATA1_RESERVED0_BITS                             6
#define TX2_ANATXMDATA1_RESERVED0_SHIFT                            10

/* Tx2 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */
#define TX2_ANATXMDATA1_TXMDIOTSTDATAH_MASK                        0x03ff
#define TX2_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN                       0
#define TX2_ANATXMDATA1_TXMDIOTSTDATAH_BITS                        10
#define TX2_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT                       0


/****************************************************************************
 * Tx2 :: anaTxAStatus1
 ***************************************************************************/
/* Tx2 :: anaTxAStatus1 :: tx_id [15:14] */
#define TX2_ANATXASTATUS1_TX_ID_MASK                               0xc000
#define TX2_ANATXASTATUS1_TX_ID_ALIGN                              0
#define TX2_ANATXASTATUS1_TX_ID_BITS                               2
#define TX2_ANATXASTATUS1_TX_ID_SHIFT                              14

/* Tx2 :: anaTxAStatus1 :: reserved0 [13:00] */
#define TX2_ANATXASTATUS1_RESERVED0_MASK                           0x3fff
#define TX2_ANATXASTATUS1_RESERVED0_ALIGN                          0
#define TX2_ANATXASTATUS1_RESERVED0_BITS                           14
#define TX2_ANATXASTATUS1_RESERVED0_SHIFT                          0


/****************************************************************************
 * Tx2 :: anaTxAControl1
 ***************************************************************************/
/* Tx2 :: anaTxAControl1 :: id2c [15:13] */
#define TX2_ANATXACONTROL1_ID2C_MASK                               0xe000
#define TX2_ANATXACONTROL1_ID2C_ALIGN                              0
#define TX2_ANATXACONTROL1_ID2C_BITS                               3
#define TX2_ANATXACONTROL1_ID2C_SHIFT                              13

/* Tx2 :: anaTxAControl1 :: refl_tx [12:12] */
#define TX2_ANATXACONTROL1_REFL_TX_MASK                            0x1000
#define TX2_ANATXACONTROL1_REFL_TX_ALIGN                           0
#define TX2_ANATXACONTROL1_REFL_TX_BITS                            1
#define TX2_ANATXACONTROL1_REFL_TX_SHIFT                           12

/* Tx2 :: anaTxAControl1 :: refh_tx [11:11] */
#define TX2_ANATXACONTROL1_REFH_TX_MASK                            0x0800
#define TX2_ANATXACONTROL1_REFH_TX_ALIGN                           0
#define TX2_ANATXACONTROL1_REFH_TX_BITS                            1
#define TX2_ANATXACONTROL1_REFH_TX_SHIFT                           11

/* Tx2 :: anaTxAControl1 :: newbias_en [10:10] */
#define TX2_ANATXACONTROL1_NEWBIAS_EN_MASK                         0x0400
#define TX2_ANATXACONTROL1_NEWBIAS_EN_ALIGN                        0
#define TX2_ANATXACONTROL1_NEWBIAS_EN_BITS                         1
#define TX2_ANATXACONTROL1_NEWBIAS_EN_SHIFT                        10

/* Tx2 :: anaTxAControl1 :: drivermode [09:09] */
#define TX2_ANATXACONTROL1_DRIVERMODE_MASK                         0x0200
#define TX2_ANATXACONTROL1_DRIVERMODE_ALIGN                        0
#define TX2_ANATXACONTROL1_DRIVERMODE_BITS                         1
#define TX2_ANATXACONTROL1_DRIVERMODE_SHIFT                        9

/* Tx2 :: anaTxAControl1 :: vddr_bgb [08:08] */
#define TX2_ANATXACONTROL1_VDDR_BGB_MASK                           0x0100
#define TX2_ANATXACONTROL1_VDDR_BGB_ALIGN                          0
#define TX2_ANATXACONTROL1_VDDR_BGB_BITS                           1
#define TX2_ANATXACONTROL1_VDDR_BGB_SHIFT                          8

/* Tx2 :: anaTxAControl1 :: ticksel [07:06] */
#define TX2_ANATXACONTROL1_TICKSEL_MASK                            0x00c0
#define TX2_ANATXACONTROL1_TICKSEL_ALIGN                           0
#define TX2_ANATXACONTROL1_TICKSEL_BITS                            2
#define TX2_ANATXACONTROL1_TICKSEL_SHIFT                           6

/* Tx2 :: anaTxAControl1 :: driver_vcm [05:04] */
#define TX2_ANATXACONTROL1_DRIVER_VCM_MASK                         0x0030
#define TX2_ANATXACONTROL1_DRIVER_VCM_ALIGN                        0
#define TX2_ANATXACONTROL1_DRIVER_VCM_BITS                         2
#define TX2_ANATXACONTROL1_DRIVER_VCM_SHIFT                        4

/* Tx2 :: anaTxAControl1 :: tx_sel_halfrate [03:03] */
#define TX2_ANATXACONTROL1_TX_SEL_HALFRATE_MASK                    0x0008
#define TX2_ANATXACONTROL1_TX_SEL_HALFRATE_ALIGN                   0
#define TX2_ANATXACONTROL1_TX_SEL_HALFRATE_BITS                    1
#define TX2_ANATXACONTROL1_TX_SEL_HALFRATE_SHIFT                   3

/* Tx2 :: anaTxAControl1 :: ifullspd [02:00] */
#define TX2_ANATXACONTROL1_IFULLSPD_MASK                           0x0007
#define TX2_ANATXACONTROL1_IFULLSPD_ALIGN                          0
#define TX2_ANATXACONTROL1_IFULLSPD_BITS                           3
#define TX2_ANATXACONTROL1_IFULLSPD_SHIFT                          0


/****************************************************************************
 * Tx2 :: anaTxAControl2
 ***************************************************************************/
/* Tx2 :: anaTxAControl2 :: icbuf1t [15:14] */
#define TX2_ANATXACONTROL2_ICBUF1T_MASK                            0xc000
#define TX2_ANATXACONTROL2_ICBUF1T_ALIGN                           0
#define TX2_ANATXACONTROL2_ICBUF1T_BITS                            2
#define TX2_ANATXACONTROL2_ICBUF1T_SHIFT                           14

/* Tx2 :: anaTxAControl2 :: icbuf2t [13:11] */
#define TX2_ANATXACONTROL2_ICBUF2T_MASK                            0x3800
#define TX2_ANATXACONTROL2_ICBUF2T_ALIGN                           0
#define TX2_ANATXACONTROL2_ICBUF2T_BITS                            3
#define TX2_ANATXACONTROL2_ICBUF2T_SHIFT                           11

/* Tx2 :: anaTxAControl2 :: imin_predrv [10:10] */
#define TX2_ANATXACONTROL2_IMIN_PREDRV_MASK                        0x0400
#define TX2_ANATXACONTROL2_IMIN_PREDRV_ALIGN                       0
#define TX2_ANATXACONTROL2_IMIN_PREDRV_BITS                        1
#define TX2_ANATXACONTROL2_IMIN_PREDRV_SHIFT                       10

/* Tx2 :: anaTxAControl2 :: imax_predrv [09:09] */
#define TX2_ANATXACONTROL2_IMAX_PREDRV_MASK                        0x0200
#define TX2_ANATXACONTROL2_IMAX_PREDRV_ALIGN                       0
#define TX2_ANATXACONTROL2_IMAX_PREDRV_BITS                        1
#define TX2_ANATXACONTROL2_IMAX_PREDRV_SHIFT                       9

/* Tx2 :: anaTxAControl2 :: imode_predrv [08:08] */
#define TX2_ANATXACONTROL2_IMODE_PREDRV_MASK                       0x0100
#define TX2_ANATXACONTROL2_IMODE_PREDRV_ALIGN                      0
#define TX2_ANATXACONTROL2_IMODE_PREDRV_BITS                       1
#define TX2_ANATXACONTROL2_IMODE_PREDRV_SHIFT                      8

/* Tx2 :: anaTxAControl2 :: i21mux [07:05] */
#define TX2_ANATXACONTROL2_I21MUX_MASK                             0x00e0
#define TX2_ANATXACONTROL2_I21MUX_ALIGN                            0
#define TX2_ANATXACONTROL2_I21MUX_BITS                             3
#define TX2_ANATXACONTROL2_I21MUX_SHIFT                            5

/* Tx2 :: anaTxAControl2 :: imin_drvr [04:04] */
#define TX2_ANATXACONTROL2_IMIN_DRVR_MASK                          0x0010
#define TX2_ANATXACONTROL2_IMIN_DRVR_ALIGN                         0
#define TX2_ANATXACONTROL2_IMIN_DRVR_BITS                          1
#define TX2_ANATXACONTROL2_IMIN_DRVR_SHIFT                         4

/* Tx2 :: anaTxAControl2 :: imax_drvr [03:03] */
#define TX2_ANATXACONTROL2_IMAX_DRVR_MASK                          0x0008
#define TX2_ANATXACONTROL2_IMAX_DRVR_ALIGN                         0
#define TX2_ANATXACONTROL2_IMAX_DRVR_BITS                          1
#define TX2_ANATXACONTROL2_IMAX_DRVR_SHIFT                         3

/* Tx2 :: anaTxAControl2 :: imode_drvr [02:02] */
#define TX2_ANATXACONTROL2_IMODE_DRVR_MASK                         0x0004
#define TX2_ANATXACONTROL2_IMODE_DRVR_ALIGN                        0
#define TX2_ANATXACONTROL2_IMODE_DRVR_BITS                         1
#define TX2_ANATXACONTROL2_IMODE_DRVR_SHIFT                        2

/* Tx2 :: anaTxAControl2 :: reserved0 [01:00] */
#define TX2_ANATXACONTROL2_RESERVED0_MASK                          0x0003
#define TX2_ANATXACONTROL2_RESERVED0_ALIGN                         0
#define TX2_ANATXACONTROL2_RESERVED0_BITS                          2
#define TX2_ANATXACONTROL2_RESERVED0_SHIFT                         0


/****************************************************************************
 * Tx2 :: Tx_OS_Driver
 ***************************************************************************/
/* Tx2 :: Tx_OS_Driver :: preemphasis_post [15:12] */
#define TX2_TX_OS_DRIVER_PREEMPHASIS_POST_MASK                     0xf000
#define TX2_TX_OS_DRIVER_PREEMPHASIS_POST_ALIGN                    0
#define TX2_TX_OS_DRIVER_PREEMPHASIS_POST_BITS                     4
#define TX2_TX_OS_DRIVER_PREEMPHASIS_POST_SHIFT                    12

/* Tx2 :: Tx_OS_Driver :: Idriver [11:08] */
#define TX2_TX_OS_DRIVER_IDRIVER_MASK                              0x0f00
#define TX2_TX_OS_DRIVER_IDRIVER_ALIGN                             0
#define TX2_TX_OS_DRIVER_IDRIVER_BITS                              4
#define TX2_TX_OS_DRIVER_IDRIVER_SHIFT                             8

/* Tx2 :: Tx_OS_Driver :: Ipredriver [07:04] */
#define TX2_TX_OS_DRIVER_IPREDRIVER_MASK                           0x00f0
#define TX2_TX_OS_DRIVER_IPREDRIVER_ALIGN                          0
#define TX2_TX_OS_DRIVER_IPREDRIVER_BITS                           4
#define TX2_TX_OS_DRIVER_IPREDRIVER_SHIFT                          4

/* Tx2 :: Tx_OS_Driver :: preemphasis_pre [03:01] */
#define TX2_TX_OS_DRIVER_PREEMPHASIS_PRE_MASK                      0x000e
#define TX2_TX_OS_DRIVER_PREEMPHASIS_PRE_ALIGN                     0
#define TX2_TX_OS_DRIVER_PREEMPHASIS_PRE_BITS                      3
#define TX2_TX_OS_DRIVER_PREEMPHASIS_PRE_SHIFT                     1

/* Tx2 :: Tx_OS_Driver :: icbuf1t0 [00:00] */
#define TX2_TX_OS_DRIVER_ICBUF1T0_MASK                             0x0001
#define TX2_TX_OS_DRIVER_ICBUF1T0_ALIGN                            0
#define TX2_TX_OS_DRIVER_ICBUF1T0_BITS                             1
#define TX2_TX_OS_DRIVER_ICBUF1T0_SHIFT                            0


/****************************************************************************
 * Tx2 :: Tx_BR_Driver
 ***************************************************************************/
/* Tx2 :: Tx_BR_Driver :: preemphasis_post [15:12] */
#define TX2_TX_BR_DRIVER_PREEMPHASIS_POST_MASK                     0xf000
#define TX2_TX_BR_DRIVER_PREEMPHASIS_POST_ALIGN                    0
#define TX2_TX_BR_DRIVER_PREEMPHASIS_POST_BITS                     4
#define TX2_TX_BR_DRIVER_PREEMPHASIS_POST_SHIFT                    12

/* Tx2 :: Tx_BR_Driver :: Idriver [11:08] */
#define TX2_TX_BR_DRIVER_IDRIVER_MASK                              0x0f00
#define TX2_TX_BR_DRIVER_IDRIVER_ALIGN                             0
#define TX2_TX_BR_DRIVER_IDRIVER_BITS                              4
#define TX2_TX_BR_DRIVER_IDRIVER_SHIFT                             8

/* Tx2 :: Tx_BR_Driver :: Ipredriver [07:04] */
#define TX2_TX_BR_DRIVER_IPREDRIVER_MASK                           0x00f0
#define TX2_TX_BR_DRIVER_IPREDRIVER_ALIGN                          0
#define TX2_TX_BR_DRIVER_IPREDRIVER_BITS                           4
#define TX2_TX_BR_DRIVER_IPREDRIVER_SHIFT                          4

/* Tx2 :: Tx_BR_Driver :: preemphasis_pre [03:01] */
#define TX2_TX_BR_DRIVER_PREEMPHASIS_PRE_MASK                      0x000e
#define TX2_TX_BR_DRIVER_PREEMPHASIS_PRE_ALIGN                     0
#define TX2_TX_BR_DRIVER_PREEMPHASIS_PRE_BITS                      3
#define TX2_TX_BR_DRIVER_PREEMPHASIS_PRE_SHIFT                     1

/* Tx2 :: Tx_BR_Driver :: icbuf1t0 [00:00] */
#define TX2_TX_BR_DRIVER_ICBUF1T0_MASK                             0x0001
#define TX2_TX_BR_DRIVER_ICBUF1T0_ALIGN                            0
#define TX2_TX_BR_DRIVER_ICBUF1T0_BITS                             1
#define TX2_TX_BR_DRIVER_ICBUF1T0_SHIFT                            0


/****************************************************************************
 * Hypercore_USER_Tx3
 ***************************************************************************/
/****************************************************************************
 * Tx3 :: anaTxAStatus0
 ***************************************************************************/
/* Tx3 :: anaTxAStatus0 :: reserved0 [15:07] */
#define TX3_ANATXASTATUS0_RESERVED0_MASK                           0xff80
#define TX3_ANATXASTATUS0_RESERVED0_ALIGN                          0
#define TX3_ANATXASTATUS0_RESERVED0_BITS                           9
#define TX3_ANATXASTATUS0_RESERVED0_SHIFT                          7

/* Tx3 :: anaTxAStatus0 :: txdisable_ln [06:06] */
#define TX3_ANATXASTATUS0_TXDISABLE_LN_MASK                        0x0040
#define TX3_ANATXASTATUS0_TXDISABLE_LN_ALIGN                       0
#define TX3_ANATXASTATUS0_TXDISABLE_LN_BITS                        1
#define TX3_ANATXASTATUS0_TXDISABLE_LN_SHIFT                       6

/* Tx3 :: anaTxAStatus0 :: txferr_stky [05:05] */
#define TX3_ANATXASTATUS0_TXFERR_STKY_MASK                         0x0020
#define TX3_ANATXASTATUS0_TXFERR_STKY_ALIGN                        0
#define TX3_ANATXASTATUS0_TXFERR_STKY_BITS                         1
#define TX3_ANATXASTATUS0_TXFERR_STKY_SHIFT                        5

/* Tx3 :: anaTxAStatus0 :: tbi_mode [04:04] */
#define TX3_ANATXASTATUS0_TBI_MODE_MASK                            0x0010
#define TX3_ANATXASTATUS0_TBI_MODE_ALIGN                           0
#define TX3_ANATXASTATUS0_TBI_MODE_BITS                            1
#define TX3_ANATXASTATUS0_TBI_MODE_SHIFT                           4

/* Tx3 :: anaTxAStatus0 :: tx_reset [03:03] */
#define TX3_ANATXASTATUS0_TX_RESET_MASK                            0x0008
#define TX3_ANATXASTATUS0_TX_RESET_ALIGN                           0
#define TX3_ANATXASTATUS0_TX_RESET_BITS                            1
#define TX3_ANATXASTATUS0_TX_RESET_SHIFT                           3

/* Tx3 :: anaTxAStatus0 :: tx_pwrdn [02:02] */
#define TX3_ANATXASTATUS0_TX_PWRDN_MASK                            0x0004
#define TX3_ANATXASTATUS0_TX_PWRDN_ALIGN                           0
#define TX3_ANATXASTATUS0_TX_PWRDN_BITS                            1
#define TX3_ANATXASTATUS0_TX_PWRDN_SHIFT                           2

/* Tx3 :: anaTxAStatus0 :: rltxferr_stky [01:01] */
#define TX3_ANATXASTATUS0_RLTXFERR_STKY_MASK                       0x0002
#define TX3_ANATXASTATUS0_RLTXFERR_STKY_ALIGN                      0
#define TX3_ANATXASTATUS0_RLTXFERR_STKY_BITS                       1
#define TX3_ANATXASTATUS0_RLTXFERR_STKY_SHIFT                      1

/* Tx3 :: anaTxAStatus0 :: txpll_lock [00:00] */
#define TX3_ANATXASTATUS0_TXPLL_LOCK_MASK                          0x0001
#define TX3_ANATXASTATUS0_TXPLL_LOCK_ALIGN                         0
#define TX3_ANATXASTATUS0_TXPLL_LOCK_BITS                          1
#define TX3_ANATXASTATUS0_TXPLL_LOCK_SHIFT                         0


/****************************************************************************
 * Tx3 :: anaTxAControl0
 ***************************************************************************/
/* Tx3 :: anaTxAControl0 :: reserved0 [15:15] */
#define TX3_ANATXACONTROL0_RESERVED0_MASK                          0x8000
#define TX3_ANATXACONTROL0_RESERVED0_ALIGN                         0
#define TX3_ANATXACONTROL0_RESERVED0_BITS                          1
#define TX3_ANATXACONTROL0_RESERVED0_SHIFT                         15

/* Tx3 :: anaTxAControl0 :: force_txclk [14:14] */
#define TX3_ANATXACONTROL0_FORCE_TXCLK_MASK                        0x4000
#define TX3_ANATXACONTROL0_FORCE_TXCLK_ALIGN                       0
#define TX3_ANATXACONTROL0_FORCE_TXCLK_BITS                        1
#define TX3_ANATXACONTROL0_FORCE_TXCLK_SHIFT                       14

/* Tx3 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */
#define TX3_ANATXACONTROL0_TX1G_FIFO_RST_MASK                      0x2000
#define TX3_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN                     0
#define TX3_ANATXACONTROL0_TX1G_FIFO_RST_BITS                      1
#define TX3_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT                     13

/* Tx3 :: anaTxAControl0 :: gloopOutEn [12:12] */
#define TX3_ANATXACONTROL0_GLOOPOUTEN_MASK                         0x1000
#define TX3_ANATXACONTROL0_GLOOPOUTEN_ALIGN                        0
#define TX3_ANATXACONTROL0_GLOOPOUTEN_BITS                         1
#define TX3_ANATXACONTROL0_GLOOPOUTEN_SHIFT                        12

/* Tx3 :: anaTxAControl0 :: reserved1 [11:09] */
#define TX3_ANATXACONTROL0_RESERVED1_MASK                          0x0e00
#define TX3_ANATXACONTROL0_RESERVED1_ALIGN                         0
#define TX3_ANATXACONTROL0_RESERVED1_BITS                          3
#define TX3_ANATXACONTROL0_RESERVED1_SHIFT                         9

/* Tx3 :: anaTxAControl0 :: prbs_en [08:08] */
#define TX3_ANATXACONTROL0_PRBS_EN_MASK                            0x0100
#define TX3_ANATXACONTROL0_PRBS_EN_ALIGN                           0
#define TX3_ANATXACONTROL0_PRBS_EN_BITS                            1
#define TX3_ANATXACONTROL0_PRBS_EN_SHIFT                           8

/* Tx3 :: anaTxAControl0 :: pckt_en [07:07] */
#define TX3_ANATXACONTROL0_PCKT_EN_MASK                            0x0080
#define TX3_ANATXACONTROL0_PCKT_EN_ALIGN                           0
#define TX3_ANATXACONTROL0_PCKT_EN_BITS                            1
#define TX3_ANATXACONTROL0_PCKT_EN_SHIFT                           7

/* Tx3 :: anaTxAControl0 :: pckt_strt [06:06] */
#define TX3_ANATXACONTROL0_PCKT_STRT_MASK                          0x0040
#define TX3_ANATXACONTROL0_PCKT_STRT_ALIGN                         0
#define TX3_ANATXACONTROL0_PCKT_STRT_BITS                          1
#define TX3_ANATXACONTROL0_PCKT_STRT_SHIFT                         6

/* Tx3 :: anaTxAControl0 :: txpol_flip [05:05] */
#define TX3_ANATXACONTROL0_TXPOL_FLIP_MASK                         0x0020
#define TX3_ANATXACONTROL0_TXPOL_FLIP_ALIGN                        0
#define TX3_ANATXACONTROL0_TXPOL_FLIP_BITS                         1
#define TX3_ANATXACONTROL0_TXPOL_FLIP_SHIFT                        5

/* Tx3 :: anaTxAControl0 :: rtbi_flip [04:04] */
#define TX3_ANATXACONTROL0_RTBI_FLIP_MASK                          0x0010
#define TX3_ANATXACONTROL0_RTBI_FLIP_ALIGN                         0
#define TX3_ANATXACONTROL0_RTBI_FLIP_BITS                          1
#define TX3_ANATXACONTROL0_RTBI_FLIP_SHIFT                         4

/* Tx3 :: anaTxAControl0 :: eden_r [03:03] */
#define TX3_ANATXACONTROL0_EDEN_R_MASK                             0x0008
#define TX3_ANATXACONTROL0_EDEN_R_ALIGN                            0
#define TX3_ANATXACONTROL0_EDEN_R_BITS                             1
#define TX3_ANATXACONTROL0_EDEN_R_SHIFT                            3

/* Tx3 :: anaTxAControl0 :: eden_force_r [02:02] */
#define TX3_ANATXACONTROL0_EDEN_FORCE_R_MASK                       0x0004
#define TX3_ANATXACONTROL0_EDEN_FORCE_R_ALIGN                      0
#define TX3_ANATXACONTROL0_EDEN_FORCE_R_BITS                       1
#define TX3_ANATXACONTROL0_EDEN_FORCE_R_SHIFT                      2

/* Tx3 :: anaTxAControl0 :: txpat_en [01:01] */
#define TX3_ANATXACONTROL0_TXPAT_EN_MASK                           0x0002
#define TX3_ANATXACONTROL0_TXPAT_EN_ALIGN                          0
#define TX3_ANATXACONTROL0_TXPAT_EN_BITS                           1
#define TX3_ANATXACONTROL0_TXPAT_EN_SHIFT                          1

/* Tx3 :: anaTxAControl0 :: tx_mdata_en [00:00] */
#define TX3_ANATXACONTROL0_TX_MDATA_EN_MASK                        0x0001
#define TX3_ANATXACONTROL0_TX_MDATA_EN_ALIGN                       0
#define TX3_ANATXACONTROL0_TX_MDATA_EN_BITS                        1
#define TX3_ANATXACONTROL0_TX_MDATA_EN_SHIFT                       0


/****************************************************************************
 * Tx3 :: anaTxmdata0
 ***************************************************************************/
/* Tx3 :: anaTxmdata0 :: txTestMuxSel [15:13] */
#define TX3_ANATXMDATA0_TXTESTMUXSEL_MASK                          0xe000
#define TX3_ANATXMDATA0_TXTESTMUXSEL_ALIGN                         0
#define TX3_ANATXMDATA0_TXTESTMUXSEL_BITS                          3
#define TX3_ANATXMDATA0_TXTESTMUXSEL_SHIFT                         13

/* Tx3 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */
#define TX3_ANATXMDATA0_RLFIFO_TSTSEL_MASK                         0x1c00
#define TX3_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN                        0
#define TX3_ANATXMDATA0_RLFIFO_TSTSEL_BITS                         3
#define TX3_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT                        10

/* Tx3 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */
#define TX3_ANATXMDATA0_TXMDIOTSTDATAL_MASK                        0x03ff
#define TX3_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN                       0
#define TX3_ANATXMDATA0_TXMDIOTSTDATAL_BITS                        10
#define TX3_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT                       0


/****************************************************************************
 * Tx3 :: anaTxmdata1
 ***************************************************************************/
/* Tx3 :: anaTxmdata1 :: reserved0 [15:10] */
#define TX3_ANATXMDATA1_RESERVED0_MASK                             0xfc00
#define TX3_ANATXMDATA1_RESERVED0_ALIGN                            0
#define TX3_ANATXMDATA1_RESERVED0_BITS                             6
#define TX3_ANATXMDATA1_RESERVED0_SHIFT                            10

/* Tx3 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */
#define TX3_ANATXMDATA1_TXMDIOTSTDATAH_MASK                        0x03ff
#define TX3_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN                       0
#define TX3_ANATXMDATA1_TXMDIOTSTDATAH_BITS                        10
#define TX3_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT                       0


/****************************************************************************
 * Tx3 :: anaTxAStatus1
 ***************************************************************************/
/* Tx3 :: anaTxAStatus1 :: tx_id [15:14] */
#define TX3_ANATXASTATUS1_TX_ID_MASK                               0xc000
#define TX3_ANATXASTATUS1_TX_ID_ALIGN                              0
#define TX3_ANATXASTATUS1_TX_ID_BITS                               2
#define TX3_ANATXASTATUS1_TX_ID_SHIFT                              14

/* Tx3 :: anaTxAStatus1 :: reserved0 [13:00] */
#define TX3_ANATXASTATUS1_RESERVED0_MASK                           0x3fff
#define TX3_ANATXASTATUS1_RESERVED0_ALIGN                          0
#define TX3_ANATXASTATUS1_RESERVED0_BITS                           14
#define TX3_ANATXASTATUS1_RESERVED0_SHIFT                          0


/****************************************************************************
 * Tx3 :: anaTxAControl1
 ***************************************************************************/
/* Tx3 :: anaTxAControl1 :: id2c [15:13] */
#define TX3_ANATXACONTROL1_ID2C_MASK                               0xe000
#define TX3_ANATXACONTROL1_ID2C_ALIGN                              0
#define TX3_ANATXACONTROL1_ID2C_BITS                               3
#define TX3_ANATXACONTROL1_ID2C_SHIFT                              13

/* Tx3 :: anaTxAControl1 :: refl_tx [12:12] */
#define TX3_ANATXACONTROL1_REFL_TX_MASK                            0x1000
#define TX3_ANATXACONTROL1_REFL_TX_ALIGN                           0
#define TX3_ANATXACONTROL1_REFL_TX_BITS                            1
#define TX3_ANATXACONTROL1_REFL_TX_SHIFT                           12

/* Tx3 :: anaTxAControl1 :: refh_tx [11:11] */
#define TX3_ANATXACONTROL1_REFH_TX_MASK                            0x0800
#define TX3_ANATXACONTROL1_REFH_TX_ALIGN                           0
#define TX3_ANATXACONTROL1_REFH_TX_BITS                            1
#define TX3_ANATXACONTROL1_REFH_TX_SHIFT                           11

/* Tx3 :: anaTxAControl1 :: newbias_en [10:10] */
#define TX3_ANATXACONTROL1_NEWBIAS_EN_MASK                         0x0400
#define TX3_ANATXACONTROL1_NEWBIAS_EN_ALIGN                        0
#define TX3_ANATXACONTROL1_NEWBIAS_EN_BITS                         1
#define TX3_ANATXACONTROL1_NEWBIAS_EN_SHIFT                        10

/* Tx3 :: anaTxAControl1 :: drivermode [09:09] */
#define TX3_ANATXACONTROL1_DRIVERMODE_MASK                         0x0200
#define TX3_ANATXACONTROL1_DRIVERMODE_ALIGN                        0
#define TX3_ANATXACONTROL1_DRIVERMODE_BITS                         1
#define TX3_ANATXACONTROL1_DRIVERMODE_SHIFT                        9

/* Tx3 :: anaTxAControl1 :: vddr_bgb [08:08] */
#define TX3_ANATXACONTROL1_VDDR_BGB_MASK                           0x0100
#define TX3_ANATXACONTROL1_VDDR_BGB_ALIGN                          0
#define TX3_ANATXACONTROL1_VDDR_BGB_BITS                           1
#define TX3_ANATXACONTROL1_VDDR_BGB_SHIFT                          8

/* Tx3 :: anaTxAControl1 :: ticksel [07:06] */
#define TX3_ANATXACONTROL1_TICKSEL_MASK                            0x00c0
#define TX3_ANATXACONTROL1_TICKSEL_ALIGN                           0
#define TX3_ANATXACONTROL1_TICKSEL_BITS                            2
#define TX3_ANATXACONTROL1_TICKSEL_SHIFT                           6

/* Tx3 :: anaTxAControl1 :: driver_vcm [05:04] */
#define TX3_ANATXACONTROL1_DRIVER_VCM_MASK                         0x0030
#define TX3_ANATXACONTROL1_DRIVER_VCM_ALIGN                        0
#define TX3_ANATXACONTROL1_DRIVER_VCM_BITS                         2
#define TX3_ANATXACONTROL1_DRIVER_VCM_SHIFT                        4

/* Tx3 :: anaTxAControl1 :: tx_sel_halfrate [03:03] */
#define TX3_ANATXACONTROL1_TX_SEL_HALFRATE_MASK                    0x0008
#define TX3_ANATXACONTROL1_TX_SEL_HALFRATE_ALIGN                   0
#define TX3_ANATXACONTROL1_TX_SEL_HALFRATE_BITS                    1
#define TX3_ANATXACONTROL1_TX_SEL_HALFRATE_SHIFT                   3

/* Tx3 :: anaTxAControl1 :: ifullspd [02:00] */
#define TX3_ANATXACONTROL1_IFULLSPD_MASK                           0x0007
#define TX3_ANATXACONTROL1_IFULLSPD_ALIGN                          0
#define TX3_ANATXACONTROL1_IFULLSPD_BITS                           3
#define TX3_ANATXACONTROL1_IFULLSPD_SHIFT                          0


/****************************************************************************
 * Tx3 :: anaTxAControl2
 ***************************************************************************/
/* Tx3 :: anaTxAControl2 :: icbuf1t [15:14] */
#define TX3_ANATXACONTROL2_ICBUF1T_MASK                            0xc000
#define TX3_ANATXACONTROL2_ICBUF1T_ALIGN                           0
#define TX3_ANATXACONTROL2_ICBUF1T_BITS                            2
#define TX3_ANATXACONTROL2_ICBUF1T_SHIFT                           14

/* Tx3 :: anaTxAControl2 :: icbuf2t [13:11] */
#define TX3_ANATXACONTROL2_ICBUF2T_MASK                            0x3800
#define TX3_ANATXACONTROL2_ICBUF2T_ALIGN                           0
#define TX3_ANATXACONTROL2_ICBUF2T_BITS                            3
#define TX3_ANATXACONTROL2_ICBUF2T_SHIFT                           11

/* Tx3 :: anaTxAControl2 :: imin_predrv [10:10] */
#define TX3_ANATXACONTROL2_IMIN_PREDRV_MASK                        0x0400
#define TX3_ANATXACONTROL2_IMIN_PREDRV_ALIGN                       0
#define TX3_ANATXACONTROL2_IMIN_PREDRV_BITS                        1
#define TX3_ANATXACONTROL2_IMIN_PREDRV_SHIFT                       10

/* Tx3 :: anaTxAControl2 :: imax_predrv [09:09] */
#define TX3_ANATXACONTROL2_IMAX_PREDRV_MASK                        0x0200
#define TX3_ANATXACONTROL2_IMAX_PREDRV_ALIGN                       0
#define TX3_ANATXACONTROL2_IMAX_PREDRV_BITS                        1
#define TX3_ANATXACONTROL2_IMAX_PREDRV_SHIFT                       9

/* Tx3 :: anaTxAControl2 :: imode_predrv [08:08] */
#define TX3_ANATXACONTROL2_IMODE_PREDRV_MASK                       0x0100
#define TX3_ANATXACONTROL2_IMODE_PREDRV_ALIGN                      0
#define TX3_ANATXACONTROL2_IMODE_PREDRV_BITS                       1
#define TX3_ANATXACONTROL2_IMODE_PREDRV_SHIFT                      8

/* Tx3 :: anaTxAControl2 :: i21mux [07:05] */
#define TX3_ANATXACONTROL2_I21MUX_MASK                             0x00e0
#define TX3_ANATXACONTROL2_I21MUX_ALIGN                            0
#define TX3_ANATXACONTROL2_I21MUX_BITS                             3
#define TX3_ANATXACONTROL2_I21MUX_SHIFT                            5

/* Tx3 :: anaTxAControl2 :: imin_drvr [04:04] */
#define TX3_ANATXACONTROL2_IMIN_DRVR_MASK                          0x0010
#define TX3_ANATXACONTROL2_IMIN_DRVR_ALIGN                         0
#define TX3_ANATXACONTROL2_IMIN_DRVR_BITS                          1
#define TX3_ANATXACONTROL2_IMIN_DRVR_SHIFT                         4

/* Tx3 :: anaTxAControl2 :: imax_drvr [03:03] */
#define TX3_ANATXACONTROL2_IMAX_DRVR_MASK                          0x0008
#define TX3_ANATXACONTROL2_IMAX_DRVR_ALIGN                         0
#define TX3_ANATXACONTROL2_IMAX_DRVR_BITS                          1
#define TX3_ANATXACONTROL2_IMAX_DRVR_SHIFT                         3

/* Tx3 :: anaTxAControl2 :: imode_drvr [02:02] */
#define TX3_ANATXACONTROL2_IMODE_DRVR_MASK                         0x0004
#define TX3_ANATXACONTROL2_IMODE_DRVR_ALIGN                        0
#define TX3_ANATXACONTROL2_IMODE_DRVR_BITS                         1
#define TX3_ANATXACONTROL2_IMODE_DRVR_SHIFT                        2

/* Tx3 :: anaTxAControl2 :: reserved0 [01:00] */
#define TX3_ANATXACONTROL2_RESERVED0_MASK                          0x0003
#define TX3_ANATXACONTROL2_RESERVED0_ALIGN                         0
#define TX3_ANATXACONTROL2_RESERVED0_BITS                          2
#define TX3_ANATXACONTROL2_RESERVED0_SHIFT                         0


/****************************************************************************
 * Tx3 :: Tx_OS_Driver
 ***************************************************************************/
/* Tx3 :: Tx_OS_Driver :: preemphasis_post [15:12] */
#define TX3_TX_OS_DRIVER_PREEMPHASIS_POST_MASK                     0xf000
#define TX3_TX_OS_DRIVER_PREEMPHASIS_POST_ALIGN                    0
#define TX3_TX_OS_DRIVER_PREEMPHASIS_POST_BITS                     4
#define TX3_TX_OS_DRIVER_PREEMPHASIS_POST_SHIFT                    12

/* Tx3 :: Tx_OS_Driver :: Idriver [11:08] */
#define TX3_TX_OS_DRIVER_IDRIVER_MASK                              0x0f00
#define TX3_TX_OS_DRIVER_IDRIVER_ALIGN                             0
#define TX3_TX_OS_DRIVER_IDRIVER_BITS                              4
#define TX3_TX_OS_DRIVER_IDRIVER_SHIFT                             8

/* Tx3 :: Tx_OS_Driver :: Ipredriver [07:04] */
#define TX3_TX_OS_DRIVER_IPREDRIVER_MASK                           0x00f0
#define TX3_TX_OS_DRIVER_IPREDRIVER_ALIGN                          0
#define TX3_TX_OS_DRIVER_IPREDRIVER_BITS                           4
#define TX3_TX_OS_DRIVER_IPREDRIVER_SHIFT                          4

/* Tx3 :: Tx_OS_Driver :: preemphasis_pre [03:01] */
#define TX3_TX_OS_DRIVER_PREEMPHASIS_PRE_MASK                      0x000e
#define TX3_TX_OS_DRIVER_PREEMPHASIS_PRE_ALIGN                     0
#define TX3_TX_OS_DRIVER_PREEMPHASIS_PRE_BITS                      3
#define TX3_TX_OS_DRIVER_PREEMPHASIS_PRE_SHIFT                     1

/* Tx3 :: Tx_OS_Driver :: icbuf1t0 [00:00] */
#define TX3_TX_OS_DRIVER_ICBUF1T0_MASK                             0x0001
#define TX3_TX_OS_DRIVER_ICBUF1T0_ALIGN                            0
#define TX3_TX_OS_DRIVER_ICBUF1T0_BITS                             1
#define TX3_TX_OS_DRIVER_ICBUF1T0_SHIFT                            0


/****************************************************************************
 * Tx3 :: Tx_BR_Driver
 ***************************************************************************/
/* Tx3 :: Tx_BR_Driver :: preemphasis_post [15:12] */
#define TX3_TX_BR_DRIVER_PREEMPHASIS_POST_MASK                     0xf000
#define TX3_TX_BR_DRIVER_PREEMPHASIS_POST_ALIGN                    0
#define TX3_TX_BR_DRIVER_PREEMPHASIS_POST_BITS                     4
#define TX3_TX_BR_DRIVER_PREEMPHASIS_POST_SHIFT                    12

/* Tx3 :: Tx_BR_Driver :: Idriver [11:08] */
#define TX3_TX_BR_DRIVER_IDRIVER_MASK                              0x0f00
#define TX3_TX_BR_DRIVER_IDRIVER_ALIGN                             0
#define TX3_TX_BR_DRIVER_IDRIVER_BITS                              4
#define TX3_TX_BR_DRIVER_IDRIVER_SHIFT                             8

/* Tx3 :: Tx_BR_Driver :: Ipredriver [07:04] */
#define TX3_TX_BR_DRIVER_IPREDRIVER_MASK                           0x00f0
#define TX3_TX_BR_DRIVER_IPREDRIVER_ALIGN                          0
#define TX3_TX_BR_DRIVER_IPREDRIVER_BITS                           4
#define TX3_TX_BR_DRIVER_IPREDRIVER_SHIFT                          4

/* Tx3 :: Tx_BR_Driver :: preemphasis_pre [03:01] */
#define TX3_TX_BR_DRIVER_PREEMPHASIS_PRE_MASK                      0x000e
#define TX3_TX_BR_DRIVER_PREEMPHASIS_PRE_ALIGN                     0
#define TX3_TX_BR_DRIVER_PREEMPHASIS_PRE_BITS                      3
#define TX3_TX_BR_DRIVER_PREEMPHASIS_PRE_SHIFT                     1

/* Tx3 :: Tx_BR_Driver :: icbuf1t0 [00:00] */
#define TX3_TX_BR_DRIVER_ICBUF1T0_MASK                             0x0001
#define TX3_TX_BR_DRIVER_ICBUF1T0_ALIGN                            0
#define TX3_TX_BR_DRIVER_ICBUF1T0_BITS                             1
#define TX3_TX_BR_DRIVER_ICBUF1T0_SHIFT                            0


/****************************************************************************
 * Hypercore_USER_TxB
 ***************************************************************************/
/****************************************************************************
 * TxB :: anaTxAStatus0
 ***************************************************************************/
/* TxB :: anaTxAStatus0 :: reserved0 [15:07] */
#define TXB_ANATXASTATUS0_RESERVED0_MASK                           0xff80
#define TXB_ANATXASTATUS0_RESERVED0_ALIGN                          0
#define TXB_ANATXASTATUS0_RESERVED0_BITS                           9
#define TXB_ANATXASTATUS0_RESERVED0_SHIFT                          7

/* TxB :: anaTxAStatus0 :: txdisable_ln [06:06] */
#define TXB_ANATXASTATUS0_TXDISABLE_LN_MASK                        0x0040
#define TXB_ANATXASTATUS0_TXDISABLE_LN_ALIGN                       0
#define TXB_ANATXASTATUS0_TXDISABLE_LN_BITS                        1
#define TXB_ANATXASTATUS0_TXDISABLE_LN_SHIFT                       6

/* TxB :: anaTxAStatus0 :: txferr_stky [05:05] */
#define TXB_ANATXASTATUS0_TXFERR_STKY_MASK                         0x0020
#define TXB_ANATXASTATUS0_TXFERR_STKY_ALIGN                        0
#define TXB_ANATXASTATUS0_TXFERR_STKY_BITS                         1
#define TXB_ANATXASTATUS0_TXFERR_STKY_SHIFT                        5

/* TxB :: anaTxAStatus0 :: tbi_mode [04:04] */
#define TXB_ANATXASTATUS0_TBI_MODE_MASK                            0x0010
#define TXB_ANATXASTATUS0_TBI_MODE_ALIGN                           0
#define TXB_ANATXASTATUS0_TBI_MODE_BITS                            1
#define TXB_ANATXASTATUS0_TBI_MODE_SHIFT                           4

/* TxB :: anaTxAStatus0 :: tx_reset [03:03] */
#define TXB_ANATXASTATUS0_TX_RESET_MASK                            0x0008
#define TXB_ANATXASTATUS0_TX_RESET_ALIGN                           0
#define TXB_ANATXASTATUS0_TX_RESET_BITS                            1
#define TXB_ANATXASTATUS0_TX_RESET_SHIFT                           3

/* TxB :: anaTxAStatus0 :: tx_pwrdn [02:02] */
#define TXB_ANATXASTATUS0_TX_PWRDN_MASK                            0x0004
#define TXB_ANATXASTATUS0_TX_PWRDN_ALIGN                           0
#define TXB_ANATXASTATUS0_TX_PWRDN_BITS                            1
#define TXB_ANATXASTATUS0_TX_PWRDN_SHIFT                           2

/* TxB :: anaTxAStatus0 :: rltxferr_stky [01:01] */
#define TXB_ANATXASTATUS0_RLTXFERR_STKY_MASK                       0x0002
#define TXB_ANATXASTATUS0_RLTXFERR_STKY_ALIGN                      0
#define TXB_ANATXASTATUS0_RLTXFERR_STKY_BITS                       1
#define TXB_ANATXASTATUS0_RLTXFERR_STKY_SHIFT                      1

/* TxB :: anaTxAStatus0 :: txpll_lock [00:00] */
#define TXB_ANATXASTATUS0_TXPLL_LOCK_MASK                          0x0001
#define TXB_ANATXASTATUS0_TXPLL_LOCK_ALIGN                         0
#define TXB_ANATXASTATUS0_TXPLL_LOCK_BITS                          1
#define TXB_ANATXASTATUS0_TXPLL_LOCK_SHIFT                         0


/****************************************************************************
 * TxB :: anaTxAControl0
 ***************************************************************************/
/* TxB :: anaTxAControl0 :: reserved0 [15:15] */
#define TXB_ANATXACONTROL0_RESERVED0_MASK                          0x8000
#define TXB_ANATXACONTROL0_RESERVED0_ALIGN                         0
#define TXB_ANATXACONTROL0_RESERVED0_BITS                          1
#define TXB_ANATXACONTROL0_RESERVED0_SHIFT                         15

/* TxB :: anaTxAControl0 :: force_txclk [14:14] */
#define TXB_ANATXACONTROL0_FORCE_TXCLK_MASK                        0x4000
#define TXB_ANATXACONTROL0_FORCE_TXCLK_ALIGN                       0
#define TXB_ANATXACONTROL0_FORCE_TXCLK_BITS                        1
#define TXB_ANATXACONTROL0_FORCE_TXCLK_SHIFT                       14

/* TxB :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */
#define TXB_ANATXACONTROL0_TX1G_FIFO_RST_MASK                      0x2000
#define TXB_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN                     0
#define TXB_ANATXACONTROL0_TX1G_FIFO_RST_BITS                      1
#define TXB_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT                     13

/* TxB :: anaTxAControl0 :: gloopOutEn [12:12] */
#define TXB_ANATXACONTROL0_GLOOPOUTEN_MASK                         0x1000
#define TXB_ANATXACONTROL0_GLOOPOUTEN_ALIGN                        0
#define TXB_ANATXACONTROL0_GLOOPOUTEN_BITS                         1
#define TXB_ANATXACONTROL0_GLOOPOUTEN_SHIFT                        12

/* TxB :: anaTxAControl0 :: reserved1 [11:09] */
#define TXB_ANATXACONTROL0_RESERVED1_MASK                          0x0e00
#define TXB_ANATXACONTROL0_RESERVED1_ALIGN                         0
#define TXB_ANATXACONTROL0_RESERVED1_BITS                          3
#define TXB_ANATXACONTROL0_RESERVED1_SHIFT                         9

/* TxB :: anaTxAControl0 :: prbs_en [08:08] */
#define TXB_ANATXACONTROL0_PRBS_EN_MASK                            0x0100
#define TXB_ANATXACONTROL0_PRBS_EN_ALIGN                           0
#define TXB_ANATXACONTROL0_PRBS_EN_BITS                            1
#define TXB_ANATXACONTROL0_PRBS_EN_SHIFT                           8

/* TxB :: anaTxAControl0 :: pckt_en [07:07] */
#define TXB_ANATXACONTROL0_PCKT_EN_MASK                            0x0080
#define TXB_ANATXACONTROL0_PCKT_EN_ALIGN                           0
#define TXB_ANATXACONTROL0_PCKT_EN_BITS                            1
#define TXB_ANATXACONTROL0_PCKT_EN_SHIFT                           7

/* TxB :: anaTxAControl0 :: pckt_strt [06:06] */
#define TXB_ANATXACONTROL0_PCKT_STRT_MASK                          0x0040
#define TXB_ANATXACONTROL0_PCKT_STRT_ALIGN                         0
#define TXB_ANATXACONTROL0_PCKT_STRT_BITS                          1
#define TXB_ANATXACONTROL0_PCKT_STRT_SHIFT                         6

/* TxB :: anaTxAControl0 :: txpol_flip [05:05] */
#define TXB_ANATXACONTROL0_TXPOL_FLIP_MASK                         0x0020
#define TXB_ANATXACONTROL0_TXPOL_FLIP_ALIGN                        0
#define TXB_ANATXACONTROL0_TXPOL_FLIP_BITS                         1
#define TXB_ANATXACONTROL0_TXPOL_FLIP_SHIFT                        5

/* TxB :: anaTxAControl0 :: rtbi_flip [04:04] */
#define TXB_ANATXACONTROL0_RTBI_FLIP_MASK                          0x0010
#define TXB_ANATXACONTROL0_RTBI_FLIP_ALIGN                         0
#define TXB_ANATXACONTROL0_RTBI_FLIP_BITS                          1
#define TXB_ANATXACONTROL0_RTBI_FLIP_SHIFT                         4

/* TxB :: anaTxAControl0 :: eden_r [03:03] */
#define TXB_ANATXACONTROL0_EDEN_R_MASK                             0x0008
#define TXB_ANATXACONTROL0_EDEN_R_ALIGN                            0
#define TXB_ANATXACONTROL0_EDEN_R_BITS                             1
#define TXB_ANATXACONTROL0_EDEN_R_SHIFT                            3

/* TxB :: anaTxAControl0 :: eden_force_r [02:02] */
#define TXB_ANATXACONTROL0_EDEN_FORCE_R_MASK                       0x0004
#define TXB_ANATXACONTROL0_EDEN_FORCE_R_ALIGN                      0
#define TXB_ANATXACONTROL0_EDEN_FORCE_R_BITS                       1
#define TXB_ANATXACONTROL0_EDEN_FORCE_R_SHIFT                      2

/* TxB :: anaTxAControl0 :: txpat_en [01:01] */
#define TXB_ANATXACONTROL0_TXPAT_EN_MASK                           0x0002
#define TXB_ANATXACONTROL0_TXPAT_EN_ALIGN                          0
#define TXB_ANATXACONTROL0_TXPAT_EN_BITS                           1
#define TXB_ANATXACONTROL0_TXPAT_EN_SHIFT                          1

/* TxB :: anaTxAControl0 :: tx_mdata_en [00:00] */
#define TXB_ANATXACONTROL0_TX_MDATA_EN_MASK                        0x0001
#define TXB_ANATXACONTROL0_TX_MDATA_EN_ALIGN                       0
#define TXB_ANATXACONTROL0_TX_MDATA_EN_BITS                        1
#define TXB_ANATXACONTROL0_TX_MDATA_EN_SHIFT                       0


/****************************************************************************
 * TxB :: anaTxmdata0
 ***************************************************************************/
/* TxB :: anaTxmdata0 :: txTestMuxSel [15:13] */
#define TXB_ANATXMDATA0_TXTESTMUXSEL_MASK                          0xe000
#define TXB_ANATXMDATA0_TXTESTMUXSEL_ALIGN                         0
#define TXB_ANATXMDATA0_TXTESTMUXSEL_BITS                          3
#define TXB_ANATXMDATA0_TXTESTMUXSEL_SHIFT                         13

/* TxB :: anaTxmdata0 :: rlfifo_tstsel [12:10] */
#define TXB_ANATXMDATA0_RLFIFO_TSTSEL_MASK                         0x1c00
#define TXB_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN                        0
#define TXB_ANATXMDATA0_RLFIFO_TSTSEL_BITS                         3
#define TXB_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT                        10

/* TxB :: anaTxmdata0 :: TxMdioTstDataL [09:00] */
#define TXB_ANATXMDATA0_TXMDIOTSTDATAL_MASK                        0x03ff
#define TXB_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN                       0
#define TXB_ANATXMDATA0_TXMDIOTSTDATAL_BITS                        10
#define TXB_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT                       0


/****************************************************************************
 * TxB :: anaTxmdata1
 ***************************************************************************/
/* TxB :: anaTxmdata1 :: reserved0 [15:10] */
#define TXB_ANATXMDATA1_RESERVED0_MASK                             0xfc00
#define TXB_ANATXMDATA1_RESERVED0_ALIGN                            0
#define TXB_ANATXMDATA1_RESERVED0_BITS                             6
#define TXB_ANATXMDATA1_RESERVED0_SHIFT                            10

/* TxB :: anaTxmdata1 :: TxMdioTstDataH [09:00] */
#define TXB_ANATXMDATA1_TXMDIOTSTDATAH_MASK                        0x03ff
#define TXB_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN                       0
#define TXB_ANATXMDATA1_TXMDIOTSTDATAH_BITS                        10
#define TXB_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT                       0


/****************************************************************************
 * TxB :: anaTxAStatus1
 ***************************************************************************/
/* TxB :: anaTxAStatus1 :: tx_id [15:14] */
#define TXB_ANATXASTATUS1_TX_ID_MASK                               0xc000
#define TXB_ANATXASTATUS1_TX_ID_ALIGN                              0
#define TXB_ANATXASTATUS1_TX_ID_BITS                               2
#define TXB_ANATXASTATUS1_TX_ID_SHIFT                              14

/* TxB :: anaTxAStatus1 :: reserved0 [13:00] */
#define TXB_ANATXASTATUS1_RESERVED0_MASK                           0x3fff
#define TXB_ANATXASTATUS1_RESERVED0_ALIGN                          0
#define TXB_ANATXASTATUS1_RESERVED0_BITS                           14
#define TXB_ANATXASTATUS1_RESERVED0_SHIFT                          0


/****************************************************************************
 * TxB :: anaTxAControl1
 ***************************************************************************/
/* TxB :: anaTxAControl1 :: id2c [15:13] */
#define TXB_ANATXACONTROL1_ID2C_MASK                               0xe000
#define TXB_ANATXACONTROL1_ID2C_ALIGN                              0
#define TXB_ANATXACONTROL1_ID2C_BITS                               3
#define TXB_ANATXACONTROL1_ID2C_SHIFT                              13

/* TxB :: anaTxAControl1 :: refl_tx [12:12] */
#define TXB_ANATXACONTROL1_REFL_TX_MASK                            0x1000
#define TXB_ANATXACONTROL1_REFL_TX_ALIGN                           0
#define TXB_ANATXACONTROL1_REFL_TX_BITS                            1
#define TXB_ANATXACONTROL1_REFL_TX_SHIFT                           12

/* TxB :: anaTxAControl1 :: refh_tx [11:11] */
#define TXB_ANATXACONTROL1_REFH_TX_MASK                            0x0800
#define TXB_ANATXACONTROL1_REFH_TX_ALIGN                           0
#define TXB_ANATXACONTROL1_REFH_TX_BITS                            1
#define TXB_ANATXACONTROL1_REFH_TX_SHIFT                           11

/* TxB :: anaTxAControl1 :: newbias_en [10:10] */
#define TXB_ANATXACONTROL1_NEWBIAS_EN_MASK                         0x0400
#define TXB_ANATXACONTROL1_NEWBIAS_EN_ALIGN                        0
#define TXB_ANATXACONTROL1_NEWBIAS_EN_BITS                         1
#define TXB_ANATXACONTROL1_NEWBIAS_EN_SHIFT                        10

/* TxB :: anaTxAControl1 :: drivermode [09:09] */
#define TXB_ANATXACONTROL1_DRIVERMODE_MASK                         0x0200
#define TXB_ANATXACONTROL1_DRIVERMODE_ALIGN                        0
#define TXB_ANATXACONTROL1_DRIVERMODE_BITS                         1
#define TXB_ANATXACONTROL1_DRIVERMODE_SHIFT                        9

/* TxB :: anaTxAControl1 :: vddr_bgb [08:08] */
#define TXB_ANATXACONTROL1_VDDR_BGB_MASK                           0x0100
#define TXB_ANATXACONTROL1_VDDR_BGB_ALIGN                          0
#define TXB_ANATXACONTROL1_VDDR_BGB_BITS                           1
#define TXB_ANATXACONTROL1_VDDR_BGB_SHIFT                          8

/* TxB :: anaTxAControl1 :: ticksel [07:06] */
#define TXB_ANATXACONTROL1_TICKSEL_MASK                            0x00c0
#define TXB_ANATXACONTROL1_TICKSEL_ALIGN                           0
#define TXB_ANATXACONTROL1_TICKSEL_BITS                            2
#define TXB_ANATXACONTROL1_TICKSEL_SHIFT                           6

/* TxB :: anaTxAControl1 :: driver_vcm [05:04] */
#define TXB_ANATXACONTROL1_DRIVER_VCM_MASK                         0x0030
#define TXB_ANATXACONTROL1_DRIVER_VCM_ALIGN                        0
#define TXB_ANATXACONTROL1_DRIVER_VCM_BITS                         2
#define TXB_ANATXACONTROL1_DRIVER_VCM_SHIFT                        4

/* TxB :: anaTxAControl1 :: tx_sel_halfrate [03:03] */
#define TXB_ANATXACONTROL1_TX_SEL_HALFRATE_MASK                    0x0008
#define TXB_ANATXACONTROL1_TX_SEL_HALFRATE_ALIGN                   0
#define TXB_ANATXACONTROL1_TX_SEL_HALFRATE_BITS                    1
#define TXB_ANATXACONTROL1_TX_SEL_HALFRATE_SHIFT                   3

/* TxB :: anaTxAControl1 :: ifullspd [02:00] */
#define TXB_ANATXACONTROL1_IFULLSPD_MASK                           0x0007
#define TXB_ANATXACONTROL1_IFULLSPD_ALIGN                          0
#define TXB_ANATXACONTROL1_IFULLSPD_BITS                           3
#define TXB_ANATXACONTROL1_IFULLSPD_SHIFT                          0


/****************************************************************************
 * TxB :: anaTxAControl2
 ***************************************************************************/
/* TxB :: anaTxAControl2 :: icbuf1t [15:14] */
#define TXB_ANATXACONTROL2_ICBUF1T_MASK                            0xc000
#define TXB_ANATXACONTROL2_ICBUF1T_ALIGN                           0
#define TXB_ANATXACONTROL2_ICBUF1T_BITS                            2
#define TXB_ANATXACONTROL2_ICBUF1T_SHIFT                           14

/* TxB :: anaTxAControl2 :: icbuf2t [13:11] */
#define TXB_ANATXACONTROL2_ICBUF2T_MASK                            0x3800
#define TXB_ANATXACONTROL2_ICBUF2T_ALIGN                           0
#define TXB_ANATXACONTROL2_ICBUF2T_BITS                            3
#define TXB_ANATXACONTROL2_ICBUF2T_SHIFT                           11

/* TxB :: anaTxAControl2 :: imin_predrv [10:10] */
#define TXB_ANATXACONTROL2_IMIN_PREDRV_MASK                        0x0400
#define TXB_ANATXACONTROL2_IMIN_PREDRV_ALIGN                       0
#define TXB_ANATXACONTROL2_IMIN_PREDRV_BITS                        1
#define TXB_ANATXACONTROL2_IMIN_PREDRV_SHIFT                       10

/* TxB :: anaTxAControl2 :: imax_predrv [09:09] */
#define TXB_ANATXACONTROL2_IMAX_PREDRV_MASK                        0x0200
#define TXB_ANATXACONTROL2_IMAX_PREDRV_ALIGN                       0
#define TXB_ANATXACONTROL2_IMAX_PREDRV_BITS                        1
#define TXB_ANATXACONTROL2_IMAX_PREDRV_SHIFT                       9

/* TxB :: anaTxAControl2 :: imode_predrv [08:08] */
#define TXB_ANATXACONTROL2_IMODE_PREDRV_MASK                       0x0100
#define TXB_ANATXACONTROL2_IMODE_PREDRV_ALIGN                      0
#define TXB_ANATXACONTROL2_IMODE_PREDRV_BITS                       1
#define TXB_ANATXACONTROL2_IMODE_PREDRV_SHIFT                      8

/* TxB :: anaTxAControl2 :: i21mux [07:05] */
#define TXB_ANATXACONTROL2_I21MUX_MASK                             0x00e0
#define TXB_ANATXACONTROL2_I21MUX_ALIGN                            0
#define TXB_ANATXACONTROL2_I21MUX_BITS                             3
#define TXB_ANATXACONTROL2_I21MUX_SHIFT                            5

/* TxB :: anaTxAControl2 :: imin_drvr [04:04] */
#define TXB_ANATXACONTROL2_IMIN_DRVR_MASK                          0x0010
#define TXB_ANATXACONTROL2_IMIN_DRVR_ALIGN                         0
#define TXB_ANATXACONTROL2_IMIN_DRVR_BITS                          1
#define TXB_ANATXACONTROL2_IMIN_DRVR_SHIFT                         4

/* TxB :: anaTxAControl2 :: imax_drvr [03:03] */
#define TXB_ANATXACONTROL2_IMAX_DRVR_MASK                          0x0008
#define TXB_ANATXACONTROL2_IMAX_DRVR_ALIGN                         0
#define TXB_ANATXACONTROL2_IMAX_DRVR_BITS                          1
#define TXB_ANATXACONTROL2_IMAX_DRVR_SHIFT                         3

/* TxB :: anaTxAControl2 :: imode_drvr [02:02] */
#define TXB_ANATXACONTROL2_IMODE_DRVR_MASK                         0x0004
#define TXB_ANATXACONTROL2_IMODE_DRVR_ALIGN                        0
#define TXB_ANATXACONTROL2_IMODE_DRVR_BITS                         1
#define TXB_ANATXACONTROL2_IMODE_DRVR_SHIFT                        2

/* TxB :: anaTxAControl2 :: reserved0 [01:00] */
#define TXB_ANATXACONTROL2_RESERVED0_MASK                          0x0003
#define TXB_ANATXACONTROL2_RESERVED0_ALIGN                         0
#define TXB_ANATXACONTROL2_RESERVED0_BITS                          2
#define TXB_ANATXACONTROL2_RESERVED0_SHIFT                         0


/****************************************************************************
 * TxB :: Tx_OS_Driver
 ***************************************************************************/
/* TxB :: Tx_OS_Driver :: preemphasis_post [15:12] */
#define TXB_TX_OS_DRIVER_PREEMPHASIS_POST_MASK                     0xf000
#define TXB_TX_OS_DRIVER_PREEMPHASIS_POST_ALIGN                    0
#define TXB_TX_OS_DRIVER_PREEMPHASIS_POST_BITS                     4
#define TXB_TX_OS_DRIVER_PREEMPHASIS_POST_SHIFT                    12

/* TxB :: Tx_OS_Driver :: Idriver [11:08] */
#define TXB_TX_OS_DRIVER_IDRIVER_MASK                              0x0f00
#define TXB_TX_OS_DRIVER_IDRIVER_ALIGN                             0
#define TXB_TX_OS_DRIVER_IDRIVER_BITS                              4
#define TXB_TX_OS_DRIVER_IDRIVER_SHIFT                             8

/* TxB :: Tx_OS_Driver :: Ipredriver [07:04] */
#define TXB_TX_OS_DRIVER_IPREDRIVER_MASK                           0x00f0
#define TXB_TX_OS_DRIVER_IPREDRIVER_ALIGN                          0
#define TXB_TX_OS_DRIVER_IPREDRIVER_BITS                           4
#define TXB_TX_OS_DRIVER_IPREDRIVER_SHIFT                          4

/* TxB :: Tx_OS_Driver :: preemphasis_pre [03:01] */
#define TXB_TX_OS_DRIVER_PREEMPHASIS_PRE_MASK                      0x000e
#define TXB_TX_OS_DRIVER_PREEMPHASIS_PRE_ALIGN                     0
#define TXB_TX_OS_DRIVER_PREEMPHASIS_PRE_BITS                      3
#define TXB_TX_OS_DRIVER_PREEMPHASIS_PRE_SHIFT                     1

/* TxB :: Tx_OS_Driver :: icbuf1t0 [00:00] */
#define TXB_TX_OS_DRIVER_ICBUF1T0_MASK                             0x0001
#define TXB_TX_OS_DRIVER_ICBUF1T0_ALIGN                            0
#define TXB_TX_OS_DRIVER_ICBUF1T0_BITS                             1
#define TXB_TX_OS_DRIVER_ICBUF1T0_SHIFT                            0


/****************************************************************************
 * TxB :: Tx_BR_Driver
 ***************************************************************************/
/* TxB :: Tx_BR_Driver :: preemphasis_post [15:12] */
#define TXB_TX_BR_DRIVER_PREEMPHASIS_POST_MASK                     0xf000
#define TXB_TX_BR_DRIVER_PREEMPHASIS_POST_ALIGN                    0
#define TXB_TX_BR_DRIVER_PREEMPHASIS_POST_BITS                     4
#define TXB_TX_BR_DRIVER_PREEMPHASIS_POST_SHIFT                    12

/* TxB :: Tx_BR_Driver :: Idriver [11:08] */
#define TXB_TX_BR_DRIVER_IDRIVER_MASK                              0x0f00
#define TXB_TX_BR_DRIVER_IDRIVER_ALIGN                             0
#define TXB_TX_BR_DRIVER_IDRIVER_BITS                              4
#define TXB_TX_BR_DRIVER_IDRIVER_SHIFT                             8

/* TxB :: Tx_BR_Driver :: Ipredriver [07:04] */
#define TXB_TX_BR_DRIVER_IPREDRIVER_MASK                           0x00f0
#define TXB_TX_BR_DRIVER_IPREDRIVER_ALIGN                          0
#define TXB_TX_BR_DRIVER_IPREDRIVER_BITS                           4
#define TXB_TX_BR_DRIVER_IPREDRIVER_SHIFT                          4

/* TxB :: Tx_BR_Driver :: preemphasis_pre [03:01] */
#define TXB_TX_BR_DRIVER_PREEMPHASIS_PRE_MASK                      0x000e
#define TXB_TX_BR_DRIVER_PREEMPHASIS_PRE_ALIGN                     0
#define TXB_TX_BR_DRIVER_PREEMPHASIS_PRE_BITS                      3
#define TXB_TX_BR_DRIVER_PREEMPHASIS_PRE_SHIFT                     1

/* TxB :: Tx_BR_Driver :: icbuf1t0 [00:00] */
#define TXB_TX_BR_DRIVER_ICBUF1T0_MASK                             0x0001
#define TXB_TX_BR_DRIVER_ICBUF1T0_ALIGN                            0
#define TXB_TX_BR_DRIVER_ICBUF1T0_BITS                             1
#define TXB_TX_BR_DRIVER_ICBUF1T0_SHIFT                            0


/****************************************************************************
 * Hypercore_USER_Rx0
 ***************************************************************************/
/****************************************************************************
 * Rx0 :: anaRxStatus
 ***************************************************************************/
/* union - case sigdet_Status [15:00] */
/* Rx0 :: anaRxStatus :: cx4_sigdet [15:15] */
#define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK              0x8000
#define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN             0
#define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS              1
#define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT             15

/* Rx0 :: anaRxStatus :: reserved0 [14:13] */
#define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK               0x6000
#define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN              0
#define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS               2
#define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT              13

/* Rx0 :: anaRxStatus :: rxSeqDone [12:12] */
#define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK               0x1000
#define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN              0
#define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS               1
#define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT              12

/* Rx0 :: anaRxStatus :: rx_sigdet_ll [11:11] */
#define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK            0x0800
#define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN           0
#define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS            1
#define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT           11

/* Rx0 :: anaRxStatus :: cs4_sigdet_ll [10:10] */
#define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK           0x0400
#define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN          0
#define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS           1
#define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT          10

/* Rx0 :: anaRxStatus :: rx_reset [09:09] */
#define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK                0x0200
#define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN               0
#define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS                1
#define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT               9

/* Rx0 :: anaRxStatus :: rx_pwrdn [08:08] */
#define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK                0x0100
#define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN               0
#define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS                1
#define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT               8

/* Rx0 :: anaRxStatus :: reserved1 [07:00] */
#define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK               0x00ff
#define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN              0
#define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS               8
#define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT              0


/* union - case sync_Status [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:11] */
#define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK                 0xf800
#define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN                0
#define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS                 5
#define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT                11

/* Rx0 :: anaRxStatus :: test_acq_en [10:10] */
#define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK               0x0400
#define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN              0
#define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS               1
#define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT              10

/* Rx0 :: anaRxStatus :: reserved1 [09:09] */
#define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK                 0x0200
#define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN                0
#define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS                 1
#define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT                9

/* Rx0 :: anaRxStatus :: rxSeqStart [08:08] */
#define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK                0x0100
#define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN               0
#define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS                1
#define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT               8

/* Rx0 :: anaRxStatus :: mux_comadj_sync_status [07:07] */
#define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK    0x0080
#define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN   0
#define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS    1
#define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT   7

/* Rx0 :: anaRxStatus :: sync_status [06:06] */
#define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK               0x0040
#define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN              0
#define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS               1
#define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT              6

/* Rx0 :: anaRxStatus :: rx_sigdet [05:05] */
#define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK                 0x0020
#define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN                0
#define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS                 1
#define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT                5

/* Rx0 :: anaRxStatus :: reserved2 [04:03] */
#define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK                 0x0018
#define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN                0
#define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS                 2
#define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT                3

/* Rx0 :: anaRxStatus :: saturate_status [02:02] */
#define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK           0x0004
#define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN          0
#define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS           1
#define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT          2

/* Rx0 :: anaRxStatus :: cx4_sigdet [01:01] */
#define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK                0x0002
#define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN               0
#define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS                1
#define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT               1

/* Rx0 :: anaRxStatus :: rxSeqDone [00:00] */
#define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK                 0x0001
#define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN                0
#define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS                 1
#define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT                0


/* union - case rxTestSel_0 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:10] */
#define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK                 0xfc00
#define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN                0
#define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS                 6
#define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT                10

/* Rx0 :: anaRxStatus :: indck_mode_en [09:09] */
#define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK             0x0200
#define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN            0
#define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS             1
#define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT            9

/* Rx0 :: anaRxStatus :: pci_mode_en [08:08] */
#define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK               0x0100
#define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN              0
#define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS               1
#define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT              8

/* Rx0 :: anaRxStatus :: rx_polarity [07:07] */
#define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK               0x0080
#define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN              0
#define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS               1
#define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT              7

/* Rx0 :: anaRxStatus :: rxpol_flip [06:06] */
#define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK                0x0040
#define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN               0
#define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS                1
#define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT               6

/* Rx0 :: anaRxStatus :: comma_mask [05:05] */
#define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK                0x0020
#define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN               0
#define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS                1
#define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT               5

/* Rx0 :: anaRxStatus :: link_en_r [04:04] */
#define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK                 0x0010
#define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN                0
#define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS                 1
#define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT                4

/* Rx0 :: anaRxStatus :: comma_adj_en [03:03] */
#define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK              0x0008
#define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN             0
#define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS              1
#define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT             3

/* Rx0 :: anaRxStatus :: comma_adj_en_ext [02:02] */
#define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK          0x0004
#define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN         0
#define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS          1
#define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT         2

/* Rx0 :: anaRxStatus :: reserved1 [01:00] */
#define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK                 0x0003
#define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN                0
#define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS                 2
#define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT                0


/* union - case rxTestSel_1 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:05] */
#define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK                 0xffe0
#define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN                0
#define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS                 11
#define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT                5

/* Rx0 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */
#define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK             0x0010
#define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN            0
#define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS             1
#define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT            4

/* Rx0 :: anaRxStatus :: freq_sel_PC [03:03] */
#define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK               0x0008
#define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN              0
#define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS               1
#define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT              3

/* Rx0 :: anaRxStatus :: freq_sel_SM [02:02] */
#define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK               0x0004
#define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN              0
#define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS               1
#define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT              2

/* Rx0 :: anaRxStatus :: integ_mode_SM [01:00] */
#define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK             0x0003
#define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN            0
#define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS             2
#define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT            0


/* union - case scale_Status [15:00] */
/* Rx0 :: anaRxStatus :: prop_scale [15:12] */
#define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK               0xf000
#define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN              0
#define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS               4
#define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT              12

/* Rx0 :: anaRxStatus :: integ_scale [11:08] */
#define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK              0x0f00
#define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN             0
#define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS              4
#define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT             8

/* Rx0 :: anaRxStatus :: prop_scale_acq [07:04] */
#define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK           0x00f0
#define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN          0
#define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS           4
#define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT          4

/* Rx0 :: anaRxStatus :: integ_scale_acq [03:00] */
#define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK          0x000f
#define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN         0
#define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS          4
#define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT         0


/* union - case adc_CdrStatus1 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:07] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK              0xff80
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN             0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS              9
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT             7

/* Rx0 :: anaRxStatus :: rxMuxCkSel [06:06] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK             0x0040
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN            0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS             1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT            6

/* Rx0 :: anaRxStatus :: glpbk_combo [05:05] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK            0x0020
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN           0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS            1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT           5

/* Rx0 :: anaRxStatus :: clockSwitchSel [04:04] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK         0x0010
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN        0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS         1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT        4

/* Rx0 :: anaRxStatus :: rxck_tst [03:03] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK               0x0008
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN              0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS               1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT              3

/* Rx0 :: anaRxStatus :: rxck_i [02:02] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK                 0x0004
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN                0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS                 1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT                2

/* Rx0 :: anaRxStatus :: refclk [01:01] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK                 0x0002
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN                0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS                 1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT                1

/* Rx0 :: anaRxStatus :: pll_bypass [00:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK             0x0001
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN            0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS             1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT            0


/* union - case adc_CdrStatus2 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:06] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK              0xffc0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN             0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS              10
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT             6

/* Rx0 :: anaRxStatus :: rxMuxCkSel [05:05] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK             0x0020
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN            0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS             1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT            5

/* Rx0 :: anaRxStatus :: rxSeqStart [04:04] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK             0x0010
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN            0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS             1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT            4

/* Rx0 :: anaRxStatus :: reserved1 [03:01] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK              0x000e
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN             0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS              3
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT             1

/* Rx0 :: anaRxStatus :: rxSeqDone [00:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK              0x0001
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN             0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS              1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT             0


/* union - case adc_CdrStatus3 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:04] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK              0xfff0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN             0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS              12
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT             4

/* Rx0 :: anaRxStatus :: rxSeqStart [03:03] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK             0x0008
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN            0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS             1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT            3

/* Rx0 :: anaRxStatus :: reserved1 [02:01] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK              0x0006
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN             0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS              2
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT             1

/* Rx0 :: anaRxStatus :: allow_increment_PC [00:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK     0x0001
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN    0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS     1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT    0


/* union - case adc_CdrStatus4 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:08] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK              0xff00
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN             0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS              8
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT             8

/* Rx0 :: anaRxStatus :: rx_pwrdn [07:07] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK               0x0080
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN              0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS               1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT              7

/* Rx0 :: anaRxStatus :: freq_sel [06:06] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK               0x0040
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN              0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS               1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT              6

/* Rx0 :: anaRxStatus :: pll_lock_rstb [05:05] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK          0x0020
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN         0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS          1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT         5

/* Rx0 :: anaRxStatus :: pwrdn [04:04] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK                  0x0010
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                 0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS                  1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                 4

/* Rx0 :: anaRxStatus :: reserved1 [03:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK              0x000f
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN             0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS              4
#define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT             0


/* union - case adc_CdrStatus5 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK              0xffff
#define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN             0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS              16
#define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT             0


/* union - case adc_CdrStatus6 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:05] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK              0xffe0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN             0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS              11
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT             5

/* Rx0 :: anaRxStatus :: rx_reset [04:04] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK               0x0010
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN              0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS               1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT              4

/* Rx0 :: anaRxStatus :: rx_pwrdn [03:03] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK               0x0008
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN              0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS               1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT              3

/* Rx0 :: anaRxStatus :: reset_anlg [02:02] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK             0x0004
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN            0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS             1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT            2

/* Rx0 :: anaRxStatus :: pwrdn_rx [01:01] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK               0x0002
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN              0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS               1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT              1

/* Rx0 :: anaRxStatus :: pwrdn_pll [00:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK              0x0001
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN             0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS              1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT             0


/* union - case adc_CdrStatus7e [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:05] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK             0xffe0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN            0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS             11
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT            5

/* Rx0 :: anaRxStatus :: rxck0_even [04:04] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK            0x0010
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN           0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS            1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT           4

/* Rx0 :: anaRxStatus :: rxck1_even [03:03] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK            0x0008
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN           0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS            1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT           3

/* Rx0 :: anaRxStatus :: comdet_even [02:02] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK           0x0004
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN          0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS           1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT          2

/* Rx0 :: anaRxStatus :: en_cdet_even [01:01] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK          0x0002
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN         0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS          1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT         1

/* Rx0 :: anaRxStatus :: comma_adj_en_even [00:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK     0x0001
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN    0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS     1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT    0


/* union - case adc_CdrStatus7o [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:05] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK             0xffe0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN            0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS             11
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT            5

/* Rx0 :: anaRxStatus :: rxck0_odd [04:04] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK             0x0010
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN            0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS             1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT            4

/* Rx0 :: anaRxStatus :: rxck1_odd [03:03] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK             0x0008
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN            0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS             1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT            3

/* Rx0 :: anaRxStatus :: comdet_odd [02:02] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK            0x0004
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN           0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS            1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT           2

/* Rx0 :: anaRxStatus :: en_cdet_odd [01:01] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK           0x0002
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN          0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS           1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT          1

/* Rx0 :: anaRxStatus :: comma_adj_en_odd [00:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK      0x0001
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN     0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS      1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT     0


/* union - case adc_CdrStatus8 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:01] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK              0xfffe
#define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN             0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS              15
#define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT             1

/* Rx0 :: anaRxStatus :: sigdet [00:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK                 0x0001
#define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN                0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS                 1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT                0


/* union - case adc_CdrStatus9 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK              0xffff
#define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN             0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS              16
#define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT             0


/* union - case adc_CdrStatus10 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:07] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK             0xff80
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN            0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS             9
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT            7

/* Rx0 :: anaRxStatus :: prbs_en [06:06] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK               0x0040
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN              0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS               1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT              6

/* Rx0 :: anaRxStatus :: rstb_tst [05:05] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK              0x0020
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN             0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS              1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT             5

/* Rx0 :: anaRxStatus :: reserved1 [04:04] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK             0x0010
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN            0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS             1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT            4

/* Rx0 :: anaRxStatus :: prbs_state [03:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK            0x000f
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN           0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS            4
#define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT           0


/* union - case adc_CdrStatus11 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK             0xffff
#define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN            0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS             16
#define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT            0


/* union - case adc_CdrStatus12_1 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:06] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK           0xffc0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN          0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS           10
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT          6

/* Rx0 :: anaRxStatus :: enable4 [05:05] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK             0x0020
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN            0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS             1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT            5

/* Rx0 :: anaRxStatus :: radr_test [04:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK           0x001f
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN          0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS           5
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT          0


/* union - case adc_CdrStatus12_2 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:05] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK           0xffe0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN          0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS           11
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT          5

/* Rx0 :: anaRxStatus :: wadr_test [04:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK           0x001f
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN          0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS           5
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT          0


/* union - case adc_CdrStatus12_3 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:06] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK           0xffc0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN          0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS           10
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT          6

/* Rx0 :: anaRxStatus :: rxck_66B_tmux [05:05] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK       0x0020
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN      0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS       1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT      5

/* Rx0 :: anaRxStatus :: rstb_66B [04:04] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK            0x0010
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN           0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS            1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT           4

/* Rx0 :: anaRxStatus :: prstb_66B_mux [03:03] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK       0x0008
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN      0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS       1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT      3

/* Rx0 :: anaRxStatus :: rxck_i66_tmux [02:02] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK       0x0004
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN      0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS       1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT      2

/* Rx0 :: anaRxStatus :: rstb_i66 [01:01] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK            0x0002
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN           0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS            1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT           1

/* Rx0 :: anaRxStatus :: prstb_i66_mux [00:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK       0x0001
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN      0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS       1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT      0


/* union - case adc_CdrStatus12_4 [15:00] */
/* Rx0 :: anaRxStatus :: reserved0 [15:04] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK           0xfff0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN          0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS           12
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT          4

/* Rx0 :: anaRxStatus :: rfifo_error_r [03:02] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK       0x000c
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN      0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS       2
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT      2

/* Rx0 :: anaRxStatus :: rfifo_unflow [01:01] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK        0x0002
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN       0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS        1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT       1

/* Rx0 :: anaRxStatus :: rfifo_ovflow [00:00] */
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK        0x0001
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN       0
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS        1
#define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT       0


/* union - case integ_Status [15:00] */
/* Rx0 :: anaRxStatus :: integ_status [15:00] */
#define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK             0xffff
#define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN            0
#define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS             16
#define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT            0


/* union - case vco_Status [15:00] */
/* Rx0 :: anaRxStatus :: vco_status [15:00] */
#define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK                 0xffff
#define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN                0
#define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS                 16
#define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT                0


/* union - case prbs_Status [15:00] */
/* Rx0 :: anaRxStatus :: prbs_lock [15:15] */
#define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK                 0x8000
#define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN                0
#define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS                 1
#define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT                15

/* Rx0 :: anaRxStatus :: prbs_stky [14:14] */
#define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK                 0x4000
#define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN                0
#define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS                 1
#define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT                14

/* Rx0 :: anaRxStatus :: ptbs_errors [13:00] */
#define RX0_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK               0x3fff
#define RX0_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN              0
#define RX0_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS               14
#define RX0_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT              0



/****************************************************************************
 * Rx0 :: anaRxControl
 ***************************************************************************/
/* Rx0 :: anaRxControl :: reserved0 [15:10] */
#define RX0_ANARXCONTROL_RESERVED0_MASK                            0xfc00
#define RX0_ANARXCONTROL_RESERVED0_ALIGN                           0
#define RX0_ANARXCONTROL_RESERVED0_BITS                            6
#define RX0_ANARXCONTROL_RESERVED0_SHIFT                           10

/* Rx0 :: anaRxControl :: override_sigdet_en [09:09] */
#define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK                   0x0200
#define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN                  0
#define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS                   1
#define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT                  9

/* Rx0 :: anaRxControl :: override_sigdet_val [08:08] */
#define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK                  0x0100
#define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN                 0
#define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS                  1
#define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT                 8

/* Rx0 :: anaRxControl :: reserved1 [07:03] */
#define RX0_ANARXCONTROL_RESERVED1_MASK                            0x00f8
#define RX0_ANARXCONTROL_RESERVED1_ALIGN                           0
#define RX0_ANARXCONTROL_RESERVED1_BITS                            5
#define RX0_ANARXCONTROL_RESERVED1_SHIFT                           3

/* Rx0 :: anaRxControl :: status_sel [02:00] */
#define RX0_ANARXCONTROL_STATUS_SEL_MASK                           0x0007
#define RX0_ANARXCONTROL_STATUS_SEL_ALIGN                          0
#define RX0_ANARXCONTROL_STATUS_SEL_BITS                           3
#define RX0_ANARXCONTROL_STATUS_SEL_SHIFT                          0
#define RX0_ANARXCONTROL_STATUS_SEL_sigdetStatus                   0
#define RX0_ANARXCONTROL_STATUS_SEL_syncStatus                     1
#define RX0_ANARXCONTROL_STATUS_SEL_rxTestSel                      2
#define RX0_ANARXCONTROL_STATUS_SEL_scaleStatus                    3
#define RX0_ANARXCONTROL_STATUS_SEL_adcCdrStatus                   4
#define RX0_ANARXCONTROL_STATUS_SEL_integStatus                    5
#define RX0_ANARXCONTROL_STATUS_SEL_vcoStatus                      6
#define RX0_ANARXCONTROL_STATUS_SEL_prbsStatus                     7


/****************************************************************************
 * Rx0 :: anaRxTest
 ***************************************************************************/
/* Rx0 :: anaRxTest :: sigdet_mux_SM [15:12] */
#define RX0_ANARXTEST_SIGDET_MUX_SM_MASK                           0xf000
#define RX0_ANARXTEST_SIGDET_MUX_SM_ALIGN                          0
#define RX0_ANARXTEST_SIGDET_MUX_SM_BITS                           4
#define RX0_ANARXTEST_SIGDET_MUX_SM_SHIFT                          12

/* Rx0 :: anaRxTest :: reserved0 [11:09] */
#define RX0_ANARXTEST_RESERVED0_MASK                               0x0e00
#define RX0_ANARXTEST_RESERVED0_ALIGN                              0
#define RX0_ANARXTEST_RESERVED0_BITS                               3
#define RX0_ANARXTEST_RESERVED0_SHIFT                              9

/* Rx0 :: anaRxTest :: tpctrl_SM [08:04] */
#define RX0_ANARXTEST_TPCTRL_SM_MASK                               0x01f0
#define RX0_ANARXTEST_TPCTRL_SM_ALIGN                              0
#define RX0_ANARXTEST_TPCTRL_SM_BITS                               5
#define RX0_ANARXTEST_TPCTRL_SM_SHIFT                              4

/* Rx0 :: anaRxTest :: testMuxSelect_SM [03:00] */
#define RX0_ANARXTEST_TESTMUXSELECT_SM_MASK                        0x000f
#define RX0_ANARXTEST_TESTMUXSELECT_SM_ALIGN                       0
#define RX0_ANARXTEST_TESTMUXSELECT_SM_BITS                        4
#define RX0_ANARXTEST_TESTMUXSELECT_SM_SHIFT                       0


/****************************************************************************
 * Rx0 :: anaRxControl1G
 ***************************************************************************/
/* Rx0 :: anaRxControl1G :: fpat_md [15:15] */
#define RX0_ANARXCONTROL1G_FPAT_MD_MASK                            0x8000
#define RX0_ANARXCONTROL1G_FPAT_MD_ALIGN                           0
#define RX0_ANARXCONTROL1G_FPAT_MD_BITS                            1
#define RX0_ANARXCONTROL1G_FPAT_MD_SHIFT                           15

/* Rx0 :: anaRxControl1G :: pkt_count_en [14:14] */
#define RX0_ANARXCONTROL1G_PKT_COUNT_EN_MASK                       0x4000
#define RX0_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN                      0
#define RX0_ANARXCONTROL1G_PKT_COUNT_EN_BITS                       1
#define RX0_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT                      14

/* Rx0 :: anaRxControl1G :: staMuxRegDis [13:13] */
#define RX0_ANARXCONTROL1G_STAMUXREGDIS_MASK                       0x2000
#define RX0_ANARXCONTROL1G_STAMUXREGDIS_ALIGN                      0
#define RX0_ANARXCONTROL1G_STAMUXREGDIS_BITS                       1
#define RX0_ANARXCONTROL1G_STAMUXREGDIS_SHIFT                      13

/* Rx0 :: anaRxControl1G :: prbs_clr_dis [12:12] */
#define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_MASK                       0x1000
#define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN                      0
#define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_BITS                       1
#define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT                      12

/* Rx0 :: anaRxControl1G :: rxd_dec_sel [11:11] */
#define RX0_ANARXCONTROL1G_RXD_DEC_SEL_MASK                        0x0800
#define RX0_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN                       0
#define RX0_ANARXCONTROL1G_RXD_DEC_SEL_BITS                        1
#define RX0_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT                       11

/* Rx0 :: anaRxControl1G :: cgbad_tst [10:10] */
#define RX0_ANARXCONTROL1G_CGBAD_TST_MASK                          0x0400
#define RX0_ANARXCONTROL1G_CGBAD_TST_ALIGN                         0
#define RX0_ANARXCONTROL1G_CGBAD_TST_BITS                          1
#define RX0_ANARXCONTROL1G_CGBAD_TST_SHIFT                         10

/* Rx0 :: anaRxControl1G :: Emon_en [09:09] */
#define RX0_ANARXCONTROL1G_EMON_EN_MASK                            0x0200
#define RX0_ANARXCONTROL1G_EMON_EN_ALIGN                           0
#define RX0_ANARXCONTROL1G_EMON_EN_BITS                            1
#define RX0_ANARXCONTROL1G_EMON_EN_SHIFT                           9

/* Rx0 :: anaRxControl1G :: prbs_en [08:08] */
#define RX0_ANARXCONTROL1G_PRBS_EN_MASK                            0x0100
#define RX0_ANARXCONTROL1G_PRBS_EN_ALIGN                           0
#define RX0_ANARXCONTROL1G_PRBS_EN_BITS                            1
#define RX0_ANARXCONTROL1G_PRBS_EN_SHIFT                           8

/* Rx0 :: anaRxControl1G :: cgbad_en [07:07] */
#define RX0_ANARXCONTROL1G_CGBAD_EN_MASK                           0x0080
#define RX0_ANARXCONTROL1G_CGBAD_EN_ALIGN                          0
#define RX0_ANARXCONTROL1G_CGBAD_EN_BITS                           1
#define RX0_ANARXCONTROL1G_CGBAD_EN_SHIFT                          7

/* Rx0 :: anaRxControl1G :: cstretch [06:06] */
#define RX0_ANARXCONTROL1G_CSTRETCH_MASK                           0x0040
#define RX0_ANARXCONTROL1G_CSTRETCH_ALIGN                          0
#define RX0_ANARXCONTROL1G_CSTRETCH_BITS                           1
#define RX0_ANARXCONTROL1G_CSTRETCH_SHIFT                          6

/* Rx0 :: anaRxControl1G :: comma_low_byte_SM [05:05] */
#define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK                  0x0020
#define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN                 0
#define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS                  1
#define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT                 5

/* Rx0 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */
#define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK               0x0010
#define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN              0
#define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS               1
#define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT              4

/* Rx0 :: anaRxControl1G :: reserved0 [03:02] */
#define RX0_ANARXCONTROL1G_RESERVED0_MASK                          0x000c
#define RX0_ANARXCONTROL1G_RESERVED0_ALIGN                         0
#define RX0_ANARXCONTROL1G_RESERVED0_BITS                          2
#define RX0_ANARXCONTROL1G_RESERVED0_SHIFT                         2

/* Rx0 :: anaRxControl1G :: freq_sel_force [01:01] */
#define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK                     0x0002
#define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN                    0
#define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS                     1
#define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT                    1

/* Rx0 :: anaRxControl1G :: freq_sel [00:00] */
#define RX0_ANARXCONTROL1G_FREQ_SEL_MASK                           0x0001
#define RX0_ANARXCONTROL1G_FREQ_SEL_ALIGN                          0
#define RX0_ANARXCONTROL1G_FREQ_SEL_BITS                           1
#define RX0_ANARXCONTROL1G_FREQ_SEL_SHIFT                          0


/****************************************************************************
 * Rx0 :: anaRxControlPci
 ***************************************************************************/
/* Rx0 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK                0x8000
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN               0
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS                1
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT               15

/* Rx0 :: anaRxControlPci :: comma_mask_force_r [14:14] */
#define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK                0x4000
#define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN               0
#define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS                1
#define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT               14

/* Rx0 :: anaRxControlPci :: comma_mask_r [13:13] */
#define RX0_ANARXCONTROLPCI_COMMA_MASK_R_MASK                      0x2000
#define RX0_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN                     0
#define RX0_ANARXCONTROLPCI_COMMA_MASK_R_BITS                      1
#define RX0_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT                     13

/* Rx0 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */
#define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK         0x1000
#define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN        0
#define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS         1
#define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT        12

/* Rx0 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */
#define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK            0x0800
#define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN           0
#define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS            1
#define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT           11

/* Rx0 :: anaRxControlPci :: sync_status_force_r [10:10] */
#define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK               0x0400
#define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN              0
#define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS               1
#define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT              10

/* Rx0 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK         0x0200
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN        0
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS         1
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT        9

/* Rx0 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK        0x0100
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN       0
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS        1
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT       8

/* Rx0 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK           0x0080
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN          0
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS           1
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT          7

/* Rx0 :: anaRxControlPci :: comma_adj_en_r [06:06] */
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK                    0x0040
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN                   0
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS                    1
#define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT                   6

/* Rx0 :: anaRxControlPci :: link_en_force_SM [05:05] */
#define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK                  0x0020
#define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN                 0
#define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS                  1
#define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT                 5

/* Rx0 :: anaRxControlPci :: link_en_r [04:04] */
#define RX0_ANARXCONTROLPCI_LINK_EN_R_MASK                         0x0010
#define RX0_ANARXCONTROLPCI_LINK_EN_R_ALIGN                        0
#define RX0_ANARXCONTROLPCI_LINK_EN_R_BITS                         1
#define RX0_ANARXCONTROLPCI_LINK_EN_R_SHIFT                        4

/* Rx0 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */
#define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK              0x0008
#define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN             0
#define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS              1
#define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT             3

/* Rx0 :: anaRxControlPci :: rx_polarity_r [02:02] */
#define RX0_ANARXCONTROLPCI_RX_POLARITY_R_MASK                     0x0004
#define RX0_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN                    0
#define RX0_ANARXCONTROLPCI_RX_POLARITY_R_BITS                     1
#define RX0_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT                    2

/* Rx0 :: anaRxControlPci :: integ_mode_SM [01:00] */
#define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_MASK                     0x0003
#define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN                    0
#define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_BITS                     2
#define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT                    0


/****************************************************************************
 * Rx0 :: anaRxAstatus
 ***************************************************************************/
/* Rx0 :: anaRxAstatus :: sigdet [15:15] */
#define RX0_ANARXASTATUS_SIGDET_MASK                               0x8000
#define RX0_ANARXASTATUS_SIGDET_ALIGN                              0
#define RX0_ANARXASTATUS_SIGDET_BITS                               1
#define RX0_ANARXASTATUS_SIGDET_SHIFT                              15

/* Rx0 :: anaRxAstatus :: rx_pf [14:12] */
#define RX0_ANARXASTATUS_RX_PF_MASK                                0x7000
#define RX0_ANARXASTATUS_RX_PF_ALIGN                               0
#define RX0_ANARXASTATUS_RX_PF_BITS                                3
#define RX0_ANARXASTATUS_RX_PF_SHIFT                               12

/* Rx0 :: anaRxAstatus :: dfe [11:06] */
#define RX0_ANARXASTATUS_DFE_MASK                                  0x0fc0
#define RX0_ANARXASTATUS_DFE_ALIGN                                 0
#define RX0_ANARXASTATUS_DFE_BITS                                  6
#define RX0_ANARXASTATUS_DFE_SHIFT                                 6

/* Rx0 :: anaRxAstatus :: reserved0 [05:05] */
#define RX0_ANARXASTATUS_RESERVED0_MASK                            0x0020
#define RX0_ANARXASTATUS_RESERVED0_ALIGN                           0
#define RX0_ANARXASTATUS_RESERVED0_BITS                            1
#define RX0_ANARXASTATUS_RESERVED0_SHIFT                           5

/* Rx0 :: anaRxAstatus :: vga [04:00] */
#define RX0_ANARXASTATUS_VGA_MASK                                  0x001f
#define RX0_ANARXASTATUS_VGA_ALIGN                                 0
#define RX0_ANARXASTATUS_VGA_BITS                                  5
#define RX0_ANARXASTATUS_VGA_SHIFT                                 0


/****************************************************************************
 * Rx0 :: anaRxAControl1
 ***************************************************************************/
/* Rx0 :: anaRxAControl1 :: imode_vcm [15:15] */
#define RX0_ANARXACONTROL1_IMODE_VCM_MASK                          0x8000
#define RX0_ANARXACONTROL1_IMODE_VCM_ALIGN                         0
#define RX0_ANARXACONTROL1_IMODE_VCM_BITS                          1
#define RX0_ANARXACONTROL1_IMODE_VCM_SHIFT                         15

/* Rx0 :: anaRxAControl1 :: imin_vcm [14:14] */
#define RX0_ANARXACONTROL1_IMIN_VCM_MASK                           0x4000
#define RX0_ANARXACONTROL1_IMIN_VCM_ALIGN                          0
#define RX0_ANARXACONTROL1_IMIN_VCM_BITS                           1
#define RX0_ANARXACONTROL1_IMIN_VCM_SHIFT                          14

/* Rx0 :: anaRxAControl1 :: imax_sigdet [13:13] */
#define RX0_ANARXACONTROL1_IMAX_SIGDET_MASK                        0x2000
#define RX0_ANARXACONTROL1_IMAX_SIGDET_ALIGN                       0
#define RX0_ANARXACONTROL1_IMAX_SIGDET_BITS                        1
#define RX0_ANARXACONTROL1_IMAX_SIGDET_SHIFT                       13

/* Rx0 :: anaRxAControl1 :: imode_sigdet [12:12] */
#define RX0_ANARXACONTROL1_IMODE_SIGDET_MASK                       0x1000
#define RX0_ANARXACONTROL1_IMODE_SIGDET_ALIGN                      0
#define RX0_ANARXACONTROL1_IMODE_SIGDET_BITS                       1
#define RX0_ANARXACONTROL1_IMODE_SIGDET_SHIFT                      12

/* Rx0 :: anaRxAControl1 :: imin_sigdet [11:11] */
#define RX0_ANARXACONTROL1_IMIN_SIGDET_MASK                        0x0800
#define RX0_ANARXACONTROL1_IMIN_SIGDET_ALIGN                       0
#define RX0_ANARXACONTROL1_IMIN_SIGDET_BITS                        1
#define RX0_ANARXACONTROL1_IMIN_SIGDET_SHIFT                       11

/* Rx0 :: anaRxAControl1 :: refh_rx [10:10] */
#define RX0_ANARXACONTROL1_REFH_RX_MASK                            0x0400
#define RX0_ANARXACONTROL1_REFH_RX_ALIGN                           0
#define RX0_ANARXACONTROL1_REFH_RX_BITS                            1
#define RX0_ANARXACONTROL1_REFH_RX_SHIFT                           10

/* Rx0 :: anaRxAControl1 :: refl_rx [09:09] */
#define RX0_ANARXACONTROL1_REFL_RX_MASK                            0x0200
#define RX0_ANARXACONTROL1_REFL_RX_ALIGN                           0
#define RX0_ANARXACONTROL1_REFL_RX_BITS                            1
#define RX0_ANARXACONTROL1_REFL_RX_SHIFT                           9

/* Rx0 :: anaRxAControl1 :: tport_en [08:08] */
#define RX0_ANARXACONTROL1_TPORT_EN_MASK                           0x0100
#define RX0_ANARXACONTROL1_TPORT_EN_ALIGN                          0
#define RX0_ANARXACONTROL1_TPORT_EN_BITS                           1
#define RX0_ANARXACONTROL1_TPORT_EN_SHIFT                          8

/* Rx0 :: anaRxAControl1 :: vddrb_bg [07:07] */
#define RX0_ANARXACONTROL1_VDDRB_BG_MASK                           0x0080
#define RX0_ANARXACONTROL1_VDDRB_BG_ALIGN                          0
#define RX0_ANARXACONTROL1_VDDRB_BG_BITS                           1
#define RX0_ANARXACONTROL1_VDDRB_BG_SHIFT                          7

/* Rx0 :: anaRxAControl1 :: sig_pwrdn [06:06] */
#define RX0_ANARXACONTROL1_SIG_PWRDN_MASK                          0x0040
#define RX0_ANARXACONTROL1_SIG_PWRDN_ALIGN                         0
#define RX0_ANARXACONTROL1_SIG_PWRDN_BITS                          1
#define RX0_ANARXACONTROL1_SIG_PWRDN_SHIFT                         6

/* Rx0 :: anaRxAControl1 :: offset_ctrl [05:03] */
#define RX0_ANARXACONTROL1_OFFSET_CTRL_MASK                        0x0038
#define RX0_ANARXACONTROL1_OFFSET_CTRL_ALIGN                       0
#define RX0_ANARXACONTROL1_OFFSET_CTRL_BITS                        3
#define RX0_ANARXACONTROL1_OFFSET_CTRL_SHIFT                       3

/* Rx0 :: anaRxAControl1 :: offset_sel [02:02] */
#define RX0_ANARXACONTROL1_OFFSET_SEL_MASK                         0x0004
#define RX0_ANARXACONTROL1_OFFSET_SEL_ALIGN                        0
#define RX0_ANARXACONTROL1_OFFSET_SEL_BITS                         1
#define RX0_ANARXACONTROL1_OFFSET_SEL_SHIFT                        2

/* Rx0 :: anaRxAControl1 :: reserved0 [01:00] */
#define RX0_ANARXACONTROL1_RESERVED0_MASK                          0x0003
#define RX0_ANARXACONTROL1_RESERVED0_ALIGN                         0
#define RX0_ANARXACONTROL1_RESERVED0_BITS                          2
#define RX0_ANARXACONTROL1_RESERVED0_SHIFT                         0


/****************************************************************************
 * Rx0 :: anaRxAControl2
 ***************************************************************************/
/* Rx0 :: anaRxAControl2 :: imax_clkbuf [15:15] */
#define RX0_ANARXACONTROL2_IMAX_CLKBUF_MASK                        0x8000
#define RX0_ANARXACONTROL2_IMAX_CLKBUF_ALIGN                       0
#define RX0_ANARXACONTROL2_IMAX_CLKBUF_BITS                        1
#define RX0_ANARXACONTROL2_IMAX_CLKBUF_SHIFT                       15

/* Rx0 :: anaRxAControl2 :: imode_clkbuf [14:14] */
#define RX0_ANARXACONTROL2_IMODE_CLKBUF_MASK                       0x4000
#define RX0_ANARXACONTROL2_IMODE_CLKBUF_ALIGN                      0
#define RX0_ANARXACONTROL2_IMODE_CLKBUF_BITS                       1
#define RX0_ANARXACONTROL2_IMODE_CLKBUF_SHIFT                      14

/* Rx0 :: anaRxAControl2 :: imin_clkbuf [13:13] */
#define RX0_ANARXACONTROL2_IMIN_CLKBUF_MASK                        0x2000
#define RX0_ANARXACONTROL2_IMIN_CLKBUF_ALIGN                       0
#define RX0_ANARXACONTROL2_IMIN_CLKBUF_BITS                        1
#define RX0_ANARXACONTROL2_IMIN_CLKBUF_SHIFT                       13

/* Rx0 :: anaRxAControl2 :: imax_eqfl [12:12] */
#define RX0_ANARXACONTROL2_IMAX_EQFL_MASK                          0x1000
#define RX0_ANARXACONTROL2_IMAX_EQFL_ALIGN                         0
#define RX0_ANARXACONTROL2_IMAX_EQFL_BITS                          1
#define RX0_ANARXACONTROL2_IMAX_EQFL_SHIFT                         12

/* Rx0 :: anaRxAControl2 :: imode_eqfl [11:11] */
#define RX0_ANARXACONTROL2_IMODE_EQFL_MASK                         0x0800
#define RX0_ANARXACONTROL2_IMODE_EQFL_ALIGN                        0
#define RX0_ANARXACONTROL2_IMODE_EQFL_BITS                         1
#define RX0_ANARXACONTROL2_IMODE_EQFL_SHIFT                        11

/* Rx0 :: anaRxAControl2 :: imin_eqfl [10:10] */
#define RX0_ANARXACONTROL2_IMIN_EQFL_MASK                          0x0400
#define RX0_ANARXACONTROL2_IMIN_EQFL_ALIGN                         0
#define RX0_ANARXACONTROL2_IMIN_EQFL_BITS                          1
#define RX0_ANARXACONTROL2_IMIN_EQFL_SHIFT                         10

/* Rx0 :: anaRxAControl2 :: imax_dfesum [09:09] */
#define RX0_ANARXACONTROL2_IMAX_DFESUM_MASK                        0x0200
#define RX0_ANARXACONTROL2_IMAX_DFESUM_ALIGN                       0
#define RX0_ANARXACONTROL2_IMAX_DFESUM_BITS                        1
#define RX0_ANARXACONTROL2_IMAX_DFESUM_SHIFT                       9

/* Rx0 :: anaRxAControl2 :: imode_dfesum [08:08] */
#define RX0_ANARXACONTROL2_IMODE_DFESUM_MASK                       0x0100
#define RX0_ANARXACONTROL2_IMODE_DFESUM_ALIGN                      0
#define RX0_ANARXACONTROL2_IMODE_DFESUM_BITS                       1
#define RX0_ANARXACONTROL2_IMODE_DFESUM_SHIFT                      8

/* Rx0 :: anaRxAControl2 :: imin_dfesum [07:07] */
#define RX0_ANARXACONTROL2_IMIN_DFESUM_MASK                        0x0080
#define RX0_ANARXACONTROL2_IMIN_DFESUM_ALIGN                       0
#define RX0_ANARXACONTROL2_IMIN_DFESUM_BITS                        1
#define RX0_ANARXACONTROL2_IMIN_DFESUM_SHIFT                       7

/* Rx0 :: anaRxAControl2 :: imax_vga [06:06] */
#define RX0_ANARXACONTROL2_IMAX_VGA_MASK                           0x0040
#define RX0_ANARXACONTROL2_IMAX_VGA_ALIGN                          0
#define RX0_ANARXACONTROL2_IMAX_VGA_BITS                           1
#define RX0_ANARXACONTROL2_IMAX_VGA_SHIFT                          6

/* Rx0 :: anaRxAControl2 :: imode_vga [05:05] */
#define RX0_ANARXACONTROL2_IMODE_VGA_MASK                          0x0020
#define RX0_ANARXACONTROL2_IMODE_VGA_ALIGN                         0
#define RX0_ANARXACONTROL2_IMODE_VGA_BITS                          1
#define RX0_ANARXACONTROL2_IMODE_VGA_SHIFT                         5

/* Rx0 :: anaRxAControl2 :: imin_vga [04:04] */
#define RX0_ANARXACONTROL2_IMIN_VGA_MASK                           0x0010
#define RX0_ANARXACONTROL2_IMIN_VGA_ALIGN                          0
#define RX0_ANARXACONTROL2_IMIN_VGA_BITS                           1
#define RX0_ANARXACONTROL2_IMIN_VGA_SHIFT                          4

/* Rx0 :: anaRxAControl2 :: imax_interp [03:03] */
#define RX0_ANARXACONTROL2_IMAX_INTERP_MASK                        0x0008
#define RX0_ANARXACONTROL2_IMAX_INTERP_ALIGN                       0
#define RX0_ANARXACONTROL2_IMAX_INTERP_BITS                        1
#define RX0_ANARXACONTROL2_IMAX_INTERP_SHIFT                       3

/* Rx0 :: anaRxAControl2 :: imode_interp [02:02] */
#define RX0_ANARXACONTROL2_IMODE_INTERP_MASK                       0x0004
#define RX0_ANARXACONTROL2_IMODE_INTERP_ALIGN                      0
#define RX0_ANARXACONTROL2_IMODE_INTERP_BITS                       1
#define RX0_ANARXACONTROL2_IMODE_INTERP_SHIFT                      2

/* Rx0 :: anaRxAControl2 :: imin_interp [01:01] */
#define RX0_ANARXACONTROL2_IMIN_INTERP_MASK                        0x0002
#define RX0_ANARXACONTROL2_IMIN_INTERP_ALIGN                       0
#define RX0_ANARXACONTROL2_IMIN_INTERP_BITS                        1
#define RX0_ANARXACONTROL2_IMIN_INTERP_SHIFT                       1

/* Rx0 :: anaRxAControl2 :: imax_vcm [00:00] */
#define RX0_ANARXACONTROL2_IMAX_VCM_MASK                           0x0001
#define RX0_ANARXACONTROL2_IMAX_VCM_ALIGN                          0
#define RX0_ANARXACONTROL2_IMAX_VCM_BITS                           1
#define RX0_ANARXACONTROL2_IMAX_VCM_SHIFT                          0


/****************************************************************************
 * Rx0 :: anaRxAControl3
 ***************************************************************************/
/* Rx0 :: anaRxAControl3 :: en_clk16 [15:15] */
#define RX0_ANARXACONTROL3_EN_CLK16_MASK                           0x8000
#define RX0_ANARXACONTROL3_EN_CLK16_ALIGN                          0
#define RX0_ANARXACONTROL3_EN_CLK16_BITS                           1
#define RX0_ANARXACONTROL3_EN_CLK16_SHIFT                          15

/* Rx0 :: anaRxAControl3 :: pd_ch_p1 [14:14] */
#define RX0_ANARXACONTROL3_PD_CH_P1_MASK                           0x4000
#define RX0_ANARXACONTROL3_PD_CH_P1_ALIGN                          0
#define RX0_ANARXACONTROL3_PD_CH_P1_BITS                           1
#define RX0_ANARXACONTROL3_PD_CH_P1_SHIFT                          14

/* Rx0 :: anaRxAControl3 :: en_vcctrl [13:13] */
#define RX0_ANARXACONTROL3_EN_VCCTRL_MASK                          0x2000
#define RX0_ANARXACONTROL3_EN_VCCTRL_ALIGN                         0
#define RX0_ANARXACONTROL3_EN_VCCTRL_BITS                          1
#define RX0_ANARXACONTROL3_EN_VCCTRL_SHIFT                         13

/* Rx0 :: anaRxAControl3 :: en_dfeclk [12:12] */
#define RX0_ANARXACONTROL3_EN_DFECLK_MASK                          0x1000
#define RX0_ANARXACONTROL3_EN_DFECLK_ALIGN                         0
#define RX0_ANARXACONTROL3_EN_DFECLK_BITS                          1
#define RX0_ANARXACONTROL3_EN_DFECLK_SHIFT                         12

/* Rx0 :: anaRxAControl3 :: en_hgain [11:11] */
#define RX0_ANARXACONTROL3_EN_HGAIN_MASK                           0x0800
#define RX0_ANARXACONTROL3_EN_HGAIN_ALIGN                          0
#define RX0_ANARXACONTROL3_EN_HGAIN_BITS                           1
#define RX0_ANARXACONTROL3_EN_HGAIN_SHIFT                          11

/* Rx0 :: anaRxAControl3 :: en_dfeckpwr [10:10] */
#define RX0_ANARXACONTROL3_EN_DFECKPWR_MASK                        0x0400
#define RX0_ANARXACONTROL3_EN_DFECKPWR_ALIGN                       0
#define RX0_ANARXACONTROL3_EN_DFECKPWR_BITS                        1
#define RX0_ANARXACONTROL3_EN_DFECKPWR_SHIFT                       10

/* Rx0 :: anaRxAControl3 :: offset_pd [09:09] */
#define RX0_ANARXACONTROL3_OFFSET_PD_MASK                          0x0200
#define RX0_ANARXACONTROL3_OFFSET_PD_ALIGN                         0
#define RX0_ANARXACONTROL3_OFFSET_PD_BITS                          1
#define RX0_ANARXACONTROL3_OFFSET_PD_SHIFT                         9

/* Rx0 :: anaRxAControl3 :: imax_dfetap [08:08] */
#define RX0_ANARXACONTROL3_IMAX_DFETAP_MASK                        0x0100
#define RX0_ANARXACONTROL3_IMAX_DFETAP_ALIGN                       0
#define RX0_ANARXACONTROL3_IMAX_DFETAP_BITS                        1
#define RX0_ANARXACONTROL3_IMAX_DFETAP_SHIFT                       8

/* Rx0 :: anaRxAControl3 :: imode_dfetap [07:07] */
#define RX0_ANARXACONTROL3_IMODE_DFETAP_MASK                       0x0080
#define RX0_ANARXACONTROL3_IMODE_DFETAP_ALIGN                      0
#define RX0_ANARXACONTROL3_IMODE_DFETAP_BITS                       1
#define RX0_ANARXACONTROL3_IMODE_DFETAP_SHIFT                      7

/* Rx0 :: anaRxAControl3 :: imin_dfetap [06:06] */
#define RX0_ANARXACONTROL3_IMIN_DFETAP_MASK                        0x0040
#define RX0_ANARXACONTROL3_IMIN_DFETAP_ALIGN                       0
#define RX0_ANARXACONTROL3_IMIN_DFETAP_BITS                        1
#define RX0_ANARXACONTROL3_IMIN_DFETAP_SHIFT                       6

/* Rx0 :: anaRxAControl3 :: imax_slcd2c [05:05] */
#define RX0_ANARXACONTROL3_IMAX_SLCD2C_MASK                        0x0020
#define RX0_ANARXACONTROL3_IMAX_SLCD2C_ALIGN                       0
#define RX0_ANARXACONTROL3_IMAX_SLCD2C_BITS                        1
#define RX0_ANARXACONTROL3_IMAX_SLCD2C_SHIFT                       5

/* Rx0 :: anaRxAControl3 :: imode_slcd2c [04:04] */
#define RX0_ANARXACONTROL3_IMODE_SLCD2C_MASK                       0x0010
#define RX0_ANARXACONTROL3_IMODE_SLCD2C_ALIGN                      0
#define RX0_ANARXACONTROL3_IMODE_SLCD2C_BITS                       1
#define RX0_ANARXACONTROL3_IMODE_SLCD2C_SHIFT                      4

/* Rx0 :: anaRxAControl3 :: imin_slcd2c [03:03] */
#define RX0_ANARXACONTROL3_IMIN_SLCD2C_MASK                        0x0008
#define RX0_ANARXACONTROL3_IMIN_SLCD2C_ALIGN                       0
#define RX0_ANARXACONTROL3_IMIN_SLCD2C_BITS                        1
#define RX0_ANARXACONTROL3_IMIN_SLCD2C_SHIFT                       3

/* Rx0 :: anaRxAControl3 :: imax_dfevref [02:02] */
#define RX0_ANARXACONTROL3_IMAX_DFEVREF_MASK                       0x0004
#define RX0_ANARXACONTROL3_IMAX_DFEVREF_ALIGN                      0
#define RX0_ANARXACONTROL3_IMAX_DFEVREF_BITS                       1
#define RX0_ANARXACONTROL3_IMAX_DFEVREF_SHIFT                      2

/* Rx0 :: anaRxAControl3 :: imode_dfevref [01:01] */
#define RX0_ANARXACONTROL3_IMODE_DFEVREF_MASK                      0x0002
#define RX0_ANARXACONTROL3_IMODE_DFEVREF_ALIGN                     0
#define RX0_ANARXACONTROL3_IMODE_DFEVREF_BITS                      1
#define RX0_ANARXACONTROL3_IMODE_DFEVREF_SHIFT                     1

/* Rx0 :: anaRxAControl3 :: imin_dfevref [00:00] */
#define RX0_ANARXACONTROL3_IMIN_DFEVREF_MASK                       0x0001
#define RX0_ANARXACONTROL3_IMIN_DFEVREF_ALIGN                      0
#define RX0_ANARXACONTROL3_IMIN_DFEVREF_BITS                       1
#define RX0_ANARXACONTROL3_IMIN_DFEVREF_SHIFT                      0


/****************************************************************************
 * Hypercore_USER_Rx1
 ***************************************************************************/
/****************************************************************************
 * Rx1 :: anaRxStatus
 ***************************************************************************/
/* union - case sigdet_Status [15:00] */
/* Rx1 :: anaRxStatus :: cx4_sigdet [15:15] */
#define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK              0x8000
#define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN             0
#define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS              1
#define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT             15

/* Rx1 :: anaRxStatus :: reserved0 [14:13] */
#define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK               0x6000
#define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN              0
#define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS               2
#define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT              13

/* Rx1 :: anaRxStatus :: rxSeqDone [12:12] */
#define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK               0x1000
#define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN              0
#define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS               1
#define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT              12

/* Rx1 :: anaRxStatus :: rx_sigdet_ll [11:11] */
#define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK            0x0800
#define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN           0
#define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS            1
#define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT           11

/* Rx1 :: anaRxStatus :: cs4_sigdet_ll [10:10] */
#define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK           0x0400
#define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN          0
#define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS           1
#define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT          10

/* Rx1 :: anaRxStatus :: rx_reset [09:09] */
#define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK                0x0200
#define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN               0
#define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS                1
#define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT               9

/* Rx1 :: anaRxStatus :: rx_pwrdn [08:08] */
#define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK                0x0100
#define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN               0
#define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS                1
#define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT               8

/* Rx1 :: anaRxStatus :: reserved1 [07:00] */
#define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK               0x00ff
#define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN              0
#define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS               8
#define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT              0


/* union - case sync_Status [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:11] */
#define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK                 0xf800
#define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN                0
#define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS                 5
#define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT                11

/* Rx1 :: anaRxStatus :: test_acq_en [10:10] */
#define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK               0x0400
#define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN              0
#define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS               1
#define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT              10

/* Rx1 :: anaRxStatus :: reserved1 [09:09] */
#define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK                 0x0200
#define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN                0
#define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS                 1
#define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT                9

/* Rx1 :: anaRxStatus :: rxSeqStart [08:08] */
#define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK                0x0100
#define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN               0
#define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS                1
#define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT               8

/* Rx1 :: anaRxStatus :: mux_comadj_sync_status [07:07] */
#define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK    0x0080
#define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN   0
#define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS    1
#define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT   7

/* Rx1 :: anaRxStatus :: sync_status [06:06] */
#define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK               0x0040
#define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN              0
#define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS               1
#define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT              6

/* Rx1 :: anaRxStatus :: rx_sigdet [05:05] */
#define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK                 0x0020
#define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN                0
#define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS                 1
#define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT                5

/* Rx1 :: anaRxStatus :: reserved2 [04:03] */
#define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK                 0x0018
#define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN                0
#define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS                 2
#define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT                3

/* Rx1 :: anaRxStatus :: saturate_status [02:02] */
#define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK           0x0004
#define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN          0
#define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS           1
#define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT          2

/* Rx1 :: anaRxStatus :: cx4_sigdet [01:01] */
#define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK                0x0002
#define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN               0
#define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS                1
#define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT               1

/* Rx1 :: anaRxStatus :: rxSeqDone [00:00] */
#define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK                 0x0001
#define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN                0
#define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS                 1
#define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT                0


/* union - case rxTestSel_0 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:10] */
#define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK                 0xfc00
#define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN                0
#define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS                 6
#define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT                10

/* Rx1 :: anaRxStatus :: indck_mode_en [09:09] */
#define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK             0x0200
#define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN            0
#define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS             1
#define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT            9

/* Rx1 :: anaRxStatus :: pci_mode_en [08:08] */
#define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK               0x0100
#define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN              0
#define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS               1
#define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT              8

/* Rx1 :: anaRxStatus :: rx_polarity [07:07] */
#define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK               0x0080
#define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN              0
#define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS               1
#define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT              7

/* Rx1 :: anaRxStatus :: rxpol_flip [06:06] */
#define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK                0x0040
#define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN               0
#define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS                1
#define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT               6

/* Rx1 :: anaRxStatus :: comma_mask [05:05] */
#define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK                0x0020
#define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN               0
#define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS                1
#define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT               5

/* Rx1 :: anaRxStatus :: link_en_r [04:04] */
#define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK                 0x0010
#define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN                0
#define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS                 1
#define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT                4

/* Rx1 :: anaRxStatus :: comma_adj_en [03:03] */
#define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK              0x0008
#define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN             0
#define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS              1
#define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT             3

/* Rx1 :: anaRxStatus :: comma_adj_en_ext [02:02] */
#define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK          0x0004
#define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN         0
#define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS          1
#define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT         2

/* Rx1 :: anaRxStatus :: reserved1 [01:00] */
#define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK                 0x0003
#define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN                0
#define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS                 2
#define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT                0


/* union - case rxTestSel_1 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:05] */
#define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK                 0xffe0
#define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN                0
#define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS                 11
#define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT                5

/* Rx1 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */
#define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK             0x0010
#define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN            0
#define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS             1
#define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT            4

/* Rx1 :: anaRxStatus :: freq_sel_PC [03:03] */
#define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK               0x0008
#define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN              0
#define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS               1
#define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT              3

/* Rx1 :: anaRxStatus :: freq_sel_SM [02:02] */
#define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK               0x0004
#define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN              0
#define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS               1
#define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT              2

/* Rx1 :: anaRxStatus :: integ_mode_SM [01:00] */
#define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK             0x0003
#define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN            0
#define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS             2
#define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT            0


/* union - case scale_Status [15:00] */
/* Rx1 :: anaRxStatus :: prop_scale [15:12] */
#define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK               0xf000
#define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN              0
#define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS               4
#define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT              12

/* Rx1 :: anaRxStatus :: integ_scale [11:08] */
#define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK              0x0f00
#define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN             0
#define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS              4
#define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT             8

/* Rx1 :: anaRxStatus :: prop_scale_acq [07:04] */
#define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK           0x00f0
#define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN          0
#define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS           4
#define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT          4

/* Rx1 :: anaRxStatus :: integ_scale_acq [03:00] */
#define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK          0x000f
#define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN         0
#define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS          4
#define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT         0


/* union - case adc_CdrStatus1 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:07] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK              0xff80
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN             0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS              9
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT             7

/* Rx1 :: anaRxStatus :: rxMuxCkSel [06:06] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK             0x0040
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN            0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS             1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT            6

/* Rx1 :: anaRxStatus :: glpbk_combo [05:05] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK            0x0020
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN           0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS            1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT           5

/* Rx1 :: anaRxStatus :: clockSwitchSel [04:04] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK         0x0010
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN        0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS         1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT        4

/* Rx1 :: anaRxStatus :: rxck_tst [03:03] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK               0x0008
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN              0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS               1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT              3

/* Rx1 :: anaRxStatus :: rxck_i [02:02] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK                 0x0004
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN                0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS                 1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT                2

/* Rx1 :: anaRxStatus :: refclk [01:01] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK                 0x0002
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN                0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS                 1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT                1

/* Rx1 :: anaRxStatus :: pll_bypass [00:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK             0x0001
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN            0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS             1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT            0


/* union - case adc_CdrStatus2 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:06] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK              0xffc0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN             0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS              10
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT             6

/* Rx1 :: anaRxStatus :: rxMuxCkSel [05:05] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK             0x0020
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN            0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS             1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT            5

/* Rx1 :: anaRxStatus :: rxSeqStart [04:04] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK             0x0010
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN            0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS             1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT            4

/* Rx1 :: anaRxStatus :: reserved1 [03:01] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK              0x000e
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN             0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS              3
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT             1

/* Rx1 :: anaRxStatus :: rxSeqDone [00:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK              0x0001
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN             0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS              1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT             0


/* union - case adc_CdrStatus3 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:04] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK              0xfff0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN             0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS              12
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT             4

/* Rx1 :: anaRxStatus :: rxSeqStart [03:03] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK             0x0008
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN            0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS             1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT            3

/* Rx1 :: anaRxStatus :: reserved1 [02:01] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK              0x0006
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN             0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS              2
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT             1

/* Rx1 :: anaRxStatus :: allow_increment_PC [00:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK     0x0001
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN    0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS     1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT    0


/* union - case adc_CdrStatus4 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:08] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK              0xff00
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN             0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS              8
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT             8

/* Rx1 :: anaRxStatus :: rx_pwrdn [07:07] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK               0x0080
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN              0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS               1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT              7

/* Rx1 :: anaRxStatus :: freq_sel [06:06] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK               0x0040
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN              0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS               1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT              6

/* Rx1 :: anaRxStatus :: pll_lock_rstb [05:05] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK          0x0020
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN         0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS          1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT         5

/* Rx1 :: anaRxStatus :: pwrdn [04:04] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK                  0x0010
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                 0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS                  1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                 4

/* Rx1 :: anaRxStatus :: reserved1 [03:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK              0x000f
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN             0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS              4
#define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT             0


/* union - case adc_CdrStatus5 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK              0xffff
#define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN             0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS              16
#define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT             0


/* union - case adc_CdrStatus6 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:05] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK              0xffe0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN             0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS              11
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT             5

/* Rx1 :: anaRxStatus :: rx_reset [04:04] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK               0x0010
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN              0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS               1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT              4

/* Rx1 :: anaRxStatus :: rx_pwrdn [03:03] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK               0x0008
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN              0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS               1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT              3

/* Rx1 :: anaRxStatus :: reset_anlg [02:02] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK             0x0004
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN            0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS             1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT            2

/* Rx1 :: anaRxStatus :: pwrdn_rx [01:01] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK               0x0002
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN              0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS               1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT              1

/* Rx1 :: anaRxStatus :: pwrdn_pll [00:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK              0x0001
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN             0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS              1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT             0


/* union - case adc_CdrStatus7e [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:05] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK             0xffe0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN            0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS             11
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT            5

/* Rx1 :: anaRxStatus :: rxck0_even [04:04] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK            0x0010
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN           0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS            1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT           4

/* Rx1 :: anaRxStatus :: rxck1_even [03:03] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK            0x0008
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN           0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS            1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT           3

/* Rx1 :: anaRxStatus :: comdet_even [02:02] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK           0x0004
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN          0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS           1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT          2

/* Rx1 :: anaRxStatus :: en_cdet_even [01:01] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK          0x0002
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN         0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS          1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT         1

/* Rx1 :: anaRxStatus :: comma_adj_en_even [00:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK     0x0001
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN    0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS     1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT    0


/* union - case adc_CdrStatus7o [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:05] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK             0xffe0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN            0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS             11
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT            5

/* Rx1 :: anaRxStatus :: rxck0_odd [04:04] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK             0x0010
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN            0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS             1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT            4

/* Rx1 :: anaRxStatus :: rxck1_odd [03:03] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK             0x0008
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN            0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS             1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT            3

/* Rx1 :: anaRxStatus :: comdet_odd [02:02] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK            0x0004
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN           0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS            1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT           2

/* Rx1 :: anaRxStatus :: en_cdet_odd [01:01] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK           0x0002
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN          0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS           1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT          1

/* Rx1 :: anaRxStatus :: comma_adj_en_odd [00:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK      0x0001
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN     0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS      1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT     0


/* union - case adc_CdrStatus8 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:01] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK              0xfffe
#define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN             0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS              15
#define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT             1

/* Rx1 :: anaRxStatus :: sigdet [00:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK                 0x0001
#define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN                0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS                 1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT                0


/* union - case adc_CdrStatus9 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK              0xffff
#define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN             0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS              16
#define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT             0


/* union - case adc_CdrStatus10 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:07] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK             0xff80
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN            0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS             9
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT            7

/* Rx1 :: anaRxStatus :: prbs_en [06:06] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK               0x0040
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN              0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS               1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT              6

/* Rx1 :: anaRxStatus :: rstb_tst [05:05] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK              0x0020
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN             0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS              1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT             5

/* Rx1 :: anaRxStatus :: reserved1 [04:04] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK             0x0010
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN            0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS             1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT            4

/* Rx1 :: anaRxStatus :: prbs_state [03:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK            0x000f
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN           0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS            4
#define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT           0


/* union - case adc_CdrStatus11 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK             0xffff
#define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN            0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS             16
#define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT            0


/* union - case adc_CdrStatus12_1 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:06] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK           0xffc0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN          0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS           10
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT          6

/* Rx1 :: anaRxStatus :: enable4 [05:05] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK             0x0020
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN            0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS             1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT            5

/* Rx1 :: anaRxStatus :: radr_test [04:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK           0x001f
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN          0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS           5
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT          0


/* union - case adc_CdrStatus12_2 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:05] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK           0xffe0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN          0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS           11
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT          5

/* Rx1 :: anaRxStatus :: wadr_test [04:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK           0x001f
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN          0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS           5
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT          0


/* union - case adc_CdrStatus12_3 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:06] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK           0xffc0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN          0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS           10
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT          6

/* Rx1 :: anaRxStatus :: rxck_66B_tmux [05:05] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK       0x0020
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN      0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS       1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT      5

/* Rx1 :: anaRxStatus :: rstb_66B [04:04] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK            0x0010
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN           0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS            1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT           4

/* Rx1 :: anaRxStatus :: prstb_66B_mux [03:03] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK       0x0008
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN      0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS       1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT      3

/* Rx1 :: anaRxStatus :: rxck_i66_tmux [02:02] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK       0x0004
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN      0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS       1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT      2

/* Rx1 :: anaRxStatus :: rstb_i66 [01:01] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK            0x0002
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN           0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS            1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT           1

/* Rx1 :: anaRxStatus :: prstb_i66_mux [00:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK       0x0001
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN      0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS       1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT      0


/* union - case adc_CdrStatus12_4 [15:00] */
/* Rx1 :: anaRxStatus :: reserved0 [15:04] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK           0xfff0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN          0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS           12
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT          4

/* Rx1 :: anaRxStatus :: rfifo_error_r [03:02] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK       0x000c
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN      0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS       2
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT      2

/* Rx1 :: anaRxStatus :: rfifo_unflow [01:01] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK        0x0002
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN       0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS        1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT       1

/* Rx1 :: anaRxStatus :: rfifo_ovflow [00:00] */
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK        0x0001
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN       0
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS        1
#define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT       0


/* union - case integ_Status [15:00] */
/* Rx1 :: anaRxStatus :: integ_status [15:00] */
#define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK             0xffff
#define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN            0
#define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS             16
#define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT            0


/* union - case vco_Status [15:00] */
/* Rx1 :: anaRxStatus :: vco_status [15:00] */
#define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK                 0xffff
#define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN                0
#define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS                 16
#define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT                0


/* union - case prbs_Status [15:00] */
/* Rx1 :: anaRxStatus :: prbs_lock [15:15] */
#define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK                 0x8000
#define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN                0
#define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS                 1
#define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT                15

/* Rx1 :: anaRxStatus :: prbs_stky [14:14] */
#define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK                 0x4000
#define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN                0
#define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS                 1
#define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT                14

/* Rx1 :: anaRxStatus :: ptbs_errors [13:00] */
#define RX1_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK               0x3fff
#define RX1_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN              0
#define RX1_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS               14
#define RX1_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT              0



/****************************************************************************
 * Rx1 :: anaRxControl
 ***************************************************************************/
/* Rx1 :: anaRxControl :: reserved0 [15:10] */
#define RX1_ANARXCONTROL_RESERVED0_MASK                            0xfc00
#define RX1_ANARXCONTROL_RESERVED0_ALIGN                           0
#define RX1_ANARXCONTROL_RESERVED0_BITS                            6
#define RX1_ANARXCONTROL_RESERVED0_SHIFT                           10

/* Rx1 :: anaRxControl :: override_sigdet_en [09:09] */
#define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK                   0x0200
#define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN                  0
#define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS                   1
#define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT                  9

/* Rx1 :: anaRxControl :: override_sigdet_val [08:08] */
#define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK                  0x0100
#define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN                 0
#define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS                  1
#define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT                 8

/* Rx1 :: anaRxControl :: reserved1 [07:03] */
#define RX1_ANARXCONTROL_RESERVED1_MASK                            0x00f8
#define RX1_ANARXCONTROL_RESERVED1_ALIGN                           0
#define RX1_ANARXCONTROL_RESERVED1_BITS                            5
#define RX1_ANARXCONTROL_RESERVED1_SHIFT                           3

/* Rx1 :: anaRxControl :: status_sel [02:00] */
#define RX1_ANARXCONTROL_STATUS_SEL_MASK                           0x0007
#define RX1_ANARXCONTROL_STATUS_SEL_ALIGN                          0
#define RX1_ANARXCONTROL_STATUS_SEL_BITS                           3
#define RX1_ANARXCONTROL_STATUS_SEL_SHIFT                          0
#define RX1_ANARXCONTROL_STATUS_SEL_sigdetStatus                   0
#define RX1_ANARXCONTROL_STATUS_SEL_syncStatus                     1
#define RX1_ANARXCONTROL_STATUS_SEL_rxTestSel                      2
#define RX1_ANARXCONTROL_STATUS_SEL_scaleStatus                    3
#define RX1_ANARXCONTROL_STATUS_SEL_adcCdrStatus                   4
#define RX1_ANARXCONTROL_STATUS_SEL_integStatus                    5
#define RX1_ANARXCONTROL_STATUS_SEL_vcoStatus                      6
#define RX1_ANARXCONTROL_STATUS_SEL_prbsStatus                     7


/****************************************************************************
 * Rx1 :: anaRxTest
 ***************************************************************************/
/* Rx1 :: anaRxTest :: sigdet_mux_SM [15:12] */
#define RX1_ANARXTEST_SIGDET_MUX_SM_MASK                           0xf000
#define RX1_ANARXTEST_SIGDET_MUX_SM_ALIGN                          0
#define RX1_ANARXTEST_SIGDET_MUX_SM_BITS                           4
#define RX1_ANARXTEST_SIGDET_MUX_SM_SHIFT                          12

/* Rx1 :: anaRxTest :: reserved0 [11:09] */
#define RX1_ANARXTEST_RESERVED0_MASK                               0x0e00
#define RX1_ANARXTEST_RESERVED0_ALIGN                              0
#define RX1_ANARXTEST_RESERVED0_BITS                               3
#define RX1_ANARXTEST_RESERVED0_SHIFT                              9

/* Rx1 :: anaRxTest :: tpctrl_SM [08:04] */
#define RX1_ANARXTEST_TPCTRL_SM_MASK                               0x01f0
#define RX1_ANARXTEST_TPCTRL_SM_ALIGN                              0
#define RX1_ANARXTEST_TPCTRL_SM_BITS                               5
#define RX1_ANARXTEST_TPCTRL_SM_SHIFT                              4

/* Rx1 :: anaRxTest :: testMuxSelect_SM [03:00] */
#define RX1_ANARXTEST_TESTMUXSELECT_SM_MASK                        0x000f
#define RX1_ANARXTEST_TESTMUXSELECT_SM_ALIGN                       0
#define RX1_ANARXTEST_TESTMUXSELECT_SM_BITS                        4
#define RX1_ANARXTEST_TESTMUXSELECT_SM_SHIFT                       0


/****************************************************************************
 * Rx1 :: anaRxControl1G
 ***************************************************************************/
/* Rx1 :: anaRxControl1G :: fpat_md [15:15] */
#define RX1_ANARXCONTROL1G_FPAT_MD_MASK                            0x8000
#define RX1_ANARXCONTROL1G_FPAT_MD_ALIGN                           0
#define RX1_ANARXCONTROL1G_FPAT_MD_BITS                            1
#define RX1_ANARXCONTROL1G_FPAT_MD_SHIFT                           15

/* Rx1 :: anaRxControl1G :: pkt_count_en [14:14] */
#define RX1_ANARXCONTROL1G_PKT_COUNT_EN_MASK                       0x4000
#define RX1_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN                      0
#define RX1_ANARXCONTROL1G_PKT_COUNT_EN_BITS                       1
#define RX1_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT                      14

/* Rx1 :: anaRxControl1G :: staMuxRegDis [13:13] */
#define RX1_ANARXCONTROL1G_STAMUXREGDIS_MASK                       0x2000
#define RX1_ANARXCONTROL1G_STAMUXREGDIS_ALIGN                      0
#define RX1_ANARXCONTROL1G_STAMUXREGDIS_BITS                       1
#define RX1_ANARXCONTROL1G_STAMUXREGDIS_SHIFT                      13

/* Rx1 :: anaRxControl1G :: prbs_clr_dis [12:12] */
#define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_MASK                       0x1000
#define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN                      0
#define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_BITS                       1
#define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT                      12

/* Rx1 :: anaRxControl1G :: rxd_dec_sel [11:11] */
#define RX1_ANARXCONTROL1G_RXD_DEC_SEL_MASK                        0x0800
#define RX1_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN                       0
#define RX1_ANARXCONTROL1G_RXD_DEC_SEL_BITS                        1
#define RX1_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT                       11

/* Rx1 :: anaRxControl1G :: cgbad_tst [10:10] */
#define RX1_ANARXCONTROL1G_CGBAD_TST_MASK                          0x0400
#define RX1_ANARXCONTROL1G_CGBAD_TST_ALIGN                         0
#define RX1_ANARXCONTROL1G_CGBAD_TST_BITS                          1
#define RX1_ANARXCONTROL1G_CGBAD_TST_SHIFT                         10

/* Rx1 :: anaRxControl1G :: Emon_en [09:09] */
#define RX1_ANARXCONTROL1G_EMON_EN_MASK                            0x0200
#define RX1_ANARXCONTROL1G_EMON_EN_ALIGN                           0
#define RX1_ANARXCONTROL1G_EMON_EN_BITS                            1
#define RX1_ANARXCONTROL1G_EMON_EN_SHIFT                           9

/* Rx1 :: anaRxControl1G :: prbs_en [08:08] */
#define RX1_ANARXCONTROL1G_PRBS_EN_MASK                            0x0100
#define RX1_ANARXCONTROL1G_PRBS_EN_ALIGN                           0
#define RX1_ANARXCONTROL1G_PRBS_EN_BITS                            1
#define RX1_ANARXCONTROL1G_PRBS_EN_SHIFT                           8

/* Rx1 :: anaRxControl1G :: cgbad_en [07:07] */
#define RX1_ANARXCONTROL1G_CGBAD_EN_MASK                           0x0080
#define RX1_ANARXCONTROL1G_CGBAD_EN_ALIGN                          0
#define RX1_ANARXCONTROL1G_CGBAD_EN_BITS                           1
#define RX1_ANARXCONTROL1G_CGBAD_EN_SHIFT                          7

/* Rx1 :: anaRxControl1G :: cstretch [06:06] */
#define RX1_ANARXCONTROL1G_CSTRETCH_MASK                           0x0040
#define RX1_ANARXCONTROL1G_CSTRETCH_ALIGN                          0
#define RX1_ANARXCONTROL1G_CSTRETCH_BITS                           1
#define RX1_ANARXCONTROL1G_CSTRETCH_SHIFT                          6

/* Rx1 :: anaRxControl1G :: comma_low_byte_SM [05:05] */
#define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK                  0x0020
#define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN                 0
#define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS                  1
#define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT                 5

/* Rx1 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */
#define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK               0x0010
#define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN              0
#define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS               1
#define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT              4

/* Rx1 :: anaRxControl1G :: reserved0 [03:02] */
#define RX1_ANARXCONTROL1G_RESERVED0_MASK                          0x000c
#define RX1_ANARXCONTROL1G_RESERVED0_ALIGN                         0
#define RX1_ANARXCONTROL1G_RESERVED0_BITS                          2
#define RX1_ANARXCONTROL1G_RESERVED0_SHIFT                         2

/* Rx1 :: anaRxControl1G :: freq_sel_force [01:01] */
#define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK                     0x0002
#define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN                    0
#define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS                     1
#define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT                    1

/* Rx1 :: anaRxControl1G :: freq_sel [00:00] */
#define RX1_ANARXCONTROL1G_FREQ_SEL_MASK                           0x0001
#define RX1_ANARXCONTROL1G_FREQ_SEL_ALIGN                          0
#define RX1_ANARXCONTROL1G_FREQ_SEL_BITS                           1
#define RX1_ANARXCONTROL1G_FREQ_SEL_SHIFT                          0


/****************************************************************************
 * Rx1 :: anaRxControlPci
 ***************************************************************************/
/* Rx1 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK                0x8000
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN               0
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS                1
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT               15

/* Rx1 :: anaRxControlPci :: comma_mask_force_r [14:14] */
#define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK                0x4000
#define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN               0
#define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS                1
#define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT               14

/* Rx1 :: anaRxControlPci :: comma_mask_r [13:13] */
#define RX1_ANARXCONTROLPCI_COMMA_MASK_R_MASK                      0x2000
#define RX1_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN                     0
#define RX1_ANARXCONTROLPCI_COMMA_MASK_R_BITS                      1
#define RX1_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT                     13

/* Rx1 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */
#define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK         0x1000
#define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN        0
#define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS         1
#define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT        12

/* Rx1 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */
#define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK            0x0800
#define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN           0
#define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS            1
#define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT           11

/* Rx1 :: anaRxControlPci :: sync_status_force_r [10:10] */
#define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK               0x0400
#define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN              0
#define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS               1
#define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT              10

/* Rx1 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK         0x0200
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN        0
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS         1
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT        9

/* Rx1 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK        0x0100
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN       0
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS        1
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT       8

/* Rx1 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK           0x0080
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN          0
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS           1
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT          7

/* Rx1 :: anaRxControlPci :: comma_adj_en_r [06:06] */
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK                    0x0040
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN                   0
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS                    1
#define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT                   6

/* Rx1 :: anaRxControlPci :: link_en_force_SM [05:05] */
#define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK                  0x0020
#define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN                 0
#define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS                  1
#define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT                 5

/* Rx1 :: anaRxControlPci :: link_en_r [04:04] */
#define RX1_ANARXCONTROLPCI_LINK_EN_R_MASK                         0x0010
#define RX1_ANARXCONTROLPCI_LINK_EN_R_ALIGN                        0
#define RX1_ANARXCONTROLPCI_LINK_EN_R_BITS                         1
#define RX1_ANARXCONTROLPCI_LINK_EN_R_SHIFT                        4

/* Rx1 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */
#define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK              0x0008
#define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN             0
#define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS              1
#define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT             3

/* Rx1 :: anaRxControlPci :: rx_polarity_r [02:02] */
#define RX1_ANARXCONTROLPCI_RX_POLARITY_R_MASK                     0x0004
#define RX1_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN                    0
#define RX1_ANARXCONTROLPCI_RX_POLARITY_R_BITS                     1
#define RX1_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT                    2

/* Rx1 :: anaRxControlPci :: integ_mode_SM [01:00] */
#define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_MASK                     0x0003
#define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN                    0
#define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_BITS                     2
#define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT                    0


/****************************************************************************
 * Rx1 :: anaRxAstatus
 ***************************************************************************/
/* Rx1 :: anaRxAstatus :: sigdet [15:15] */
#define RX1_ANARXASTATUS_SIGDET_MASK                               0x8000
#define RX1_ANARXASTATUS_SIGDET_ALIGN                              0
#define RX1_ANARXASTATUS_SIGDET_BITS                               1
#define RX1_ANARXASTATUS_SIGDET_SHIFT                              15

/* Rx1 :: anaRxAstatus :: rx_pf [14:12] */
#define RX1_ANARXASTATUS_RX_PF_MASK                                0x7000
#define RX1_ANARXASTATUS_RX_PF_ALIGN                               0
#define RX1_ANARXASTATUS_RX_PF_BITS                                3
#define RX1_ANARXASTATUS_RX_PF_SHIFT                               12

/* Rx1 :: anaRxAstatus :: dfe [11:06] */
#define RX1_ANARXASTATUS_DFE_MASK                                  0x0fc0
#define RX1_ANARXASTATUS_DFE_ALIGN                                 0
#define RX1_ANARXASTATUS_DFE_BITS                                  6
#define RX1_ANARXASTATUS_DFE_SHIFT                                 6

/* Rx1 :: anaRxAstatus :: reserved0 [05:05] */
#define RX1_ANARXASTATUS_RESERVED0_MASK                            0x0020
#define RX1_ANARXASTATUS_RESERVED0_ALIGN                           0
#define RX1_ANARXASTATUS_RESERVED0_BITS                            1
#define RX1_ANARXASTATUS_RESERVED0_SHIFT                           5

/* Rx1 :: anaRxAstatus :: vga [04:00] */
#define RX1_ANARXASTATUS_VGA_MASK                                  0x001f
#define RX1_ANARXASTATUS_VGA_ALIGN                                 0
#define RX1_ANARXASTATUS_VGA_BITS                                  5
#define RX1_ANARXASTATUS_VGA_SHIFT                                 0


/****************************************************************************
 * Rx1 :: anaRxAControl1
 ***************************************************************************/
/* Rx1 :: anaRxAControl1 :: imode_vcm [15:15] */
#define RX1_ANARXACONTROL1_IMODE_VCM_MASK                          0x8000
#define RX1_ANARXACONTROL1_IMODE_VCM_ALIGN                         0
#define RX1_ANARXACONTROL1_IMODE_VCM_BITS                          1
#define RX1_ANARXACONTROL1_IMODE_VCM_SHIFT                         15

/* Rx1 :: anaRxAControl1 :: imin_vcm [14:14] */
#define RX1_ANARXACONTROL1_IMIN_VCM_MASK                           0x4000
#define RX1_ANARXACONTROL1_IMIN_VCM_ALIGN                          0
#define RX1_ANARXACONTROL1_IMIN_VCM_BITS                           1
#define RX1_ANARXACONTROL1_IMIN_VCM_SHIFT                          14

/* Rx1 :: anaRxAControl1 :: imax_sigdet [13:13] */
#define RX1_ANARXACONTROL1_IMAX_SIGDET_MASK                        0x2000
#define RX1_ANARXACONTROL1_IMAX_SIGDET_ALIGN                       0
#define RX1_ANARXACONTROL1_IMAX_SIGDET_BITS                        1
#define RX1_ANARXACONTROL1_IMAX_SIGDET_SHIFT                       13

/* Rx1 :: anaRxAControl1 :: imode_sigdet [12:12] */
#define RX1_ANARXACONTROL1_IMODE_SIGDET_MASK                       0x1000
#define RX1_ANARXACONTROL1_IMODE_SIGDET_ALIGN                      0
#define RX1_ANARXACONTROL1_IMODE_SIGDET_BITS                       1
#define RX1_ANARXACONTROL1_IMODE_SIGDET_SHIFT                      12

/* Rx1 :: anaRxAControl1 :: imin_sigdet [11:11] */
#define RX1_ANARXACONTROL1_IMIN_SIGDET_MASK                        0x0800
#define RX1_ANARXACONTROL1_IMIN_SIGDET_ALIGN                       0
#define RX1_ANARXACONTROL1_IMIN_SIGDET_BITS                        1
#define RX1_ANARXACONTROL1_IMIN_SIGDET_SHIFT                       11

/* Rx1 :: anaRxAControl1 :: refh_rx [10:10] */
#define RX1_ANARXACONTROL1_REFH_RX_MASK                            0x0400
#define RX1_ANARXACONTROL1_REFH_RX_ALIGN                           0
#define RX1_ANARXACONTROL1_REFH_RX_BITS                            1
#define RX1_ANARXACONTROL1_REFH_RX_SHIFT                           10

/* Rx1 :: anaRxAControl1 :: refl_rx [09:09] */
#define RX1_ANARXACONTROL1_REFL_RX_MASK                            0x0200
#define RX1_ANARXACONTROL1_REFL_RX_ALIGN                           0
#define RX1_ANARXACONTROL1_REFL_RX_BITS                            1
#define RX1_ANARXACONTROL1_REFL_RX_SHIFT                           9

/* Rx1 :: anaRxAControl1 :: tport_en [08:08] */
#define RX1_ANARXACONTROL1_TPORT_EN_MASK                           0x0100
#define RX1_ANARXACONTROL1_TPORT_EN_ALIGN                          0
#define RX1_ANARXACONTROL1_TPORT_EN_BITS                           1
#define RX1_ANARXACONTROL1_TPORT_EN_SHIFT                          8

/* Rx1 :: anaRxAControl1 :: vddrb_bg [07:07] */
#define RX1_ANARXACONTROL1_VDDRB_BG_MASK                           0x0080
#define RX1_ANARXACONTROL1_VDDRB_BG_ALIGN                          0
#define RX1_ANARXACONTROL1_VDDRB_BG_BITS                           1
#define RX1_ANARXACONTROL1_VDDRB_BG_SHIFT                          7

/* Rx1 :: anaRxAControl1 :: sig_pwrdn [06:06] */
#define RX1_ANARXACONTROL1_SIG_PWRDN_MASK                          0x0040
#define RX1_ANARXACONTROL1_SIG_PWRDN_ALIGN                         0
#define RX1_ANARXACONTROL1_SIG_PWRDN_BITS                          1
#define RX1_ANARXACONTROL1_SIG_PWRDN_SHIFT                         6

/* Rx1 :: anaRxAControl1 :: offset_ctrl [05:03] */
#define RX1_ANARXACONTROL1_OFFSET_CTRL_MASK                        0x0038
#define RX1_ANARXACONTROL1_OFFSET_CTRL_ALIGN                       0
#define RX1_ANARXACONTROL1_OFFSET_CTRL_BITS                        3
#define RX1_ANARXACONTROL1_OFFSET_CTRL_SHIFT                       3

/* Rx1 :: anaRxAControl1 :: offset_sel [02:02] */
#define RX1_ANARXACONTROL1_OFFSET_SEL_MASK                         0x0004
#define RX1_ANARXACONTROL1_OFFSET_SEL_ALIGN                        0
#define RX1_ANARXACONTROL1_OFFSET_SEL_BITS                         1
#define RX1_ANARXACONTROL1_OFFSET_SEL_SHIFT                        2

/* Rx1 :: anaRxAControl1 :: reserved0 [01:00] */
#define RX1_ANARXACONTROL1_RESERVED0_MASK                          0x0003
#define RX1_ANARXACONTROL1_RESERVED0_ALIGN                         0
#define RX1_ANARXACONTROL1_RESERVED0_BITS                          2
#define RX1_ANARXACONTROL1_RESERVED0_SHIFT                         0


/****************************************************************************
 * Rx1 :: anaRxAControl2
 ***************************************************************************/
/* Rx1 :: anaRxAControl2 :: imax_clkbuf [15:15] */
#define RX1_ANARXACONTROL2_IMAX_CLKBUF_MASK                        0x8000
#define RX1_ANARXACONTROL2_IMAX_CLKBUF_ALIGN                       0
#define RX1_ANARXACONTROL2_IMAX_CLKBUF_BITS                        1
#define RX1_ANARXACONTROL2_IMAX_CLKBUF_SHIFT                       15

/* Rx1 :: anaRxAControl2 :: imode_clkbuf [14:14] */
#define RX1_ANARXACONTROL2_IMODE_CLKBUF_MASK                       0x4000
#define RX1_ANARXACONTROL2_IMODE_CLKBUF_ALIGN                      0
#define RX1_ANARXACONTROL2_IMODE_CLKBUF_BITS                       1
#define RX1_ANARXACONTROL2_IMODE_CLKBUF_SHIFT                      14

/* Rx1 :: anaRxAControl2 :: imin_clkbuf [13:13] */
#define RX1_ANARXACONTROL2_IMIN_CLKBUF_MASK                        0x2000
#define RX1_ANARXACONTROL2_IMIN_CLKBUF_ALIGN                       0
#define RX1_ANARXACONTROL2_IMIN_CLKBUF_BITS                        1
#define RX1_ANARXACONTROL2_IMIN_CLKBUF_SHIFT                       13

/* Rx1 :: anaRxAControl2 :: imax_eqfl [12:12] */
#define RX1_ANARXACONTROL2_IMAX_EQFL_MASK                          0x1000
#define RX1_ANARXACONTROL2_IMAX_EQFL_ALIGN                         0
#define RX1_ANARXACONTROL2_IMAX_EQFL_BITS                          1
#define RX1_ANARXACONTROL2_IMAX_EQFL_SHIFT                         12

/* Rx1 :: anaRxAControl2 :: imode_eqfl [11:11] */
#define RX1_ANARXACONTROL2_IMODE_EQFL_MASK                         0x0800
#define RX1_ANARXACONTROL2_IMODE_EQFL_ALIGN                        0
#define RX1_ANARXACONTROL2_IMODE_EQFL_BITS                         1
#define RX1_ANARXACONTROL2_IMODE_EQFL_SHIFT                        11

/* Rx1 :: anaRxAControl2 :: imin_eqfl [10:10] */
#define RX1_ANARXACONTROL2_IMIN_EQFL_MASK                          0x0400
#define RX1_ANARXACONTROL2_IMIN_EQFL_ALIGN                         0
#define RX1_ANARXACONTROL2_IMIN_EQFL_BITS                          1
#define RX1_ANARXACONTROL2_IMIN_EQFL_SHIFT                         10

/* Rx1 :: anaRxAControl2 :: imax_dfesum [09:09] */
#define RX1_ANARXACONTROL2_IMAX_DFESUM_MASK                        0x0200
#define RX1_ANARXACONTROL2_IMAX_DFESUM_ALIGN                       0
#define RX1_ANARXACONTROL2_IMAX_DFESUM_BITS                        1
#define RX1_ANARXACONTROL2_IMAX_DFESUM_SHIFT                       9

/* Rx1 :: anaRxAControl2 :: imode_dfesum [08:08] */
#define RX1_ANARXACONTROL2_IMODE_DFESUM_MASK                       0x0100
#define RX1_ANARXACONTROL2_IMODE_DFESUM_ALIGN                      0
#define RX1_ANARXACONTROL2_IMODE_DFESUM_BITS                       1
#define RX1_ANARXACONTROL2_IMODE_DFESUM_SHIFT                      8

/* Rx1 :: anaRxAControl2 :: imin_dfesum [07:07] */
#define RX1_ANARXACONTROL2_IMIN_DFESUM_MASK                        0x0080
#define RX1_ANARXACONTROL2_IMIN_DFESUM_ALIGN                       0
#define RX1_ANARXACONTROL2_IMIN_DFESUM_BITS                        1
#define RX1_ANARXACONTROL2_IMIN_DFESUM_SHIFT                       7

/* Rx1 :: anaRxAControl2 :: imax_vga [06:06] */
#define RX1_ANARXACONTROL2_IMAX_VGA_MASK                           0x0040
#define RX1_ANARXACONTROL2_IMAX_VGA_ALIGN                          0
#define RX1_ANARXACONTROL2_IMAX_VGA_BITS                           1
#define RX1_ANARXACONTROL2_IMAX_VGA_SHIFT                          6

/* Rx1 :: anaRxAControl2 :: imode_vga [05:05] */
#define RX1_ANARXACONTROL2_IMODE_VGA_MASK                          0x0020
#define RX1_ANARXACONTROL2_IMODE_VGA_ALIGN                         0
#define RX1_ANARXACONTROL2_IMODE_VGA_BITS                          1
#define RX1_ANARXACONTROL2_IMODE_VGA_SHIFT                         5

/* Rx1 :: anaRxAControl2 :: imin_vga [04:04] */
#define RX1_ANARXACONTROL2_IMIN_VGA_MASK                           0x0010
#define RX1_ANARXACONTROL2_IMIN_VGA_ALIGN                          0
#define RX1_ANARXACONTROL2_IMIN_VGA_BITS                           1
#define RX1_ANARXACONTROL2_IMIN_VGA_SHIFT                          4

/* Rx1 :: anaRxAControl2 :: imax_interp [03:03] */
#define RX1_ANARXACONTROL2_IMAX_INTERP_MASK                        0x0008
#define RX1_ANARXACONTROL2_IMAX_INTERP_ALIGN                       0
#define RX1_ANARXACONTROL2_IMAX_INTERP_BITS                        1
#define RX1_ANARXACONTROL2_IMAX_INTERP_SHIFT                       3

/* Rx1 :: anaRxAControl2 :: imode_interp [02:02] */
#define RX1_ANARXACONTROL2_IMODE_INTERP_MASK                       0x0004
#define RX1_ANARXACONTROL2_IMODE_INTERP_ALIGN                      0
#define RX1_ANARXACONTROL2_IMODE_INTERP_BITS                       1
#define RX1_ANARXACONTROL2_IMODE_INTERP_SHIFT                      2

/* Rx1 :: anaRxAControl2 :: imin_interp [01:01] */
#define RX1_ANARXACONTROL2_IMIN_INTERP_MASK                        0x0002
#define RX1_ANARXACONTROL2_IMIN_INTERP_ALIGN                       0
#define RX1_ANARXACONTROL2_IMIN_INTERP_BITS                        1
#define RX1_ANARXACONTROL2_IMIN_INTERP_SHIFT                       1

/* Rx1 :: anaRxAControl2 :: imax_vcm [00:00] */
#define RX1_ANARXACONTROL2_IMAX_VCM_MASK                           0x0001
#define RX1_ANARXACONTROL2_IMAX_VCM_ALIGN                          0
#define RX1_ANARXACONTROL2_IMAX_VCM_BITS                           1
#define RX1_ANARXACONTROL2_IMAX_VCM_SHIFT                          0


/****************************************************************************
 * Rx1 :: anaRxAControl3
 ***************************************************************************/
/* Rx1 :: anaRxAControl3 :: en_clk16 [15:15] */
#define RX1_ANARXACONTROL3_EN_CLK16_MASK                           0x8000
#define RX1_ANARXACONTROL3_EN_CLK16_ALIGN                          0
#define RX1_ANARXACONTROL3_EN_CLK16_BITS                           1
#define RX1_ANARXACONTROL3_EN_CLK16_SHIFT                          15

/* Rx1 :: anaRxAControl3 :: pd_ch_p1 [14:14] */
#define RX1_ANARXACONTROL3_PD_CH_P1_MASK                           0x4000
#define RX1_ANARXACONTROL3_PD_CH_P1_ALIGN                          0
#define RX1_ANARXACONTROL3_PD_CH_P1_BITS                           1
#define RX1_ANARXACONTROL3_PD_CH_P1_SHIFT                          14

/* Rx1 :: anaRxAControl3 :: en_vcctrl [13:13] */
#define RX1_ANARXACONTROL3_EN_VCCTRL_MASK                          0x2000
#define RX1_ANARXACONTROL3_EN_VCCTRL_ALIGN                         0
#define RX1_ANARXACONTROL3_EN_VCCTRL_BITS                          1
#define RX1_ANARXACONTROL3_EN_VCCTRL_SHIFT                         13

/* Rx1 :: anaRxAControl3 :: en_dfeclk [12:12] */
#define RX1_ANARXACONTROL3_EN_DFECLK_MASK                          0x1000
#define RX1_ANARXACONTROL3_EN_DFECLK_ALIGN                         0
#define RX1_ANARXACONTROL3_EN_DFECLK_BITS                          1
#define RX1_ANARXACONTROL3_EN_DFECLK_SHIFT                         12

/* Rx1 :: anaRxAControl3 :: en_hgain [11:11] */
#define RX1_ANARXACONTROL3_EN_HGAIN_MASK                           0x0800
#define RX1_ANARXACONTROL3_EN_HGAIN_ALIGN                          0
#define RX1_ANARXACONTROL3_EN_HGAIN_BITS                           1
#define RX1_ANARXACONTROL3_EN_HGAIN_SHIFT                          11

/* Rx1 :: anaRxAControl3 :: en_dfeckpwr [10:10] */
#define RX1_ANARXACONTROL3_EN_DFECKPWR_MASK                        0x0400
#define RX1_ANARXACONTROL3_EN_DFECKPWR_ALIGN                       0
#define RX1_ANARXACONTROL3_EN_DFECKPWR_BITS                        1
#define RX1_ANARXACONTROL3_EN_DFECKPWR_SHIFT                       10

/* Rx1 :: anaRxAControl3 :: offset_pd [09:09] */
#define RX1_ANARXACONTROL3_OFFSET_PD_MASK                          0x0200
#define RX1_ANARXACONTROL3_OFFSET_PD_ALIGN                         0
#define RX1_ANARXACONTROL3_OFFSET_PD_BITS                          1
#define RX1_ANARXACONTROL3_OFFSET_PD_SHIFT                         9

/* Rx1 :: anaRxAControl3 :: imax_dfetap [08:08] */
#define RX1_ANARXACONTROL3_IMAX_DFETAP_MASK                        0x0100
#define RX1_ANARXACONTROL3_IMAX_DFETAP_ALIGN                       0
#define RX1_ANARXACONTROL3_IMAX_DFETAP_BITS                        1
#define RX1_ANARXACONTROL3_IMAX_DFETAP_SHIFT                       8

/* Rx1 :: anaRxAControl3 :: imode_dfetap [07:07] */
#define RX1_ANARXACONTROL3_IMODE_DFETAP_MASK                       0x0080
#define RX1_ANARXACONTROL3_IMODE_DFETAP_ALIGN                      0
#define RX1_ANARXACONTROL3_IMODE_DFETAP_BITS                       1
#define RX1_ANARXACONTROL3_IMODE_DFETAP_SHIFT                      7

/* Rx1 :: anaRxAControl3 :: imin_dfetap [06:06] */
#define RX1_ANARXACONTROL3_IMIN_DFETAP_MASK                        0x0040
#define RX1_ANARXACONTROL3_IMIN_DFETAP_ALIGN                       0
#define RX1_ANARXACONTROL3_IMIN_DFETAP_BITS                        1
#define RX1_ANARXACONTROL3_IMIN_DFETAP_SHIFT                       6

/* Rx1 :: anaRxAControl3 :: imax_slcd2c [05:05] */
#define RX1_ANARXACONTROL3_IMAX_SLCD2C_MASK                        0x0020
#define RX1_ANARXACONTROL3_IMAX_SLCD2C_ALIGN                       0
#define RX1_ANARXACONTROL3_IMAX_SLCD2C_BITS                        1
#define RX1_ANARXACONTROL3_IMAX_SLCD2C_SHIFT                       5

/* Rx1 :: anaRxAControl3 :: imode_slcd2c [04:04] */
#define RX1_ANARXACONTROL3_IMODE_SLCD2C_MASK                       0x0010
#define RX1_ANARXACONTROL3_IMODE_SLCD2C_ALIGN                      0
#define RX1_ANARXACONTROL3_IMODE_SLCD2C_BITS                       1
#define RX1_ANARXACONTROL3_IMODE_SLCD2C_SHIFT                      4

/* Rx1 :: anaRxAControl3 :: imin_slcd2c [03:03] */
#define RX1_ANARXACONTROL3_IMIN_SLCD2C_MASK                        0x0008
#define RX1_ANARXACONTROL3_IMIN_SLCD2C_ALIGN                       0
#define RX1_ANARXACONTROL3_IMIN_SLCD2C_BITS                        1
#define RX1_ANARXACONTROL3_IMIN_SLCD2C_SHIFT                       3

/* Rx1 :: anaRxAControl3 :: imax_dfevref [02:02] */
#define RX1_ANARXACONTROL3_IMAX_DFEVREF_MASK                       0x0004
#define RX1_ANARXACONTROL3_IMAX_DFEVREF_ALIGN                      0
#define RX1_ANARXACONTROL3_IMAX_DFEVREF_BITS                       1
#define RX1_ANARXACONTROL3_IMAX_DFEVREF_SHIFT                      2

/* Rx1 :: anaRxAControl3 :: imode_dfevref [01:01] */
#define RX1_ANARXACONTROL3_IMODE_DFEVREF_MASK                      0x0002
#define RX1_ANARXACONTROL3_IMODE_DFEVREF_ALIGN                     0
#define RX1_ANARXACONTROL3_IMODE_DFEVREF_BITS                      1
#define RX1_ANARXACONTROL3_IMODE_DFEVREF_SHIFT                     1

/* Rx1 :: anaRxAControl3 :: imin_dfevref [00:00] */
#define RX1_ANARXACONTROL3_IMIN_DFEVREF_MASK                       0x0001
#define RX1_ANARXACONTROL3_IMIN_DFEVREF_ALIGN                      0
#define RX1_ANARXACONTROL3_IMIN_DFEVREF_BITS                       1
#define RX1_ANARXACONTROL3_IMIN_DFEVREF_SHIFT                      0


/****************************************************************************
 * Hypercore_USER_Rx2
 ***************************************************************************/
/****************************************************************************
 * Rx2 :: anaRxStatus
 ***************************************************************************/
/* union - case sigdet_Status [15:00] */
/* Rx2 :: anaRxStatus :: cx4_sigdet [15:15] */
#define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK              0x8000
#define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN             0
#define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS              1
#define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT             15

/* Rx2 :: anaRxStatus :: reserved0 [14:13] */
#define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK               0x6000
#define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN              0
#define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS               2
#define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT              13

/* Rx2 :: anaRxStatus :: rxSeqDone [12:12] */
#define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK               0x1000
#define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN              0
#define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS               1
#define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT              12

/* Rx2 :: anaRxStatus :: rx_sigdet_ll [11:11] */
#define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK            0x0800
#define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN           0
#define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS            1
#define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT           11

/* Rx2 :: anaRxStatus :: cs4_sigdet_ll [10:10] */
#define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK           0x0400
#define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN          0
#define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS           1
#define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT          10

/* Rx2 :: anaRxStatus :: rx_reset [09:09] */
#define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK                0x0200
#define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN               0
#define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS                1
#define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT               9

/* Rx2 :: anaRxStatus :: rx_pwrdn [08:08] */
#define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK                0x0100
#define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN               0
#define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS                1
#define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT               8

/* Rx2 :: anaRxStatus :: reserved1 [07:00] */
#define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK               0x00ff
#define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN              0
#define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS               8
#define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT              0


/* union - case sync_Status [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:11] */
#define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK                 0xf800
#define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN                0
#define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS                 5
#define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT                11

/* Rx2 :: anaRxStatus :: test_acq_en [10:10] */
#define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK               0x0400
#define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN              0
#define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS               1
#define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT              10

/* Rx2 :: anaRxStatus :: reserved1 [09:09] */
#define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK                 0x0200
#define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN                0
#define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS                 1
#define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT                9

/* Rx2 :: anaRxStatus :: rxSeqStart [08:08] */
#define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK                0x0100
#define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN               0
#define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS                1
#define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT               8

/* Rx2 :: anaRxStatus :: mux_comadj_sync_status [07:07] */
#define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK    0x0080
#define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN   0
#define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS    1
#define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT   7

/* Rx2 :: anaRxStatus :: sync_status [06:06] */
#define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK               0x0040
#define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN              0
#define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS               1
#define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT              6

/* Rx2 :: anaRxStatus :: rx_sigdet [05:05] */
#define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK                 0x0020
#define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN                0
#define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS                 1
#define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT                5

/* Rx2 :: anaRxStatus :: reserved2 [04:03] */
#define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK                 0x0018
#define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN                0
#define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS                 2
#define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT                3

/* Rx2 :: anaRxStatus :: saturate_status [02:02] */
#define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK           0x0004
#define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN          0
#define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS           1
#define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT          2

/* Rx2 :: anaRxStatus :: cx4_sigdet [01:01] */
#define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK                0x0002
#define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN               0
#define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS                1
#define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT               1

/* Rx2 :: anaRxStatus :: rxSeqDone [00:00] */
#define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK                 0x0001
#define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN                0
#define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS                 1
#define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT                0


/* union - case rxTestSel_0 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:10] */
#define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK                 0xfc00
#define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN                0
#define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS                 6
#define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT                10

/* Rx2 :: anaRxStatus :: indck_mode_en [09:09] */
#define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK             0x0200
#define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN            0
#define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS             1
#define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT            9

/* Rx2 :: anaRxStatus :: pci_mode_en [08:08] */
#define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK               0x0100
#define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN              0
#define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS               1
#define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT              8

/* Rx2 :: anaRxStatus :: rx_polarity [07:07] */
#define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK               0x0080
#define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN              0
#define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS               1
#define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT              7

/* Rx2 :: anaRxStatus :: rxpol_flip [06:06] */
#define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK                0x0040
#define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN               0
#define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS                1
#define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT               6

/* Rx2 :: anaRxStatus :: comma_mask [05:05] */
#define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK                0x0020
#define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN               0
#define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS                1
#define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT               5

/* Rx2 :: anaRxStatus :: link_en_r [04:04] */
#define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK                 0x0010
#define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN                0
#define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS                 1
#define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT                4

/* Rx2 :: anaRxStatus :: comma_adj_en [03:03] */
#define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK              0x0008
#define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN             0
#define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS              1
#define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT             3

/* Rx2 :: anaRxStatus :: comma_adj_en_ext [02:02] */
#define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK          0x0004
#define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN         0
#define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS          1
#define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT         2

/* Rx2 :: anaRxStatus :: reserved1 [01:00] */
#define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK                 0x0003
#define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN                0
#define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS                 2
#define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT                0


/* union - case rxTestSel_1 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:05] */
#define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK                 0xffe0
#define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN                0
#define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS                 11
#define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT                5

/* Rx2 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */
#define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK             0x0010
#define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN            0
#define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS             1
#define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT            4

/* Rx2 :: anaRxStatus :: freq_sel_PC [03:03] */
#define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK               0x0008
#define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN              0
#define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS               1
#define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT              3

/* Rx2 :: anaRxStatus :: freq_sel_SM [02:02] */
#define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK               0x0004
#define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN              0
#define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS               1
#define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT              2

/* Rx2 :: anaRxStatus :: integ_mode_SM [01:00] */
#define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK             0x0003
#define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN            0
#define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS             2
#define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT            0


/* union - case scale_Status [15:00] */
/* Rx2 :: anaRxStatus :: prop_scale [15:12] */
#define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK               0xf000
#define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN              0
#define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS               4
#define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT              12

/* Rx2 :: anaRxStatus :: integ_scale [11:08] */
#define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK              0x0f00
#define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN             0
#define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS              4
#define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT             8

/* Rx2 :: anaRxStatus :: prop_scale_acq [07:04] */
#define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK           0x00f0
#define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN          0
#define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS           4
#define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT          4

/* Rx2 :: anaRxStatus :: integ_scale_acq [03:00] */
#define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK          0x000f
#define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN         0
#define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS          4
#define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT         0


/* union - case adc_CdrStatus1 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:07] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK              0xff80
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN             0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS              9
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT             7

/* Rx2 :: anaRxStatus :: rxMuxCkSel [06:06] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK             0x0040
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN            0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS             1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT            6

/* Rx2 :: anaRxStatus :: glpbk_combo [05:05] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK            0x0020
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN           0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS            1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT           5

/* Rx2 :: anaRxStatus :: clockSwitchSel [04:04] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK         0x0010
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN        0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS         1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT        4

/* Rx2 :: anaRxStatus :: rxck_tst [03:03] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK               0x0008
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN              0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS               1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT              3

/* Rx2 :: anaRxStatus :: rxck_i [02:02] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK                 0x0004
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN                0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS                 1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT                2

/* Rx2 :: anaRxStatus :: refclk [01:01] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK                 0x0002
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN                0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS                 1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT                1

/* Rx2 :: anaRxStatus :: pll_bypass [00:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK             0x0001
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN            0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS             1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT            0


/* union - case adc_CdrStatus2 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:06] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK              0xffc0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN             0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS              10
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT             6

/* Rx2 :: anaRxStatus :: rxMuxCkSel [05:05] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK             0x0020
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN            0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS             1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT            5

/* Rx2 :: anaRxStatus :: rxSeqStart [04:04] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK             0x0010
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN            0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS             1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT            4

/* Rx2 :: anaRxStatus :: reserved1 [03:01] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK              0x000e
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN             0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS              3
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT             1

/* Rx2 :: anaRxStatus :: rxSeqDone [00:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK              0x0001
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN             0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS              1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT             0


/* union - case adc_CdrStatus3 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:04] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK              0xfff0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN             0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS              12
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT             4

/* Rx2 :: anaRxStatus :: rxSeqStart [03:03] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK             0x0008
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN            0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS             1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT            3

/* Rx2 :: anaRxStatus :: reserved1 [02:01] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK              0x0006
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN             0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS              2
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT             1

/* Rx2 :: anaRxStatus :: allow_increment_PC [00:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK     0x0001
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN    0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS     1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT    0


/* union - case adc_CdrStatus4 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:08] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK              0xff00
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN             0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS              8
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT             8

/* Rx2 :: anaRxStatus :: rx_pwrdn [07:07] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK               0x0080
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN              0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS               1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT              7

/* Rx2 :: anaRxStatus :: freq_sel [06:06] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK               0x0040
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN              0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS               1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT              6

/* Rx2 :: anaRxStatus :: pll_lock_rstb [05:05] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK          0x0020
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN         0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS          1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT         5

/* Rx2 :: anaRxStatus :: pwrdn [04:04] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK                  0x0010
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                 0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS                  1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                 4

/* Rx2 :: anaRxStatus :: reserved1 [03:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK              0x000f
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN             0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS              4
#define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT             0


/* union - case adc_CdrStatus5 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK              0xffff
#define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN             0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS              16
#define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT             0


/* union - case adc_CdrStatus6 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:05] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK              0xffe0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN             0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS              11
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT             5

/* Rx2 :: anaRxStatus :: rx_reset [04:04] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK               0x0010
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN              0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS               1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT              4

/* Rx2 :: anaRxStatus :: rx_pwrdn [03:03] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK               0x0008
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN              0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS               1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT              3

/* Rx2 :: anaRxStatus :: reset_anlg [02:02] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK             0x0004
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN            0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS             1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT            2

/* Rx2 :: anaRxStatus :: pwrdn_rx [01:01] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK               0x0002
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN              0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS               1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT              1

/* Rx2 :: anaRxStatus :: pwrdn_pll [00:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK              0x0001
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN             0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS              1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT             0


/* union - case adc_CdrStatus7e [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:05] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK             0xffe0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN            0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS             11
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT            5

/* Rx2 :: anaRxStatus :: rxck0_even [04:04] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK            0x0010
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN           0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS            1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT           4

/* Rx2 :: anaRxStatus :: rxck1_even [03:03] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK            0x0008
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN           0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS            1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT           3

/* Rx2 :: anaRxStatus :: comdet_even [02:02] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK           0x0004
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN          0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS           1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT          2

/* Rx2 :: anaRxStatus :: en_cdet_even [01:01] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK          0x0002
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN         0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS          1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT         1

/* Rx2 :: anaRxStatus :: comma_adj_en_even [00:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK     0x0001
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN    0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS     1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT    0


/* union - case adc_CdrStatus7o [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:05] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK             0xffe0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN            0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS             11
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT            5

/* Rx2 :: anaRxStatus :: rxck0_odd [04:04] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK             0x0010
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN            0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS             1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT            4

/* Rx2 :: anaRxStatus :: rxck1_odd [03:03] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK             0x0008
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN            0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS             1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT            3

/* Rx2 :: anaRxStatus :: comdet_odd [02:02] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK            0x0004
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN           0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS            1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT           2

/* Rx2 :: anaRxStatus :: en_cdet_odd [01:01] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK           0x0002
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN          0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS           1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT          1

/* Rx2 :: anaRxStatus :: comma_adj_en_odd [00:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK      0x0001
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN     0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS      1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT     0


/* union - case adc_CdrStatus8 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:01] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK              0xfffe
#define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN             0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS              15
#define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT             1

/* Rx2 :: anaRxStatus :: sigdet [00:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK                 0x0001
#define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN                0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS                 1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT                0


/* union - case adc_CdrStatus9 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK              0xffff
#define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN             0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS              16
#define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT             0


/* union - case adc_CdrStatus10 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:07] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK             0xff80
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN            0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS             9
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT            7

/* Rx2 :: anaRxStatus :: prbs_en [06:06] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK               0x0040
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN              0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS               1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT              6

/* Rx2 :: anaRxStatus :: rstb_tst [05:05] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK              0x0020
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN             0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS              1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT             5

/* Rx2 :: anaRxStatus :: reserved1 [04:04] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK             0x0010
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN            0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS             1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT            4

/* Rx2 :: anaRxStatus :: prbs_state [03:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK            0x000f
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN           0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS            4
#define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT           0


/* union - case adc_CdrStatus11 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK             0xffff
#define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN            0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS             16
#define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT            0


/* union - case adc_CdrStatus12_1 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:06] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK           0xffc0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN          0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS           10
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT          6

/* Rx2 :: anaRxStatus :: enable4 [05:05] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK             0x0020
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN            0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS             1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT            5

/* Rx2 :: anaRxStatus :: radr_test [04:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK           0x001f
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN          0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS           5
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT          0


/* union - case adc_CdrStatus12_2 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:05] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK           0xffe0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN          0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS           11
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT          5

/* Rx2 :: anaRxStatus :: wadr_test [04:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK           0x001f
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN          0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS           5
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT          0


/* union - case adc_CdrStatus12_3 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:06] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK           0xffc0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN          0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS           10
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT          6

/* Rx2 :: anaRxStatus :: rxck_66B_tmux [05:05] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK       0x0020
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN      0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS       1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT      5

/* Rx2 :: anaRxStatus :: rstb_66B [04:04] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK            0x0010
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN           0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS            1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT           4

/* Rx2 :: anaRxStatus :: prstb_66B_mux [03:03] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK       0x0008
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN      0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS       1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT      3

/* Rx2 :: anaRxStatus :: rxck_i66_tmux [02:02] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK       0x0004
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN      0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS       1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT      2

/* Rx2 :: anaRxStatus :: rstb_i66 [01:01] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK            0x0002
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN           0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS            1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT           1

/* Rx2 :: anaRxStatus :: prstb_i66_mux [00:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK       0x0001
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN      0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS       1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT      0


/* union - case adc_CdrStatus12_4 [15:00] */
/* Rx2 :: anaRxStatus :: reserved0 [15:04] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK           0xfff0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN          0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS           12
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT          4

/* Rx2 :: anaRxStatus :: rfifo_error_r [03:02] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK       0x000c
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN      0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS       2
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT      2

/* Rx2 :: anaRxStatus :: rfifo_unflow [01:01] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK        0x0002
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN       0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS        1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT       1

/* Rx2 :: anaRxStatus :: rfifo_ovflow [00:00] */
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK        0x0001
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN       0
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS        1
#define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT       0


/* union - case integ_Status [15:00] */
/* Rx2 :: anaRxStatus :: integ_status [15:00] */
#define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK             0xffff
#define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN            0
#define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS             16
#define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT            0


/* union - case vco_Status [15:00] */
/* Rx2 :: anaRxStatus :: vco_status [15:00] */
#define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK                 0xffff
#define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN                0
#define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS                 16
#define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT                0


/* union - case prbs_Status [15:00] */
/* Rx2 :: anaRxStatus :: prbs_lock [15:15] */
#define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK                 0x8000
#define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN                0
#define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS                 1
#define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT                15

/* Rx2 :: anaRxStatus :: prbs_stky [14:14] */
#define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK                 0x4000
#define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN                0
#define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS                 1
#define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT                14

/* Rx2 :: anaRxStatus :: ptbs_errors [13:00] */
#define RX2_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK               0x3fff
#define RX2_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN              0
#define RX2_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS               14
#define RX2_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT              0



/****************************************************************************
 * Rx2 :: anaRxControl
 ***************************************************************************/
/* Rx2 :: anaRxControl :: reserved0 [15:10] */
#define RX2_ANARXCONTROL_RESERVED0_MASK                            0xfc00
#define RX2_ANARXCONTROL_RESERVED0_ALIGN                           0
#define RX2_ANARXCONTROL_RESERVED0_BITS                            6
#define RX2_ANARXCONTROL_RESERVED0_SHIFT                           10

/* Rx2 :: anaRxControl :: override_sigdet_en [09:09] */
#define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK                   0x0200
#define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN                  0
#define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS                   1
#define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT                  9

/* Rx2 :: anaRxControl :: override_sigdet_val [08:08] */
#define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK                  0x0100
#define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN                 0
#define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS                  1
#define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT                 8

/* Rx2 :: anaRxControl :: reserved1 [07:03] */
#define RX2_ANARXCONTROL_RESERVED1_MASK                            0x00f8
#define RX2_ANARXCONTROL_RESERVED1_ALIGN                           0
#define RX2_ANARXCONTROL_RESERVED1_BITS                            5
#define RX2_ANARXCONTROL_RESERVED1_SHIFT                           3

/* Rx2 :: anaRxControl :: status_sel [02:00] */
#define RX2_ANARXCONTROL_STATUS_SEL_MASK                           0x0007
#define RX2_ANARXCONTROL_STATUS_SEL_ALIGN                          0
#define RX2_ANARXCONTROL_STATUS_SEL_BITS                           3
#define RX2_ANARXCONTROL_STATUS_SEL_SHIFT                          0
#define RX2_ANARXCONTROL_STATUS_SEL_sigdetStatus                   0
#define RX2_ANARXCONTROL_STATUS_SEL_syncStatus                     1
#define RX2_ANARXCONTROL_STATUS_SEL_rxTestSel                      2
#define RX2_ANARXCONTROL_STATUS_SEL_scaleStatus                    3
#define RX2_ANARXCONTROL_STATUS_SEL_adcCdrStatus                   4
#define RX2_ANARXCONTROL_STATUS_SEL_integStatus                    5
#define RX2_ANARXCONTROL_STATUS_SEL_vcoStatus                      6
#define RX2_ANARXCONTROL_STATUS_SEL_prbsStatus                     7


/****************************************************************************
 * Rx2 :: anaRxTest
 ***************************************************************************/
/* Rx2 :: anaRxTest :: sigdet_mux_SM [15:12] */
#define RX2_ANARXTEST_SIGDET_MUX_SM_MASK                           0xf000
#define RX2_ANARXTEST_SIGDET_MUX_SM_ALIGN                          0
#define RX2_ANARXTEST_SIGDET_MUX_SM_BITS                           4
#define RX2_ANARXTEST_SIGDET_MUX_SM_SHIFT                          12

/* Rx2 :: anaRxTest :: reserved0 [11:09] */
#define RX2_ANARXTEST_RESERVED0_MASK                               0x0e00
#define RX2_ANARXTEST_RESERVED0_ALIGN                              0
#define RX2_ANARXTEST_RESERVED0_BITS                               3
#define RX2_ANARXTEST_RESERVED0_SHIFT                              9

/* Rx2 :: anaRxTest :: tpctrl_SM [08:04] */
#define RX2_ANARXTEST_TPCTRL_SM_MASK                               0x01f0
#define RX2_ANARXTEST_TPCTRL_SM_ALIGN                              0
#define RX2_ANARXTEST_TPCTRL_SM_BITS                               5
#define RX2_ANARXTEST_TPCTRL_SM_SHIFT                              4

/* Rx2 :: anaRxTest :: testMuxSelect_SM [03:00] */
#define RX2_ANARXTEST_TESTMUXSELECT_SM_MASK                        0x000f
#define RX2_ANARXTEST_TESTMUXSELECT_SM_ALIGN                       0
#define RX2_ANARXTEST_TESTMUXSELECT_SM_BITS                        4
#define RX2_ANARXTEST_TESTMUXSELECT_SM_SHIFT                       0


/****************************************************************************
 * Rx2 :: anaRxControl1G
 ***************************************************************************/
/* Rx2 :: anaRxControl1G :: fpat_md [15:15] */
#define RX2_ANARXCONTROL1G_FPAT_MD_MASK                            0x8000
#define RX2_ANARXCONTROL1G_FPAT_MD_ALIGN                           0
#define RX2_ANARXCONTROL1G_FPAT_MD_BITS                            1
#define RX2_ANARXCONTROL1G_FPAT_MD_SHIFT                           15

/* Rx2 :: anaRxControl1G :: pkt_count_en [14:14] */
#define RX2_ANARXCONTROL1G_PKT_COUNT_EN_MASK                       0x4000
#define RX2_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN                      0
#define RX2_ANARXCONTROL1G_PKT_COUNT_EN_BITS                       1
#define RX2_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT                      14

/* Rx2 :: anaRxControl1G :: staMuxRegDis [13:13] */
#define RX2_ANARXCONTROL1G_STAMUXREGDIS_MASK                       0x2000
#define RX2_ANARXCONTROL1G_STAMUXREGDIS_ALIGN                      0
#define RX2_ANARXCONTROL1G_STAMUXREGDIS_BITS                       1
#define RX2_ANARXCONTROL1G_STAMUXREGDIS_SHIFT                      13

/* Rx2 :: anaRxControl1G :: prbs_clr_dis [12:12] */
#define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_MASK                       0x1000
#define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN                      0
#define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_BITS                       1
#define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT                      12

/* Rx2 :: anaRxControl1G :: rxd_dec_sel [11:11] */
#define RX2_ANARXCONTROL1G_RXD_DEC_SEL_MASK                        0x0800
#define RX2_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN                       0
#define RX2_ANARXCONTROL1G_RXD_DEC_SEL_BITS                        1
#define RX2_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT                       11

/* Rx2 :: anaRxControl1G :: cgbad_tst [10:10] */
#define RX2_ANARXCONTROL1G_CGBAD_TST_MASK                          0x0400
#define RX2_ANARXCONTROL1G_CGBAD_TST_ALIGN                         0
#define RX2_ANARXCONTROL1G_CGBAD_TST_BITS                          1
#define RX2_ANARXCONTROL1G_CGBAD_TST_SHIFT                         10

/* Rx2 :: anaRxControl1G :: Emon_en [09:09] */
#define RX2_ANARXCONTROL1G_EMON_EN_MASK                            0x0200
#define RX2_ANARXCONTROL1G_EMON_EN_ALIGN                           0
#define RX2_ANARXCONTROL1G_EMON_EN_BITS                            1
#define RX2_ANARXCONTROL1G_EMON_EN_SHIFT                           9

/* Rx2 :: anaRxControl1G :: prbs_en [08:08] */
#define RX2_ANARXCONTROL1G_PRBS_EN_MASK                            0x0100
#define RX2_ANARXCONTROL1G_PRBS_EN_ALIGN                           0
#define RX2_ANARXCONTROL1G_PRBS_EN_BITS                            1
#define RX2_ANARXCONTROL1G_PRBS_EN_SHIFT                           8

/* Rx2 :: anaRxControl1G :: cgbad_en [07:07] */
#define RX2_ANARXCONTROL1G_CGBAD_EN_MASK                           0x0080
#define RX2_ANARXCONTROL1G_CGBAD_EN_ALIGN                          0
#define RX2_ANARXCONTROL1G_CGBAD_EN_BITS                           1
#define RX2_ANARXCONTROL1G_CGBAD_EN_SHIFT                          7

/* Rx2 :: anaRxControl1G :: cstretch [06:06] */
#define RX2_ANARXCONTROL1G_CSTRETCH_MASK                           0x0040
#define RX2_ANARXCONTROL1G_CSTRETCH_ALIGN                          0
#define RX2_ANARXCONTROL1G_CSTRETCH_BITS                           1
#define RX2_ANARXCONTROL1G_CSTRETCH_SHIFT                          6

/* Rx2 :: anaRxControl1G :: comma_low_byte_SM [05:05] */
#define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK                  0x0020
#define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN                 0
#define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS                  1
#define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT                 5

/* Rx2 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */
#define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK               0x0010
#define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN              0
#define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS               1
#define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT              4

/* Rx2 :: anaRxControl1G :: reserved0 [03:02] */
#define RX2_ANARXCONTROL1G_RESERVED0_MASK                          0x000c
#define RX2_ANARXCONTROL1G_RESERVED0_ALIGN                         0
#define RX2_ANARXCONTROL1G_RESERVED0_BITS                          2
#define RX2_ANARXCONTROL1G_RESERVED0_SHIFT                         2

/* Rx2 :: anaRxControl1G :: freq_sel_force [01:01] */
#define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK                     0x0002
#define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN                    0
#define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS                     1
#define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT                    1

/* Rx2 :: anaRxControl1G :: freq_sel [00:00] */
#define RX2_ANARXCONTROL1G_FREQ_SEL_MASK                           0x0001
#define RX2_ANARXCONTROL1G_FREQ_SEL_ALIGN                          0
#define RX2_ANARXCONTROL1G_FREQ_SEL_BITS                           1
#define RX2_ANARXCONTROL1G_FREQ_SEL_SHIFT                          0


/****************************************************************************
 * Rx2 :: anaRxControlPci
 ***************************************************************************/
/* Rx2 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK                0x8000
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN               0
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS                1
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT               15

/* Rx2 :: anaRxControlPci :: comma_mask_force_r [14:14] */
#define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK                0x4000
#define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN               0
#define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS                1
#define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT               14

/* Rx2 :: anaRxControlPci :: comma_mask_r [13:13] */
#define RX2_ANARXCONTROLPCI_COMMA_MASK_R_MASK                      0x2000
#define RX2_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN                     0
#define RX2_ANARXCONTROLPCI_COMMA_MASK_R_BITS                      1
#define RX2_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT                     13

/* Rx2 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */
#define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK         0x1000
#define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN        0
#define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS         1
#define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT        12

/* Rx2 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */
#define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK            0x0800
#define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN           0
#define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS            1
#define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT           11

/* Rx2 :: anaRxControlPci :: sync_status_force_r [10:10] */
#define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK               0x0400
#define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN              0
#define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS               1
#define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT              10

/* Rx2 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK         0x0200
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN        0
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS         1
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT        9

/* Rx2 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK        0x0100
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN       0
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS        1
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT       8

/* Rx2 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK           0x0080
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN          0
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS           1
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT          7

/* Rx2 :: anaRxControlPci :: comma_adj_en_r [06:06] */
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK                    0x0040
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN                   0
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS                    1
#define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT                   6

/* Rx2 :: anaRxControlPci :: link_en_force_SM [05:05] */
#define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK                  0x0020
#define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN                 0
#define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS                  1
#define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT                 5

/* Rx2 :: anaRxControlPci :: link_en_r [04:04] */
#define RX2_ANARXCONTROLPCI_LINK_EN_R_MASK                         0x0010
#define RX2_ANARXCONTROLPCI_LINK_EN_R_ALIGN                        0
#define RX2_ANARXCONTROLPCI_LINK_EN_R_BITS                         1
#define RX2_ANARXCONTROLPCI_LINK_EN_R_SHIFT                        4

/* Rx2 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */
#define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK              0x0008
#define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN             0
#define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS              1
#define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT             3

/* Rx2 :: anaRxControlPci :: rx_polarity_r [02:02] */
#define RX2_ANARXCONTROLPCI_RX_POLARITY_R_MASK                     0x0004
#define RX2_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN                    0
#define RX2_ANARXCONTROLPCI_RX_POLARITY_R_BITS                     1
#define RX2_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT                    2

/* Rx2 :: anaRxControlPci :: integ_mode_SM [01:00] */
#define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_MASK                     0x0003
#define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN                    0
#define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_BITS                     2
#define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT                    0


/****************************************************************************
 * Rx2 :: anaRxAstatus
 ***************************************************************************/
/* Rx2 :: anaRxAstatus :: sigdet [15:15] */
#define RX2_ANARXASTATUS_SIGDET_MASK                               0x8000
#define RX2_ANARXASTATUS_SIGDET_ALIGN                              0
#define RX2_ANARXASTATUS_SIGDET_BITS                               1
#define RX2_ANARXASTATUS_SIGDET_SHIFT                              15

/* Rx2 :: anaRxAstatus :: rx_pf [14:12] */
#define RX2_ANARXASTATUS_RX_PF_MASK                                0x7000
#define RX2_ANARXASTATUS_RX_PF_ALIGN                               0
#define RX2_ANARXASTATUS_RX_PF_BITS                                3
#define RX2_ANARXASTATUS_RX_PF_SHIFT                               12

/* Rx2 :: anaRxAstatus :: dfe [11:06] */
#define RX2_ANARXASTATUS_DFE_MASK                                  0x0fc0
#define RX2_ANARXASTATUS_DFE_ALIGN                                 0
#define RX2_ANARXASTATUS_DFE_BITS                                  6
#define RX2_ANARXASTATUS_DFE_SHIFT                                 6

/* Rx2 :: anaRxAstatus :: reserved0 [05:05] */
#define RX2_ANARXASTATUS_RESERVED0_MASK                            0x0020
#define RX2_ANARXASTATUS_RESERVED0_ALIGN                           0
#define RX2_ANARXASTATUS_RESERVED0_BITS                            1
#define RX2_ANARXASTATUS_RESERVED0_SHIFT                           5

/* Rx2 :: anaRxAstatus :: vga [04:00] */
#define RX2_ANARXASTATUS_VGA_MASK                                  0x001f
#define RX2_ANARXASTATUS_VGA_ALIGN                                 0
#define RX2_ANARXASTATUS_VGA_BITS                                  5
#define RX2_ANARXASTATUS_VGA_SHIFT                                 0


/****************************************************************************
 * Rx2 :: anaRxAControl1
 ***************************************************************************/
/* Rx2 :: anaRxAControl1 :: imode_vcm [15:15] */
#define RX2_ANARXACONTROL1_IMODE_VCM_MASK                          0x8000
#define RX2_ANARXACONTROL1_IMODE_VCM_ALIGN                         0
#define RX2_ANARXACONTROL1_IMODE_VCM_BITS                          1
#define RX2_ANARXACONTROL1_IMODE_VCM_SHIFT                         15

/* Rx2 :: anaRxAControl1 :: imin_vcm [14:14] */
#define RX2_ANARXACONTROL1_IMIN_VCM_MASK                           0x4000
#define RX2_ANARXACONTROL1_IMIN_VCM_ALIGN                          0
#define RX2_ANARXACONTROL1_IMIN_VCM_BITS                           1
#define RX2_ANARXACONTROL1_IMIN_VCM_SHIFT                          14

/* Rx2 :: anaRxAControl1 :: imax_sigdet [13:13] */
#define RX2_ANARXACONTROL1_IMAX_SIGDET_MASK                        0x2000
#define RX2_ANARXACONTROL1_IMAX_SIGDET_ALIGN                       0
#define RX2_ANARXACONTROL1_IMAX_SIGDET_BITS                        1
#define RX2_ANARXACONTROL1_IMAX_SIGDET_SHIFT                       13

/* Rx2 :: anaRxAControl1 :: imode_sigdet [12:12] */
#define RX2_ANARXACONTROL1_IMODE_SIGDET_MASK                       0x1000
#define RX2_ANARXACONTROL1_IMODE_SIGDET_ALIGN                      0
#define RX2_ANARXACONTROL1_IMODE_SIGDET_BITS                       1
#define RX2_ANARXACONTROL1_IMODE_SIGDET_SHIFT                      12

/* Rx2 :: anaRxAControl1 :: imin_sigdet [11:11] */
#define RX2_ANARXACONTROL1_IMIN_SIGDET_MASK                        0x0800
#define RX2_ANARXACONTROL1_IMIN_SIGDET_ALIGN                       0
#define RX2_ANARXACONTROL1_IMIN_SIGDET_BITS                        1
#define RX2_ANARXACONTROL1_IMIN_SIGDET_SHIFT                       11

/* Rx2 :: anaRxAControl1 :: refh_rx [10:10] */
#define RX2_ANARXACONTROL1_REFH_RX_MASK                            0x0400
#define RX2_ANARXACONTROL1_REFH_RX_ALIGN                           0
#define RX2_ANARXACONTROL1_REFH_RX_BITS                            1
#define RX2_ANARXACONTROL1_REFH_RX_SHIFT                           10

/* Rx2 :: anaRxAControl1 :: refl_rx [09:09] */
#define RX2_ANARXACONTROL1_REFL_RX_MASK                            0x0200
#define RX2_ANARXACONTROL1_REFL_RX_ALIGN                           0
#define RX2_ANARXACONTROL1_REFL_RX_BITS                            1
#define RX2_ANARXACONTROL1_REFL_RX_SHIFT                           9

/* Rx2 :: anaRxAControl1 :: tport_en [08:08] */
#define RX2_ANARXACONTROL1_TPORT_EN_MASK                           0x0100
#define RX2_ANARXACONTROL1_TPORT_EN_ALIGN                          0
#define RX2_ANARXACONTROL1_TPORT_EN_BITS                           1
#define RX2_ANARXACONTROL1_TPORT_EN_SHIFT                          8

/* Rx2 :: anaRxAControl1 :: vddrb_bg [07:07] */
#define RX2_ANARXACONTROL1_VDDRB_BG_MASK                           0x0080
#define RX2_ANARXACONTROL1_VDDRB_BG_ALIGN                          0
#define RX2_ANARXACONTROL1_VDDRB_BG_BITS                           1
#define RX2_ANARXACONTROL1_VDDRB_BG_SHIFT                          7

/* Rx2 :: anaRxAControl1 :: sig_pwrdn [06:06] */
#define RX2_ANARXACONTROL1_SIG_PWRDN_MASK                          0x0040
#define RX2_ANARXACONTROL1_SIG_PWRDN_ALIGN                         0
#define RX2_ANARXACONTROL1_SIG_PWRDN_BITS                          1
#define RX2_ANARXACONTROL1_SIG_PWRDN_SHIFT                         6

/* Rx2 :: anaRxAControl1 :: offset_ctrl [05:03] */
#define RX2_ANARXACONTROL1_OFFSET_CTRL_MASK                        0x0038
#define RX2_ANARXACONTROL1_OFFSET_CTRL_ALIGN                       0
#define RX2_ANARXACONTROL1_OFFSET_CTRL_BITS                        3
#define RX2_ANARXACONTROL1_OFFSET_CTRL_SHIFT                       3

/* Rx2 :: anaRxAControl1 :: offset_sel [02:02] */
#define RX2_ANARXACONTROL1_OFFSET_SEL_MASK                         0x0004
#define RX2_ANARXACONTROL1_OFFSET_SEL_ALIGN                        0
#define RX2_ANARXACONTROL1_OFFSET_SEL_BITS                         1
#define RX2_ANARXACONTROL1_OFFSET_SEL_SHIFT                        2

/* Rx2 :: anaRxAControl1 :: reserved0 [01:00] */
#define RX2_ANARXACONTROL1_RESERVED0_MASK                          0x0003
#define RX2_ANARXACONTROL1_RESERVED0_ALIGN                         0
#define RX2_ANARXACONTROL1_RESERVED0_BITS                          2
#define RX2_ANARXACONTROL1_RESERVED0_SHIFT                         0


/****************************************************************************
 * Rx2 :: anaRxAControl2
 ***************************************************************************/
/* Rx2 :: anaRxAControl2 :: imax_clkbuf [15:15] */
#define RX2_ANARXACONTROL2_IMAX_CLKBUF_MASK                        0x8000
#define RX2_ANARXACONTROL2_IMAX_CLKBUF_ALIGN                       0
#define RX2_ANARXACONTROL2_IMAX_CLKBUF_BITS                        1
#define RX2_ANARXACONTROL2_IMAX_CLKBUF_SHIFT                       15

/* Rx2 :: anaRxAControl2 :: imode_clkbuf [14:14] */
#define RX2_ANARXACONTROL2_IMODE_CLKBUF_MASK                       0x4000
#define RX2_ANARXACONTROL2_IMODE_CLKBUF_ALIGN                      0
#define RX2_ANARXACONTROL2_IMODE_CLKBUF_BITS                       1
#define RX2_ANARXACONTROL2_IMODE_CLKBUF_SHIFT                      14

/* Rx2 :: anaRxAControl2 :: imin_clkbuf [13:13] */
#define RX2_ANARXACONTROL2_IMIN_CLKBUF_MASK                        0x2000
#define RX2_ANARXACONTROL2_IMIN_CLKBUF_ALIGN                       0
#define RX2_ANARXACONTROL2_IMIN_CLKBUF_BITS                        1
#define RX2_ANARXACONTROL2_IMIN_CLKBUF_SHIFT                       13

/* Rx2 :: anaRxAControl2 :: imax_eqfl [12:12] */
#define RX2_ANARXACONTROL2_IMAX_EQFL_MASK                          0x1000
#define RX2_ANARXACONTROL2_IMAX_EQFL_ALIGN                         0
#define RX2_ANARXACONTROL2_IMAX_EQFL_BITS                          1
#define RX2_ANARXACONTROL2_IMAX_EQFL_SHIFT                         12

/* Rx2 :: anaRxAControl2 :: imode_eqfl [11:11] */
#define RX2_ANARXACONTROL2_IMODE_EQFL_MASK                         0x0800
#define RX2_ANARXACONTROL2_IMODE_EQFL_ALIGN                        0
#define RX2_ANARXACONTROL2_IMODE_EQFL_BITS                         1
#define RX2_ANARXACONTROL2_IMODE_EQFL_SHIFT                        11

/* Rx2 :: anaRxAControl2 :: imin_eqfl [10:10] */
#define RX2_ANARXACONTROL2_IMIN_EQFL_MASK                          0x0400
#define RX2_ANARXACONTROL2_IMIN_EQFL_ALIGN                         0
#define RX2_ANARXACONTROL2_IMIN_EQFL_BITS                          1
#define RX2_ANARXACONTROL2_IMIN_EQFL_SHIFT                         10

/* Rx2 :: anaRxAControl2 :: imax_dfesum [09:09] */
#define RX2_ANARXACONTROL2_IMAX_DFESUM_MASK                        0x0200
#define RX2_ANARXACONTROL2_IMAX_DFESUM_ALIGN                       0
#define RX2_ANARXACONTROL2_IMAX_DFESUM_BITS                        1
#define RX2_ANARXACONTROL2_IMAX_DFESUM_SHIFT                       9

/* Rx2 :: anaRxAControl2 :: imode_dfesum [08:08] */
#define RX2_ANARXACONTROL2_IMODE_DFESUM_MASK                       0x0100
#define RX2_ANARXACONTROL2_IMODE_DFESUM_ALIGN                      0
#define RX2_ANARXACONTROL2_IMODE_DFESUM_BITS                       1
#define RX2_ANARXACONTROL2_IMODE_DFESUM_SHIFT                      8

/* Rx2 :: anaRxAControl2 :: imin_dfesum [07:07] */
#define RX2_ANARXACONTROL2_IMIN_DFESUM_MASK                        0x0080
#define RX2_ANARXACONTROL2_IMIN_DFESUM_ALIGN                       0
#define RX2_ANARXACONTROL2_IMIN_DFESUM_BITS                        1
#define RX2_ANARXACONTROL2_IMIN_DFESUM_SHIFT                       7

/* Rx2 :: anaRxAControl2 :: imax_vga [06:06] */
#define RX2_ANARXACONTROL2_IMAX_VGA_MASK                           0x0040
#define RX2_ANARXACONTROL2_IMAX_VGA_ALIGN                          0
#define RX2_ANARXACONTROL2_IMAX_VGA_BITS                           1
#define RX2_ANARXACONTROL2_IMAX_VGA_SHIFT                          6

/* Rx2 :: anaRxAControl2 :: imode_vga [05:05] */
#define RX2_ANARXACONTROL2_IMODE_VGA_MASK                          0x0020
#define RX2_ANARXACONTROL2_IMODE_VGA_ALIGN                         0
#define RX2_ANARXACONTROL2_IMODE_VGA_BITS                          1
#define RX2_ANARXACONTROL2_IMODE_VGA_SHIFT                         5

/* Rx2 :: anaRxAControl2 :: imin_vga [04:04] */
#define RX2_ANARXACONTROL2_IMIN_VGA_MASK                           0x0010
#define RX2_ANARXACONTROL2_IMIN_VGA_ALIGN                          0
#define RX2_ANARXACONTROL2_IMIN_VGA_BITS                           1
#define RX2_ANARXACONTROL2_IMIN_VGA_SHIFT                          4

/* Rx2 :: anaRxAControl2 :: imax_interp [03:03] */
#define RX2_ANARXACONTROL2_IMAX_INTERP_MASK                        0x0008
#define RX2_ANARXACONTROL2_IMAX_INTERP_ALIGN                       0
#define RX2_ANARXACONTROL2_IMAX_INTERP_BITS                        1
#define RX2_ANARXACONTROL2_IMAX_INTERP_SHIFT                       3

/* Rx2 :: anaRxAControl2 :: imode_interp [02:02] */
#define RX2_ANARXACONTROL2_IMODE_INTERP_MASK                       0x0004
#define RX2_ANARXACONTROL2_IMODE_INTERP_ALIGN                      0
#define RX2_ANARXACONTROL2_IMODE_INTERP_BITS                       1
#define RX2_ANARXACONTROL2_IMODE_INTERP_SHIFT                      2

/* Rx2 :: anaRxAControl2 :: imin_interp [01:01] */
#define RX2_ANARXACONTROL2_IMIN_INTERP_MASK                        0x0002
#define RX2_ANARXACONTROL2_IMIN_INTERP_ALIGN                       0
#define RX2_ANARXACONTROL2_IMIN_INTERP_BITS                        1
#define RX2_ANARXACONTROL2_IMIN_INTERP_SHIFT                       1

/* Rx2 :: anaRxAControl2 :: imax_vcm [00:00] */
#define RX2_ANARXACONTROL2_IMAX_VCM_MASK                           0x0001
#define RX2_ANARXACONTROL2_IMAX_VCM_ALIGN                          0
#define RX2_ANARXACONTROL2_IMAX_VCM_BITS                           1
#define RX2_ANARXACONTROL2_IMAX_VCM_SHIFT                          0


/****************************************************************************
 * Rx2 :: anaRxAControl3
 ***************************************************************************/
/* Rx2 :: anaRxAControl3 :: en_clk16 [15:15] */
#define RX2_ANARXACONTROL3_EN_CLK16_MASK                           0x8000
#define RX2_ANARXACONTROL3_EN_CLK16_ALIGN                          0
#define RX2_ANARXACONTROL3_EN_CLK16_BITS                           1
#define RX2_ANARXACONTROL3_EN_CLK16_SHIFT                          15

/* Rx2 :: anaRxAControl3 :: pd_ch_p1 [14:14] */
#define RX2_ANARXACONTROL3_PD_CH_P1_MASK                           0x4000
#define RX2_ANARXACONTROL3_PD_CH_P1_ALIGN                          0
#define RX2_ANARXACONTROL3_PD_CH_P1_BITS                           1
#define RX2_ANARXACONTROL3_PD_CH_P1_SHIFT                          14

/* Rx2 :: anaRxAControl3 :: en_vcctrl [13:13] */
#define RX2_ANARXACONTROL3_EN_VCCTRL_MASK                          0x2000
#define RX2_ANARXACONTROL3_EN_VCCTRL_ALIGN                         0
#define RX2_ANARXACONTROL3_EN_VCCTRL_BITS                          1
#define RX2_ANARXACONTROL3_EN_VCCTRL_SHIFT                         13

/* Rx2 :: anaRxAControl3 :: en_dfeclk [12:12] */
#define RX2_ANARXACONTROL3_EN_DFECLK_MASK                          0x1000
#define RX2_ANARXACONTROL3_EN_DFECLK_ALIGN                         0
#define RX2_ANARXACONTROL3_EN_DFECLK_BITS                          1
#define RX2_ANARXACONTROL3_EN_DFECLK_SHIFT                         12

/* Rx2 :: anaRxAControl3 :: en_hgain [11:11] */
#define RX2_ANARXACONTROL3_EN_HGAIN_MASK                           0x0800
#define RX2_ANARXACONTROL3_EN_HGAIN_ALIGN                          0
#define RX2_ANARXACONTROL3_EN_HGAIN_BITS                           1
#define RX2_ANARXACONTROL3_EN_HGAIN_SHIFT                          11

/* Rx2 :: anaRxAControl3 :: en_dfeckpwr [10:10] */
#define RX2_ANARXACONTROL3_EN_DFECKPWR_MASK                        0x0400
#define RX2_ANARXACONTROL3_EN_DFECKPWR_ALIGN                       0
#define RX2_ANARXACONTROL3_EN_DFECKPWR_BITS                        1
#define RX2_ANARXACONTROL3_EN_DFECKPWR_SHIFT                       10

/* Rx2 :: anaRxAControl3 :: offset_pd [09:09] */
#define RX2_ANARXACONTROL3_OFFSET_PD_MASK                          0x0200
#define RX2_ANARXACONTROL3_OFFSET_PD_ALIGN                         0
#define RX2_ANARXACONTROL3_OFFSET_PD_BITS                          1
#define RX2_ANARXACONTROL3_OFFSET_PD_SHIFT                         9

/* Rx2 :: anaRxAControl3 :: imax_dfetap [08:08] */
#define RX2_ANARXACONTROL3_IMAX_DFETAP_MASK                        0x0100
#define RX2_ANARXACONTROL3_IMAX_DFETAP_ALIGN                       0
#define RX2_ANARXACONTROL3_IMAX_DFETAP_BITS                        1
#define RX2_ANARXACONTROL3_IMAX_DFETAP_SHIFT                       8

/* Rx2 :: anaRxAControl3 :: imode_dfetap [07:07] */
#define RX2_ANARXACONTROL3_IMODE_DFETAP_MASK                       0x0080
#define RX2_ANARXACONTROL3_IMODE_DFETAP_ALIGN                      0
#define RX2_ANARXACONTROL3_IMODE_DFETAP_BITS                       1
#define RX2_ANARXACONTROL3_IMODE_DFETAP_SHIFT                      7

/* Rx2 :: anaRxAControl3 :: imin_dfetap [06:06] */
#define RX2_ANARXACONTROL3_IMIN_DFETAP_MASK                        0x0040
#define RX2_ANARXACONTROL3_IMIN_DFETAP_ALIGN                       0
#define RX2_ANARXACONTROL3_IMIN_DFETAP_BITS                        1
#define RX2_ANARXACONTROL3_IMIN_DFETAP_SHIFT                       6

/* Rx2 :: anaRxAControl3 :: imax_slcd2c [05:05] */
#define RX2_ANARXACONTROL3_IMAX_SLCD2C_MASK                        0x0020
#define RX2_ANARXACONTROL3_IMAX_SLCD2C_ALIGN                       0
#define RX2_ANARXACONTROL3_IMAX_SLCD2C_BITS                        1
#define RX2_ANARXACONTROL3_IMAX_SLCD2C_SHIFT                       5

/* Rx2 :: anaRxAControl3 :: imode_slcd2c [04:04] */
#define RX2_ANARXACONTROL3_IMODE_SLCD2C_MASK                       0x0010
#define RX2_ANARXACONTROL3_IMODE_SLCD2C_ALIGN                      0
#define RX2_ANARXACONTROL3_IMODE_SLCD2C_BITS                       1
#define RX2_ANARXACONTROL3_IMODE_SLCD2C_SHIFT                      4

/* Rx2 :: anaRxAControl3 :: imin_slcd2c [03:03] */
#define RX2_ANARXACONTROL3_IMIN_SLCD2C_MASK                        0x0008
#define RX2_ANARXACONTROL3_IMIN_SLCD2C_ALIGN                       0
#define RX2_ANARXACONTROL3_IMIN_SLCD2C_BITS                        1
#define RX2_ANARXACONTROL3_IMIN_SLCD2C_SHIFT                       3

/* Rx2 :: anaRxAControl3 :: imax_dfevref [02:02] */
#define RX2_ANARXACONTROL3_IMAX_DFEVREF_MASK                       0x0004
#define RX2_ANARXACONTROL3_IMAX_DFEVREF_ALIGN                      0
#define RX2_ANARXACONTROL3_IMAX_DFEVREF_BITS                       1
#define RX2_ANARXACONTROL3_IMAX_DFEVREF_SHIFT                      2

/* Rx2 :: anaRxAControl3 :: imode_dfevref [01:01] */
#define RX2_ANARXACONTROL3_IMODE_DFEVREF_MASK                      0x0002
#define RX2_ANARXACONTROL3_IMODE_DFEVREF_ALIGN                     0
#define RX2_ANARXACONTROL3_IMODE_DFEVREF_BITS                      1
#define RX2_ANARXACONTROL3_IMODE_DFEVREF_SHIFT                     1

/* Rx2 :: anaRxAControl3 :: imin_dfevref [00:00] */
#define RX2_ANARXACONTROL3_IMIN_DFEVREF_MASK                       0x0001
#define RX2_ANARXACONTROL3_IMIN_DFEVREF_ALIGN                      0
#define RX2_ANARXACONTROL3_IMIN_DFEVREF_BITS                       1
#define RX2_ANARXACONTROL3_IMIN_DFEVREF_SHIFT                      0


/****************************************************************************
 * Hypercore_USER_Rx3
 ***************************************************************************/
/****************************************************************************
 * Rx3 :: anaRxStatus
 ***************************************************************************/
/* union - case sigdet_Status [15:00] */
/* Rx3 :: anaRxStatus :: cx4_sigdet [15:15] */
#define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK              0x8000
#define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN             0
#define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS              1
#define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT             15

/* Rx3 :: anaRxStatus :: reserved0 [14:13] */
#define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK               0x6000
#define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN              0
#define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS               2
#define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT              13

/* Rx3 :: anaRxStatus :: rxSeqDone [12:12] */
#define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK               0x1000
#define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN              0
#define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS               1
#define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT              12

/* Rx3 :: anaRxStatus :: rx_sigdet_ll [11:11] */
#define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK            0x0800
#define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN           0
#define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS            1
#define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT           11

/* Rx3 :: anaRxStatus :: cs4_sigdet_ll [10:10] */
#define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK           0x0400
#define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN          0
#define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS           1
#define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT          10

/* Rx3 :: anaRxStatus :: rx_reset [09:09] */
#define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK                0x0200
#define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN               0
#define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS                1
#define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT               9

/* Rx3 :: anaRxStatus :: rx_pwrdn [08:08] */
#define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK                0x0100
#define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN               0
#define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS                1
#define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT               8

/* Rx3 :: anaRxStatus :: reserved1 [07:00] */
#define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK               0x00ff
#define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN              0
#define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS               8
#define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT              0


/* union - case sync_Status [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:11] */
#define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK                 0xf800
#define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN                0
#define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS                 5
#define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT                11

/* Rx3 :: anaRxStatus :: test_acq_en [10:10] */
#define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK               0x0400
#define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN              0
#define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS               1
#define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT              10

/* Rx3 :: anaRxStatus :: reserved1 [09:09] */
#define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK                 0x0200
#define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN                0
#define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS                 1
#define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT                9

/* Rx3 :: anaRxStatus :: rxSeqStart [08:08] */
#define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK                0x0100
#define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN               0
#define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS                1
#define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT               8

/* Rx3 :: anaRxStatus :: mux_comadj_sync_status [07:07] */
#define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK    0x0080
#define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN   0
#define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS    1
#define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT   7

/* Rx3 :: anaRxStatus :: sync_status [06:06] */
#define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK               0x0040
#define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN              0
#define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS               1
#define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT              6

/* Rx3 :: anaRxStatus :: rx_sigdet [05:05] */
#define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK                 0x0020
#define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN                0
#define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS                 1
#define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT                5

/* Rx3 :: anaRxStatus :: reserved2 [04:03] */
#define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK                 0x0018
#define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN                0
#define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS                 2
#define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT                3

/* Rx3 :: anaRxStatus :: saturate_status [02:02] */
#define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK           0x0004
#define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN          0
#define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS           1
#define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT          2

/* Rx3 :: anaRxStatus :: cx4_sigdet [01:01] */
#define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK                0x0002
#define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN               0
#define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS                1
#define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT               1

/* Rx3 :: anaRxStatus :: rxSeqDone [00:00] */
#define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK                 0x0001
#define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN                0
#define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS                 1
#define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT                0


/* union - case rxTestSel_0 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:10] */
#define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK                 0xfc00
#define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN                0
#define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS                 6
#define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT                10

/* Rx3 :: anaRxStatus :: indck_mode_en [09:09] */
#define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK             0x0200
#define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN            0
#define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS             1
#define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT            9

/* Rx3 :: anaRxStatus :: pci_mode_en [08:08] */
#define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK               0x0100
#define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN              0
#define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS               1
#define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT              8

/* Rx3 :: anaRxStatus :: rx_polarity [07:07] */
#define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK               0x0080
#define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN              0
#define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS               1
#define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT              7

/* Rx3 :: anaRxStatus :: rxpol_flip [06:06] */
#define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK                0x0040
#define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN               0
#define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS                1
#define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT               6

/* Rx3 :: anaRxStatus :: comma_mask [05:05] */
#define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK                0x0020
#define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN               0
#define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS                1
#define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT               5

/* Rx3 :: anaRxStatus :: link_en_r [04:04] */
#define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK                 0x0010
#define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN                0
#define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS                 1
#define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT                4

/* Rx3 :: anaRxStatus :: comma_adj_en [03:03] */
#define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK              0x0008
#define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN             0
#define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS              1
#define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT             3

/* Rx3 :: anaRxStatus :: comma_adj_en_ext [02:02] */
#define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK          0x0004
#define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN         0
#define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS          1
#define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT         2

/* Rx3 :: anaRxStatus :: reserved1 [01:00] */
#define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK                 0x0003
#define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN                0
#define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS                 2
#define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT                0


/* union - case rxTestSel_1 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:05] */
#define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK                 0xffe0
#define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN                0
#define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS                 11
#define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT                5

/* Rx3 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */
#define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK             0x0010
#define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN            0
#define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS             1
#define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT            4

/* Rx3 :: anaRxStatus :: freq_sel_PC [03:03] */
#define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK               0x0008
#define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN              0
#define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS               1
#define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT              3

/* Rx3 :: anaRxStatus :: freq_sel_SM [02:02] */
#define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK               0x0004
#define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN              0
#define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS               1
#define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT              2

/* Rx3 :: anaRxStatus :: integ_mode_SM [01:00] */
#define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK             0x0003
#define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN            0
#define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS             2
#define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT            0


/* union - case scale_Status [15:00] */
/* Rx3 :: anaRxStatus :: prop_scale [15:12] */
#define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK               0xf000
#define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN              0
#define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS               4
#define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT              12

/* Rx3 :: anaRxStatus :: integ_scale [11:08] */
#define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK              0x0f00
#define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN             0
#define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS              4
#define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT             8

/* Rx3 :: anaRxStatus :: prop_scale_acq [07:04] */
#define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK           0x00f0
#define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN          0
#define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS           4
#define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT          4

/* Rx3 :: anaRxStatus :: integ_scale_acq [03:00] */
#define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK          0x000f
#define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN         0
#define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS          4
#define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT         0


/* union - case adc_CdrStatus1 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:07] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK              0xff80
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN             0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS              9
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT             7

/* Rx3 :: anaRxStatus :: rxMuxCkSel [06:06] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK             0x0040
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN            0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS             1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT            6

/* Rx3 :: anaRxStatus :: glpbk_combo [05:05] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK            0x0020
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN           0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS            1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT           5

/* Rx3 :: anaRxStatus :: clockSwitchSel [04:04] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK         0x0010
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN        0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS         1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT        4

/* Rx3 :: anaRxStatus :: rxck_tst [03:03] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK               0x0008
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN              0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS               1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT              3

/* Rx3 :: anaRxStatus :: rxck_i [02:02] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK                 0x0004
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN                0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS                 1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT                2

/* Rx3 :: anaRxStatus :: refclk [01:01] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK                 0x0002
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN                0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS                 1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT                1

/* Rx3 :: anaRxStatus :: pll_bypass [00:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK             0x0001
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN            0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS             1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT            0


/* union - case adc_CdrStatus2 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:06] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK              0xffc0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN             0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS              10
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT             6

/* Rx3 :: anaRxStatus :: rxMuxCkSel [05:05] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK             0x0020
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN            0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS             1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT            5

/* Rx3 :: anaRxStatus :: rxSeqStart [04:04] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK             0x0010
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN            0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS             1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT            4

/* Rx3 :: anaRxStatus :: reserved1 [03:01] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK              0x000e
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN             0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS              3
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT             1

/* Rx3 :: anaRxStatus :: rxSeqDone [00:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK              0x0001
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN             0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS              1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT             0


/* union - case adc_CdrStatus3 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:04] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK              0xfff0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN             0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS              12
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT             4

/* Rx3 :: anaRxStatus :: rxSeqStart [03:03] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK             0x0008
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN            0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS             1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT            3

/* Rx3 :: anaRxStatus :: reserved1 [02:01] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK              0x0006
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN             0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS              2
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT             1

/* Rx3 :: anaRxStatus :: allow_increment_PC [00:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK     0x0001
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN    0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS     1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT    0


/* union - case adc_CdrStatus4 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:08] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK              0xff00
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN             0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS              8
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT             8

/* Rx3 :: anaRxStatus :: rx_pwrdn [07:07] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK               0x0080
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN              0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS               1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT              7

/* Rx3 :: anaRxStatus :: freq_sel [06:06] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK               0x0040
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN              0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS               1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT              6

/* Rx3 :: anaRxStatus :: pll_lock_rstb [05:05] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK          0x0020
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN         0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS          1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT         5

/* Rx3 :: anaRxStatus :: pwrdn [04:04] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK                  0x0010
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                 0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS                  1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                 4

/* Rx3 :: anaRxStatus :: reserved1 [03:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK              0x000f
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN             0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS              4
#define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT             0


/* union - case adc_CdrStatus5 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK              0xffff
#define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN             0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS              16
#define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT             0


/* union - case adc_CdrStatus6 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:05] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK              0xffe0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN             0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS              11
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT             5

/* Rx3 :: anaRxStatus :: rx_reset [04:04] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK               0x0010
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN              0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS               1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT              4

/* Rx3 :: anaRxStatus :: rx_pwrdn [03:03] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK               0x0008
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN              0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS               1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT              3

/* Rx3 :: anaRxStatus :: reset_anlg [02:02] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK             0x0004
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN            0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS             1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT            2

/* Rx3 :: anaRxStatus :: pwrdn_rx [01:01] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK               0x0002
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN              0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS               1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT              1

/* Rx3 :: anaRxStatus :: pwrdn_pll [00:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK              0x0001
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN             0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS              1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT             0


/* union - case adc_CdrStatus7e [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:05] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK             0xffe0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN            0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS             11
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT            5

/* Rx3 :: anaRxStatus :: rxck0_even [04:04] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK            0x0010
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN           0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS            1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT           4

/* Rx3 :: anaRxStatus :: rxck1_even [03:03] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK            0x0008
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN           0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS            1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT           3

/* Rx3 :: anaRxStatus :: comdet_even [02:02] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK           0x0004
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN          0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS           1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT          2

/* Rx3 :: anaRxStatus :: en_cdet_even [01:01] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK          0x0002
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN         0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS          1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT         1

/* Rx3 :: anaRxStatus :: comma_adj_en_even [00:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK     0x0001
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN    0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS     1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT    0


/* union - case adc_CdrStatus7o [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:05] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK             0xffe0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN            0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS             11
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT            5

/* Rx3 :: anaRxStatus :: rxck0_odd [04:04] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK             0x0010
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN            0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS             1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT            4

/* Rx3 :: anaRxStatus :: rxck1_odd [03:03] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK             0x0008
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN            0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS             1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT            3

/* Rx3 :: anaRxStatus :: comdet_odd [02:02] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK            0x0004
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN           0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS            1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT           2

/* Rx3 :: anaRxStatus :: en_cdet_odd [01:01] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK           0x0002
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN          0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS           1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT          1

/* Rx3 :: anaRxStatus :: comma_adj_en_odd [00:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK      0x0001
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN     0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS      1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT     0


/* union - case adc_CdrStatus8 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:01] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK              0xfffe
#define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN             0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS              15
#define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT             1

/* Rx3 :: anaRxStatus :: sigdet [00:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK                 0x0001
#define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN                0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS                 1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT                0


/* union - case adc_CdrStatus9 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK              0xffff
#define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN             0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS              16
#define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT             0


/* union - case adc_CdrStatus10 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:07] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK             0xff80
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN            0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS             9
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT            7

/* Rx3 :: anaRxStatus :: prbs_en [06:06] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK               0x0040
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN              0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS               1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT              6

/* Rx3 :: anaRxStatus :: rstb_tst [05:05] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK              0x0020
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN             0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS              1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT             5

/* Rx3 :: anaRxStatus :: reserved1 [04:04] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK             0x0010
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN            0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS             1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT            4

/* Rx3 :: anaRxStatus :: prbs_state [03:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK            0x000f
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN           0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS            4
#define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT           0


/* union - case adc_CdrStatus11 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK             0xffff
#define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN            0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS             16
#define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT            0


/* union - case adc_CdrStatus12_1 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:06] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK           0xffc0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN          0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS           10
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT          6

/* Rx3 :: anaRxStatus :: enable4 [05:05] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK             0x0020
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN            0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS             1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT            5

/* Rx3 :: anaRxStatus :: radr_test [04:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK           0x001f
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN          0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS           5
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT          0


/* union - case adc_CdrStatus12_2 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:05] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK           0xffe0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN          0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS           11
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT          5

/* Rx3 :: anaRxStatus :: wadr_test [04:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK           0x001f
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN          0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS           5
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT          0


/* union - case adc_CdrStatus12_3 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:06] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK           0xffc0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN          0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS           10
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT          6

/* Rx3 :: anaRxStatus :: rxck_66B_tmux [05:05] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK       0x0020
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN      0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS       1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT      5

/* Rx3 :: anaRxStatus :: rstb_66B [04:04] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK            0x0010
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN           0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS            1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT           4

/* Rx3 :: anaRxStatus :: prstb_66B_mux [03:03] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK       0x0008
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN      0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS       1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT      3

/* Rx3 :: anaRxStatus :: rxck_i66_tmux [02:02] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK       0x0004
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN      0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS       1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT      2

/* Rx3 :: anaRxStatus :: rstb_i66 [01:01] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK            0x0002
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN           0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS            1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT           1

/* Rx3 :: anaRxStatus :: prstb_i66_mux [00:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK       0x0001
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN      0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS       1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT      0


/* union - case adc_CdrStatus12_4 [15:00] */
/* Rx3 :: anaRxStatus :: reserved0 [15:04] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK           0xfff0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN          0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS           12
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT          4

/* Rx3 :: anaRxStatus :: rfifo_error_r [03:02] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK       0x000c
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN      0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS       2
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT      2

/* Rx3 :: anaRxStatus :: rfifo_unflow [01:01] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK        0x0002
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN       0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS        1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT       1

/* Rx3 :: anaRxStatus :: rfifo_ovflow [00:00] */
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK        0x0001
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN       0
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS        1
#define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT       0


/* union - case integ_Status [15:00] */
/* Rx3 :: anaRxStatus :: integ_status [15:00] */
#define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK             0xffff
#define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN            0
#define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS             16
#define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT            0


/* union - case vco_Status [15:00] */
/* Rx3 :: anaRxStatus :: vco_status [15:00] */
#define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK                 0xffff
#define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN                0
#define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS                 16
#define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT                0


/* union - case prbs_Status [15:00] */
/* Rx3 :: anaRxStatus :: prbs_lock [15:15] */
#define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK                 0x8000
#define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN                0
#define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS                 1
#define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT                15

/* Rx3 :: anaRxStatus :: prbs_stky [14:14] */
#define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK                 0x4000
#define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN                0
#define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS                 1
#define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT                14

/* Rx3 :: anaRxStatus :: ptbs_errors [13:00] */
#define RX3_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK               0x3fff
#define RX3_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN              0
#define RX3_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS               14
#define RX3_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT              0



/****************************************************************************
 * Rx3 :: anaRxControl
 ***************************************************************************/
/* Rx3 :: anaRxControl :: reserved0 [15:10] */
#define RX3_ANARXCONTROL_RESERVED0_MASK                            0xfc00
#define RX3_ANARXCONTROL_RESERVED0_ALIGN                           0
#define RX3_ANARXCONTROL_RESERVED0_BITS                            6
#define RX3_ANARXCONTROL_RESERVED0_SHIFT                           10

/* Rx3 :: anaRxControl :: override_sigdet_en [09:09] */
#define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK                   0x0200
#define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN                  0
#define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS                   1
#define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT                  9

/* Rx3 :: anaRxControl :: override_sigdet_val [08:08] */
#define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK                  0x0100
#define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN                 0
#define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS                  1
#define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT                 8

/* Rx3 :: anaRxControl :: reserved1 [07:03] */
#define RX3_ANARXCONTROL_RESERVED1_MASK                            0x00f8
#define RX3_ANARXCONTROL_RESERVED1_ALIGN                           0
#define RX3_ANARXCONTROL_RESERVED1_BITS                            5
#define RX3_ANARXCONTROL_RESERVED1_SHIFT                           3

/* Rx3 :: anaRxControl :: status_sel [02:00] */
#define RX3_ANARXCONTROL_STATUS_SEL_MASK                           0x0007
#define RX3_ANARXCONTROL_STATUS_SEL_ALIGN                          0
#define RX3_ANARXCONTROL_STATUS_SEL_BITS                           3
#define RX3_ANARXCONTROL_STATUS_SEL_SHIFT                          0
#define RX3_ANARXCONTROL_STATUS_SEL_sigdetStatus                   0
#define RX3_ANARXCONTROL_STATUS_SEL_syncStatus                     1
#define RX3_ANARXCONTROL_STATUS_SEL_rxTestSel                      2
#define RX3_ANARXCONTROL_STATUS_SEL_scaleStatus                    3
#define RX3_ANARXCONTROL_STATUS_SEL_adcCdrStatus                   4
#define RX3_ANARXCONTROL_STATUS_SEL_integStatus                    5
#define RX3_ANARXCONTROL_STATUS_SEL_vcoStatus                      6
#define RX3_ANARXCONTROL_STATUS_SEL_prbsStatus                     7


/****************************************************************************
 * Rx3 :: anaRxTest
 ***************************************************************************/
/* Rx3 :: anaRxTest :: sigdet_mux_SM [15:12] */
#define RX3_ANARXTEST_SIGDET_MUX_SM_MASK                           0xf000
#define RX3_ANARXTEST_SIGDET_MUX_SM_ALIGN                          0
#define RX3_ANARXTEST_SIGDET_MUX_SM_BITS                           4
#define RX3_ANARXTEST_SIGDET_MUX_SM_SHIFT                          12

/* Rx3 :: anaRxTest :: reserved0 [11:09] */
#define RX3_ANARXTEST_RESERVED0_MASK                               0x0e00
#define RX3_ANARXTEST_RESERVED0_ALIGN                              0
#define RX3_ANARXTEST_RESERVED0_BITS                               3
#define RX3_ANARXTEST_RESERVED0_SHIFT                              9

/* Rx3 :: anaRxTest :: tpctrl_SM [08:04] */
#define RX3_ANARXTEST_TPCTRL_SM_MASK                               0x01f0
#define RX3_ANARXTEST_TPCTRL_SM_ALIGN                              0
#define RX3_ANARXTEST_TPCTRL_SM_BITS                               5
#define RX3_ANARXTEST_TPCTRL_SM_SHIFT                              4

/* Rx3 :: anaRxTest :: testMuxSelect_SM [03:00] */
#define RX3_ANARXTEST_TESTMUXSELECT_SM_MASK                        0x000f
#define RX3_ANARXTEST_TESTMUXSELECT_SM_ALIGN                       0
#define RX3_ANARXTEST_TESTMUXSELECT_SM_BITS                        4
#define RX3_ANARXTEST_TESTMUXSELECT_SM_SHIFT                       0


/****************************************************************************
 * Rx3 :: anaRxControl1G
 ***************************************************************************/
/* Rx3 :: anaRxControl1G :: fpat_md [15:15] */
#define RX3_ANARXCONTROL1G_FPAT_MD_MASK                            0x8000
#define RX3_ANARXCONTROL1G_FPAT_MD_ALIGN                           0
#define RX3_ANARXCONTROL1G_FPAT_MD_BITS                            1
#define RX3_ANARXCONTROL1G_FPAT_MD_SHIFT                           15

/* Rx3 :: anaRxControl1G :: pkt_count_en [14:14] */
#define RX3_ANARXCONTROL1G_PKT_COUNT_EN_MASK                       0x4000
#define RX3_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN                      0
#define RX3_ANARXCONTROL1G_PKT_COUNT_EN_BITS                       1
#define RX3_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT                      14

/* Rx3 :: anaRxControl1G :: staMuxRegDis [13:13] */
#define RX3_ANARXCONTROL1G_STAMUXREGDIS_MASK                       0x2000
#define RX3_ANARXCONTROL1G_STAMUXREGDIS_ALIGN                      0
#define RX3_ANARXCONTROL1G_STAMUXREGDIS_BITS                       1
#define RX3_ANARXCONTROL1G_STAMUXREGDIS_SHIFT                      13

/* Rx3 :: anaRxControl1G :: prbs_clr_dis [12:12] */
#define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_MASK                       0x1000
#define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN                      0
#define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_BITS                       1
#define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT                      12

/* Rx3 :: anaRxControl1G :: rxd_dec_sel [11:11] */
#define RX3_ANARXCONTROL1G_RXD_DEC_SEL_MASK                        0x0800
#define RX3_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN                       0
#define RX3_ANARXCONTROL1G_RXD_DEC_SEL_BITS                        1
#define RX3_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT                       11

/* Rx3 :: anaRxControl1G :: cgbad_tst [10:10] */
#define RX3_ANARXCONTROL1G_CGBAD_TST_MASK                          0x0400
#define RX3_ANARXCONTROL1G_CGBAD_TST_ALIGN                         0
#define RX3_ANARXCONTROL1G_CGBAD_TST_BITS                          1
#define RX3_ANARXCONTROL1G_CGBAD_TST_SHIFT                         10

/* Rx3 :: anaRxControl1G :: Emon_en [09:09] */
#define RX3_ANARXCONTROL1G_EMON_EN_MASK                            0x0200
#define RX3_ANARXCONTROL1G_EMON_EN_ALIGN                           0
#define RX3_ANARXCONTROL1G_EMON_EN_BITS                            1
#define RX3_ANARXCONTROL1G_EMON_EN_SHIFT                           9

/* Rx3 :: anaRxControl1G :: prbs_en [08:08] */
#define RX3_ANARXCONTROL1G_PRBS_EN_MASK                            0x0100
#define RX3_ANARXCONTROL1G_PRBS_EN_ALIGN                           0
#define RX3_ANARXCONTROL1G_PRBS_EN_BITS                            1
#define RX3_ANARXCONTROL1G_PRBS_EN_SHIFT                           8

/* Rx3 :: anaRxControl1G :: cgbad_en [07:07] */
#define RX3_ANARXCONTROL1G_CGBAD_EN_MASK                           0x0080
#define RX3_ANARXCONTROL1G_CGBAD_EN_ALIGN                          0
#define RX3_ANARXCONTROL1G_CGBAD_EN_BITS                           1
#define RX3_ANARXCONTROL1G_CGBAD_EN_SHIFT                          7

/* Rx3 :: anaRxControl1G :: cstretch [06:06] */
#define RX3_ANARXCONTROL1G_CSTRETCH_MASK                           0x0040
#define RX3_ANARXCONTROL1G_CSTRETCH_ALIGN                          0
#define RX3_ANARXCONTROL1G_CSTRETCH_BITS                           1
#define RX3_ANARXCONTROL1G_CSTRETCH_SHIFT                          6

/* Rx3 :: anaRxControl1G :: comma_low_byte_SM [05:05] */
#define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK                  0x0020
#define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN                 0
#define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS                  1
#define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT                 5

/* Rx3 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */
#define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK               0x0010
#define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN              0
#define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS               1
#define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT              4

/* Rx3 :: anaRxControl1G :: reserved0 [03:02] */
#define RX3_ANARXCONTROL1G_RESERVED0_MASK                          0x000c
#define RX3_ANARXCONTROL1G_RESERVED0_ALIGN                         0
#define RX3_ANARXCONTROL1G_RESERVED0_BITS                          2
#define RX3_ANARXCONTROL1G_RESERVED0_SHIFT                         2

/* Rx3 :: anaRxControl1G :: freq_sel_force [01:01] */
#define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK                     0x0002
#define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN                    0
#define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS                     1
#define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT                    1

/* Rx3 :: anaRxControl1G :: freq_sel [00:00] */
#define RX3_ANARXCONTROL1G_FREQ_SEL_MASK                           0x0001
#define RX3_ANARXCONTROL1G_FREQ_SEL_ALIGN                          0
#define RX3_ANARXCONTROL1G_FREQ_SEL_BITS                           1
#define RX3_ANARXCONTROL1G_FREQ_SEL_SHIFT                          0


/****************************************************************************
 * Rx3 :: anaRxControlPci
 ***************************************************************************/
/* Rx3 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK                0x8000
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN               0
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS                1
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT               15

/* Rx3 :: anaRxControlPci :: comma_mask_force_r [14:14] */
#define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK                0x4000
#define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN               0
#define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS                1
#define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT               14

/* Rx3 :: anaRxControlPci :: comma_mask_r [13:13] */
#define RX3_ANARXCONTROLPCI_COMMA_MASK_R_MASK                      0x2000
#define RX3_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN                     0
#define RX3_ANARXCONTROLPCI_COMMA_MASK_R_BITS                      1
#define RX3_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT                     13

/* Rx3 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */
#define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK         0x1000
#define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN        0
#define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS         1
#define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT        12

/* Rx3 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */
#define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK            0x0800
#define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN           0
#define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS            1
#define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT           11

/* Rx3 :: anaRxControlPci :: sync_status_force_r [10:10] */
#define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK               0x0400
#define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN              0
#define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS               1
#define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT              10

/* Rx3 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK         0x0200
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN        0
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS         1
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT        9

/* Rx3 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK        0x0100
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN       0
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS        1
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT       8

/* Rx3 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK           0x0080
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN          0
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS           1
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT          7

/* Rx3 :: anaRxControlPci :: comma_adj_en_r [06:06] */
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK                    0x0040
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN                   0
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS                    1
#define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT                   6

/* Rx3 :: anaRxControlPci :: link_en_force_SM [05:05] */
#define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK                  0x0020
#define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN                 0
#define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS                  1
#define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT                 5

/* Rx3 :: anaRxControlPci :: link_en_r [04:04] */
#define RX3_ANARXCONTROLPCI_LINK_EN_R_MASK                         0x0010
#define RX3_ANARXCONTROLPCI_LINK_EN_R_ALIGN                        0
#define RX3_ANARXCONTROLPCI_LINK_EN_R_BITS                         1
#define RX3_ANARXCONTROLPCI_LINK_EN_R_SHIFT                        4

/* Rx3 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */
#define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK              0x0008
#define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN             0
#define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS              1
#define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT             3

/* Rx3 :: anaRxControlPci :: rx_polarity_r [02:02] */
#define RX3_ANARXCONTROLPCI_RX_POLARITY_R_MASK                     0x0004
#define RX3_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN                    0
#define RX3_ANARXCONTROLPCI_RX_POLARITY_R_BITS                     1
#define RX3_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT                    2

/* Rx3 :: anaRxControlPci :: integ_mode_SM [01:00] */
#define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_MASK                     0x0003
#define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN                    0
#define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_BITS                     2
#define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT                    0


/****************************************************************************
 * Rx3 :: anaRxAstatus
 ***************************************************************************/
/* Rx3 :: anaRxAstatus :: sigdet [15:15] */
#define RX3_ANARXASTATUS_SIGDET_MASK                               0x8000
#define RX3_ANARXASTATUS_SIGDET_ALIGN                              0
#define RX3_ANARXASTATUS_SIGDET_BITS                               1
#define RX3_ANARXASTATUS_SIGDET_SHIFT                              15

/* Rx3 :: anaRxAstatus :: rx_pf [14:12] */
#define RX3_ANARXASTATUS_RX_PF_MASK                                0x7000
#define RX3_ANARXASTATUS_RX_PF_ALIGN                               0
#define RX3_ANARXASTATUS_RX_PF_BITS                                3
#define RX3_ANARXASTATUS_RX_PF_SHIFT                               12

/* Rx3 :: anaRxAstatus :: dfe [11:06] */
#define RX3_ANARXASTATUS_DFE_MASK                                  0x0fc0
#define RX3_ANARXASTATUS_DFE_ALIGN                                 0
#define RX3_ANARXASTATUS_DFE_BITS                                  6
#define RX3_ANARXASTATUS_DFE_SHIFT                                 6

/* Rx3 :: anaRxAstatus :: reserved0 [05:05] */
#define RX3_ANARXASTATUS_RESERVED0_MASK                            0x0020
#define RX3_ANARXASTATUS_RESERVED0_ALIGN                           0
#define RX3_ANARXASTATUS_RESERVED0_BITS                            1
#define RX3_ANARXASTATUS_RESERVED0_SHIFT                           5

/* Rx3 :: anaRxAstatus :: vga [04:00] */
#define RX3_ANARXASTATUS_VGA_MASK                                  0x001f
#define RX3_ANARXASTATUS_VGA_ALIGN                                 0
#define RX3_ANARXASTATUS_VGA_BITS                                  5
#define RX3_ANARXASTATUS_VGA_SHIFT                                 0


/****************************************************************************
 * Rx3 :: anaRxAControl1
 ***************************************************************************/
/* Rx3 :: anaRxAControl1 :: imode_vcm [15:15] */
#define RX3_ANARXACONTROL1_IMODE_VCM_MASK                          0x8000
#define RX3_ANARXACONTROL1_IMODE_VCM_ALIGN                         0
#define RX3_ANARXACONTROL1_IMODE_VCM_BITS                          1
#define RX3_ANARXACONTROL1_IMODE_VCM_SHIFT                         15

/* Rx3 :: anaRxAControl1 :: imin_vcm [14:14] */
#define RX3_ANARXACONTROL1_IMIN_VCM_MASK                           0x4000
#define RX3_ANARXACONTROL1_IMIN_VCM_ALIGN                          0
#define RX3_ANARXACONTROL1_IMIN_VCM_BITS                           1
#define RX3_ANARXACONTROL1_IMIN_VCM_SHIFT                          14

/* Rx3 :: anaRxAControl1 :: imax_sigdet [13:13] */
#define RX3_ANARXACONTROL1_IMAX_SIGDET_MASK                        0x2000
#define RX3_ANARXACONTROL1_IMAX_SIGDET_ALIGN                       0
#define RX3_ANARXACONTROL1_IMAX_SIGDET_BITS                        1
#define RX3_ANARXACONTROL1_IMAX_SIGDET_SHIFT                       13

/* Rx3 :: anaRxAControl1 :: imode_sigdet [12:12] */
#define RX3_ANARXACONTROL1_IMODE_SIGDET_MASK                       0x1000
#define RX3_ANARXACONTROL1_IMODE_SIGDET_ALIGN                      0
#define RX3_ANARXACONTROL1_IMODE_SIGDET_BITS                       1
#define RX3_ANARXACONTROL1_IMODE_SIGDET_SHIFT                      12

/* Rx3 :: anaRxAControl1 :: imin_sigdet [11:11] */
#define RX3_ANARXACONTROL1_IMIN_SIGDET_MASK                        0x0800
#define RX3_ANARXACONTROL1_IMIN_SIGDET_ALIGN                       0
#define RX3_ANARXACONTROL1_IMIN_SIGDET_BITS                        1
#define RX3_ANARXACONTROL1_IMIN_SIGDET_SHIFT                       11

/* Rx3 :: anaRxAControl1 :: refh_rx [10:10] */
#define RX3_ANARXACONTROL1_REFH_RX_MASK                            0x0400
#define RX3_ANARXACONTROL1_REFH_RX_ALIGN                           0
#define RX3_ANARXACONTROL1_REFH_RX_BITS                            1
#define RX3_ANARXACONTROL1_REFH_RX_SHIFT                           10

/* Rx3 :: anaRxAControl1 :: refl_rx [09:09] */
#define RX3_ANARXACONTROL1_REFL_RX_MASK                            0x0200
#define RX3_ANARXACONTROL1_REFL_RX_ALIGN                           0
#define RX3_ANARXACONTROL1_REFL_RX_BITS                            1
#define RX3_ANARXACONTROL1_REFL_RX_SHIFT                           9

/* Rx3 :: anaRxAControl1 :: tport_en [08:08] */
#define RX3_ANARXACONTROL1_TPORT_EN_MASK                           0x0100
#define RX3_ANARXACONTROL1_TPORT_EN_ALIGN                          0
#define RX3_ANARXACONTROL1_TPORT_EN_BITS                           1
#define RX3_ANARXACONTROL1_TPORT_EN_SHIFT                          8

/* Rx3 :: anaRxAControl1 :: vddrb_bg [07:07] */
#define RX3_ANARXACONTROL1_VDDRB_BG_MASK                           0x0080
#define RX3_ANARXACONTROL1_VDDRB_BG_ALIGN                          0
#define RX3_ANARXACONTROL1_VDDRB_BG_BITS                           1
#define RX3_ANARXACONTROL1_VDDRB_BG_SHIFT                          7

/* Rx3 :: anaRxAControl1 :: sig_pwrdn [06:06] */
#define RX3_ANARXACONTROL1_SIG_PWRDN_MASK                          0x0040
#define RX3_ANARXACONTROL1_SIG_PWRDN_ALIGN                         0
#define RX3_ANARXACONTROL1_SIG_PWRDN_BITS                          1
#define RX3_ANARXACONTROL1_SIG_PWRDN_SHIFT                         6

/* Rx3 :: anaRxAControl1 :: offset_ctrl [05:03] */
#define RX3_ANARXACONTROL1_OFFSET_CTRL_MASK                        0x0038
#define RX3_ANARXACONTROL1_OFFSET_CTRL_ALIGN                       0
#define RX3_ANARXACONTROL1_OFFSET_CTRL_BITS                        3
#define RX3_ANARXACONTROL1_OFFSET_CTRL_SHIFT                       3

/* Rx3 :: anaRxAControl1 :: offset_sel [02:02] */
#define RX3_ANARXACONTROL1_OFFSET_SEL_MASK                         0x0004
#define RX3_ANARXACONTROL1_OFFSET_SEL_ALIGN                        0
#define RX3_ANARXACONTROL1_OFFSET_SEL_BITS                         1
#define RX3_ANARXACONTROL1_OFFSET_SEL_SHIFT                        2

/* Rx3 :: anaRxAControl1 :: reserved0 [01:00] */
#define RX3_ANARXACONTROL1_RESERVED0_MASK                          0x0003
#define RX3_ANARXACONTROL1_RESERVED0_ALIGN                         0
#define RX3_ANARXACONTROL1_RESERVED0_BITS                          2
#define RX3_ANARXACONTROL1_RESERVED0_SHIFT                         0


/****************************************************************************
 * Rx3 :: anaRxAControl2
 ***************************************************************************/
/* Rx3 :: anaRxAControl2 :: imax_clkbuf [15:15] */
#define RX3_ANARXACONTROL2_IMAX_CLKBUF_MASK                        0x8000
#define RX3_ANARXACONTROL2_IMAX_CLKBUF_ALIGN                       0
#define RX3_ANARXACONTROL2_IMAX_CLKBUF_BITS                        1
#define RX3_ANARXACONTROL2_IMAX_CLKBUF_SHIFT                       15

/* Rx3 :: anaRxAControl2 :: imode_clkbuf [14:14] */
#define RX3_ANARXACONTROL2_IMODE_CLKBUF_MASK                       0x4000
#define RX3_ANARXACONTROL2_IMODE_CLKBUF_ALIGN                      0
#define RX3_ANARXACONTROL2_IMODE_CLKBUF_BITS                       1
#define RX3_ANARXACONTROL2_IMODE_CLKBUF_SHIFT                      14

/* Rx3 :: anaRxAControl2 :: imin_clkbuf [13:13] */
#define RX3_ANARXACONTROL2_IMIN_CLKBUF_MASK                        0x2000
#define RX3_ANARXACONTROL2_IMIN_CLKBUF_ALIGN                       0
#define RX3_ANARXACONTROL2_IMIN_CLKBUF_BITS                        1
#define RX3_ANARXACONTROL2_IMIN_CLKBUF_SHIFT                       13

/* Rx3 :: anaRxAControl2 :: imax_eqfl [12:12] */
#define RX3_ANARXACONTROL2_IMAX_EQFL_MASK                          0x1000
#define RX3_ANARXACONTROL2_IMAX_EQFL_ALIGN                         0
#define RX3_ANARXACONTROL2_IMAX_EQFL_BITS                          1
#define RX3_ANARXACONTROL2_IMAX_EQFL_SHIFT                         12

/* Rx3 :: anaRxAControl2 :: imode_eqfl [11:11] */
#define RX3_ANARXACONTROL2_IMODE_EQFL_MASK                         0x0800
#define RX3_ANARXACONTROL2_IMODE_EQFL_ALIGN                        0
#define RX3_ANARXACONTROL2_IMODE_EQFL_BITS                         1
#define RX3_ANARXACONTROL2_IMODE_EQFL_SHIFT                        11

/* Rx3 :: anaRxAControl2 :: imin_eqfl [10:10] */
#define RX3_ANARXACONTROL2_IMIN_EQFL_MASK                          0x0400
#define RX3_ANARXACONTROL2_IMIN_EQFL_ALIGN                         0
#define RX3_ANARXACONTROL2_IMIN_EQFL_BITS                          1
#define RX3_ANARXACONTROL2_IMIN_EQFL_SHIFT                         10

/* Rx3 :: anaRxAControl2 :: imax_dfesum [09:09] */
#define RX3_ANARXACONTROL2_IMAX_DFESUM_MASK                        0x0200
#define RX3_ANARXACONTROL2_IMAX_DFESUM_ALIGN                       0
#define RX3_ANARXACONTROL2_IMAX_DFESUM_BITS                        1
#define RX3_ANARXACONTROL2_IMAX_DFESUM_SHIFT                       9

/* Rx3 :: anaRxAControl2 :: imode_dfesum [08:08] */
#define RX3_ANARXACONTROL2_IMODE_DFESUM_MASK                       0x0100
#define RX3_ANARXACONTROL2_IMODE_DFESUM_ALIGN                      0
#define RX3_ANARXACONTROL2_IMODE_DFESUM_BITS                       1
#define RX3_ANARXACONTROL2_IMODE_DFESUM_SHIFT                      8

/* Rx3 :: anaRxAControl2 :: imin_dfesum [07:07] */
#define RX3_ANARXACONTROL2_IMIN_DFESUM_MASK                        0x0080
#define RX3_ANARXACONTROL2_IMIN_DFESUM_ALIGN                       0
#define RX3_ANARXACONTROL2_IMIN_DFESUM_BITS                        1
#define RX3_ANARXACONTROL2_IMIN_DFESUM_SHIFT                       7

/* Rx3 :: anaRxAControl2 :: imax_vga [06:06] */
#define RX3_ANARXACONTROL2_IMAX_VGA_MASK                           0x0040
#define RX3_ANARXACONTROL2_IMAX_VGA_ALIGN                          0
#define RX3_ANARXACONTROL2_IMAX_VGA_BITS                           1
#define RX3_ANARXACONTROL2_IMAX_VGA_SHIFT                          6

/* Rx3 :: anaRxAControl2 :: imode_vga [05:05] */
#define RX3_ANARXACONTROL2_IMODE_VGA_MASK                          0x0020
#define RX3_ANARXACONTROL2_IMODE_VGA_ALIGN                         0
#define RX3_ANARXACONTROL2_IMODE_VGA_BITS                          1
#define RX3_ANARXACONTROL2_IMODE_VGA_SHIFT                         5

/* Rx3 :: anaRxAControl2 :: imin_vga [04:04] */
#define RX3_ANARXACONTROL2_IMIN_VGA_MASK                           0x0010
#define RX3_ANARXACONTROL2_IMIN_VGA_ALIGN                          0
#define RX3_ANARXACONTROL2_IMIN_VGA_BITS                           1
#define RX3_ANARXACONTROL2_IMIN_VGA_SHIFT                          4

/* Rx3 :: anaRxAControl2 :: imax_interp [03:03] */
#define RX3_ANARXACONTROL2_IMAX_INTERP_MASK                        0x0008
#define RX3_ANARXACONTROL2_IMAX_INTERP_ALIGN                       0
#define RX3_ANARXACONTROL2_IMAX_INTERP_BITS                        1
#define RX3_ANARXACONTROL2_IMAX_INTERP_SHIFT                       3

/* Rx3 :: anaRxAControl2 :: imode_interp [02:02] */
#define RX3_ANARXACONTROL2_IMODE_INTERP_MASK                       0x0004
#define RX3_ANARXACONTROL2_IMODE_INTERP_ALIGN                      0
#define RX3_ANARXACONTROL2_IMODE_INTERP_BITS                       1
#define RX3_ANARXACONTROL2_IMODE_INTERP_SHIFT                      2

/* Rx3 :: anaRxAControl2 :: imin_interp [01:01] */
#define RX3_ANARXACONTROL2_IMIN_INTERP_MASK                        0x0002
#define RX3_ANARXACONTROL2_IMIN_INTERP_ALIGN                       0
#define RX3_ANARXACONTROL2_IMIN_INTERP_BITS                        1
#define RX3_ANARXACONTROL2_IMIN_INTERP_SHIFT                       1

/* Rx3 :: anaRxAControl2 :: imax_vcm [00:00] */
#define RX3_ANARXACONTROL2_IMAX_VCM_MASK                           0x0001
#define RX3_ANARXACONTROL2_IMAX_VCM_ALIGN                          0
#define RX3_ANARXACONTROL2_IMAX_VCM_BITS                           1
#define RX3_ANARXACONTROL2_IMAX_VCM_SHIFT                          0


/****************************************************************************
 * Rx3 :: anaRxAControl3
 ***************************************************************************/
/* Rx3 :: anaRxAControl3 :: en_clk16 [15:15] */
#define RX3_ANARXACONTROL3_EN_CLK16_MASK                           0x8000
#define RX3_ANARXACONTROL3_EN_CLK16_ALIGN                          0
#define RX3_ANARXACONTROL3_EN_CLK16_BITS                           1
#define RX3_ANARXACONTROL3_EN_CLK16_SHIFT                          15

/* Rx3 :: anaRxAControl3 :: pd_ch_p1 [14:14] */
#define RX3_ANARXACONTROL3_PD_CH_P1_MASK                           0x4000
#define RX3_ANARXACONTROL3_PD_CH_P1_ALIGN                          0
#define RX3_ANARXACONTROL3_PD_CH_P1_BITS                           1
#define RX3_ANARXACONTROL3_PD_CH_P1_SHIFT                          14

/* Rx3 :: anaRxAControl3 :: en_vcctrl [13:13] */
#define RX3_ANARXACONTROL3_EN_VCCTRL_MASK                          0x2000
#define RX3_ANARXACONTROL3_EN_VCCTRL_ALIGN                         0
#define RX3_ANARXACONTROL3_EN_VCCTRL_BITS                          1
#define RX3_ANARXACONTROL3_EN_VCCTRL_SHIFT                         13

/* Rx3 :: anaRxAControl3 :: en_dfeclk [12:12] */
#define RX3_ANARXACONTROL3_EN_DFECLK_MASK                          0x1000
#define RX3_ANARXACONTROL3_EN_DFECLK_ALIGN                         0
#define RX3_ANARXACONTROL3_EN_DFECLK_BITS                          1
#define RX3_ANARXACONTROL3_EN_DFECLK_SHIFT                         12

/* Rx3 :: anaRxAControl3 :: en_hgain [11:11] */
#define RX3_ANARXACONTROL3_EN_HGAIN_MASK                           0x0800
#define RX3_ANARXACONTROL3_EN_HGAIN_ALIGN                          0
#define RX3_ANARXACONTROL3_EN_HGAIN_BITS                           1
#define RX3_ANARXACONTROL3_EN_HGAIN_SHIFT                          11

/* Rx3 :: anaRxAControl3 :: en_dfeckpwr [10:10] */
#define RX3_ANARXACONTROL3_EN_DFECKPWR_MASK                        0x0400
#define RX3_ANARXACONTROL3_EN_DFECKPWR_ALIGN                       0
#define RX3_ANARXACONTROL3_EN_DFECKPWR_BITS                        1
#define RX3_ANARXACONTROL3_EN_DFECKPWR_SHIFT                       10

/* Rx3 :: anaRxAControl3 :: offset_pd [09:09] */
#define RX3_ANARXACONTROL3_OFFSET_PD_MASK                          0x0200
#define RX3_ANARXACONTROL3_OFFSET_PD_ALIGN                         0
#define RX3_ANARXACONTROL3_OFFSET_PD_BITS                          1
#define RX3_ANARXACONTROL3_OFFSET_PD_SHIFT                         9

/* Rx3 :: anaRxAControl3 :: imax_dfetap [08:08] */
#define RX3_ANARXACONTROL3_IMAX_DFETAP_MASK                        0x0100
#define RX3_ANARXACONTROL3_IMAX_DFETAP_ALIGN                       0
#define RX3_ANARXACONTROL3_IMAX_DFETAP_BITS                        1
#define RX3_ANARXACONTROL3_IMAX_DFETAP_SHIFT                       8

/* Rx3 :: anaRxAControl3 :: imode_dfetap [07:07] */
#define RX3_ANARXACONTROL3_IMODE_DFETAP_MASK                       0x0080
#define RX3_ANARXACONTROL3_IMODE_DFETAP_ALIGN                      0
#define RX3_ANARXACONTROL3_IMODE_DFETAP_BITS                       1
#define RX3_ANARXACONTROL3_IMODE_DFETAP_SHIFT                      7

/* Rx3 :: anaRxAControl3 :: imin_dfetap [06:06] */
#define RX3_ANARXACONTROL3_IMIN_DFETAP_MASK                        0x0040
#define RX3_ANARXACONTROL3_IMIN_DFETAP_ALIGN                       0
#define RX3_ANARXACONTROL3_IMIN_DFETAP_BITS                        1
#define RX3_ANARXACONTROL3_IMIN_DFETAP_SHIFT                       6

/* Rx3 :: anaRxAControl3 :: imax_slcd2c [05:05] */
#define RX3_ANARXACONTROL3_IMAX_SLCD2C_MASK                        0x0020
#define RX3_ANARXACONTROL3_IMAX_SLCD2C_ALIGN                       0
#define RX3_ANARXACONTROL3_IMAX_SLCD2C_BITS                        1
#define RX3_ANARXACONTROL3_IMAX_SLCD2C_SHIFT                       5

/* Rx3 :: anaRxAControl3 :: imode_slcd2c [04:04] */
#define RX3_ANARXACONTROL3_IMODE_SLCD2C_MASK                       0x0010
#define RX3_ANARXACONTROL3_IMODE_SLCD2C_ALIGN                      0
#define RX3_ANARXACONTROL3_IMODE_SLCD2C_BITS                       1
#define RX3_ANARXACONTROL3_IMODE_SLCD2C_SHIFT                      4

/* Rx3 :: anaRxAControl3 :: imin_slcd2c [03:03] */
#define RX3_ANARXACONTROL3_IMIN_SLCD2C_MASK                        0x0008
#define RX3_ANARXACONTROL3_IMIN_SLCD2C_ALIGN                       0
#define RX3_ANARXACONTROL3_IMIN_SLCD2C_BITS                        1
#define RX3_ANARXACONTROL3_IMIN_SLCD2C_SHIFT                       3

/* Rx3 :: anaRxAControl3 :: imax_dfevref [02:02] */
#define RX3_ANARXACONTROL3_IMAX_DFEVREF_MASK                       0x0004
#define RX3_ANARXACONTROL3_IMAX_DFEVREF_ALIGN                      0
#define RX3_ANARXACONTROL3_IMAX_DFEVREF_BITS                       1
#define RX3_ANARXACONTROL3_IMAX_DFEVREF_SHIFT                      2

/* Rx3 :: anaRxAControl3 :: imode_dfevref [01:01] */
#define RX3_ANARXACONTROL3_IMODE_DFEVREF_MASK                      0x0002
#define RX3_ANARXACONTROL3_IMODE_DFEVREF_ALIGN                     0
#define RX3_ANARXACONTROL3_IMODE_DFEVREF_BITS                      1
#define RX3_ANARXACONTROL3_IMODE_DFEVREF_SHIFT                     1

/* Rx3 :: anaRxAControl3 :: imin_dfevref [00:00] */
#define RX3_ANARXACONTROL3_IMIN_DFEVREF_MASK                       0x0001
#define RX3_ANARXACONTROL3_IMIN_DFEVREF_ALIGN                      0
#define RX3_ANARXACONTROL3_IMIN_DFEVREF_BITS                       1
#define RX3_ANARXACONTROL3_IMIN_DFEVREF_SHIFT                      0


/****************************************************************************
 * Hypercore_USER_RxB
 ***************************************************************************/
/****************************************************************************
 * RxB :: anaRxStatus
 ***************************************************************************/
/* union - case sigdet_Status [15:00] */
/* RxB :: anaRxStatus :: cx4_sigdet [15:15] */
#define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK              0x8000
#define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN             0
#define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS              1
#define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT             15

/* RxB :: anaRxStatus :: reserved0 [14:13] */
#define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK               0x6000
#define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN              0
#define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS               2
#define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT              13

/* RxB :: anaRxStatus :: rxSeqDone [12:12] */
#define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK               0x1000
#define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN              0
#define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS               1
#define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT              12

/* RxB :: anaRxStatus :: rx_sigdet_ll [11:11] */
#define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK            0x0800
#define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN           0
#define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS            1
#define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT           11

/* RxB :: anaRxStatus :: cs4_sigdet_ll [10:10] */
#define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK           0x0400
#define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN          0
#define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS           1
#define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT          10

/* RxB :: anaRxStatus :: rx_reset [09:09] */
#define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK                0x0200
#define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN               0
#define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS                1
#define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT               9

/* RxB :: anaRxStatus :: rx_pwrdn [08:08] */
#define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK                0x0100
#define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN               0
#define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS                1
#define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT               8

/* RxB :: anaRxStatus :: reserved1 [07:00] */
#define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK               0x00ff
#define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN              0
#define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS               8
#define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT              0


/* union - case sync_Status [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:11] */
#define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK                 0xf800
#define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN                0
#define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS                 5
#define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT                11

/* RxB :: anaRxStatus :: test_acq_en [10:10] */
#define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK               0x0400
#define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN              0
#define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS               1
#define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT              10

/* RxB :: anaRxStatus :: reserved1 [09:09] */
#define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK                 0x0200
#define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN                0
#define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS                 1
#define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT                9

/* RxB :: anaRxStatus :: rxSeqStart [08:08] */
#define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK                0x0100
#define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN               0
#define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS                1
#define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT               8

/* RxB :: anaRxStatus :: mux_comadj_sync_status [07:07] */
#define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK    0x0080
#define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN   0
#define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS    1
#define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT   7

/* RxB :: anaRxStatus :: sync_status [06:06] */
#define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK               0x0040
#define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN              0
#define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS               1
#define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT              6

/* RxB :: anaRxStatus :: rx_sigdet [05:05] */
#define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK                 0x0020
#define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN                0
#define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS                 1
#define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT                5

/* RxB :: anaRxStatus :: reserved2 [04:03] */
#define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK                 0x0018
#define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN                0
#define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS                 2
#define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT                3

/* RxB :: anaRxStatus :: saturate_status [02:02] */
#define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK           0x0004
#define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN          0
#define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS           1
#define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT          2

/* RxB :: anaRxStatus :: cx4_sigdet [01:01] */
#define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK                0x0002
#define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN               0
#define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS                1
#define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT               1

/* RxB :: anaRxStatus :: rxSeqDone [00:00] */
#define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK                 0x0001
#define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN                0
#define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS                 1
#define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT                0


/* union - case rxTestSel_0 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:10] */
#define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK                 0xfc00
#define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN                0
#define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS                 6
#define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT                10

/* RxB :: anaRxStatus :: indck_mode_en [09:09] */
#define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK             0x0200
#define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN            0
#define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS             1
#define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT            9

/* RxB :: anaRxStatus :: pci_mode_en [08:08] */
#define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK               0x0100
#define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN              0
#define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS               1
#define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT              8

/* RxB :: anaRxStatus :: rx_polarity [07:07] */
#define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK               0x0080
#define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN              0
#define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS               1
#define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT              7

/* RxB :: anaRxStatus :: rxpol_flip [06:06] */
#define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK                0x0040
#define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN               0
#define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS                1
#define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT               6

/* RxB :: anaRxStatus :: comma_mask [05:05] */
#define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK                0x0020
#define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN               0
#define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS                1
#define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT               5

/* RxB :: anaRxStatus :: link_en_r [04:04] */
#define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK                 0x0010
#define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN                0
#define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS                 1
#define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT                4

/* RxB :: anaRxStatus :: comma_adj_en [03:03] */
#define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK              0x0008
#define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN             0
#define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS              1
#define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT             3

/* RxB :: anaRxStatus :: comma_adj_en_ext [02:02] */
#define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK          0x0004
#define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN         0
#define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS          1
#define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT         2

/* RxB :: anaRxStatus :: reserved1 [01:00] */
#define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK                 0x0003
#define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN                0
#define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS                 2
#define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT                0


/* union - case rxTestSel_1 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:05] */
#define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK                 0xffe0
#define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN                0
#define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS                 11
#define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT                5

/* RxB :: anaRxStatus :: cdrAcqDone_r2 [04:04] */
#define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK             0x0010
#define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN            0
#define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS             1
#define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT            4

/* RxB :: anaRxStatus :: freq_sel_PC [03:03] */
#define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK               0x0008
#define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN              0
#define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS               1
#define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT              3

/* RxB :: anaRxStatus :: freq_sel_SM [02:02] */
#define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK               0x0004
#define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN              0
#define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS               1
#define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT              2

/* RxB :: anaRxStatus :: integ_mode_SM [01:00] */
#define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK             0x0003
#define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN            0
#define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS             2
#define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT            0


/* union - case scale_Status [15:00] */
/* RxB :: anaRxStatus :: prop_scale [15:12] */
#define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK               0xf000
#define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN              0
#define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS               4
#define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT              12

/* RxB :: anaRxStatus :: integ_scale [11:08] */
#define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK              0x0f00
#define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN             0
#define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS              4
#define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT             8

/* RxB :: anaRxStatus :: prop_scale_acq [07:04] */
#define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK           0x00f0
#define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN          0
#define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS           4
#define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT          4

/* RxB :: anaRxStatus :: integ_scale_acq [03:00] */
#define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK          0x000f
#define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN         0
#define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS          4
#define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT         0


/* union - case adc_CdrStatus1 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:07] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK              0xff80
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN             0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS              9
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT             7

/* RxB :: anaRxStatus :: rxMuxCkSel [06:06] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK             0x0040
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN            0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS             1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT            6

/* RxB :: anaRxStatus :: glpbk_combo [05:05] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK            0x0020
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN           0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS            1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT           5

/* RxB :: anaRxStatus :: clockSwitchSel [04:04] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK         0x0010
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN        0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS         1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT        4

/* RxB :: anaRxStatus :: rxck_tst [03:03] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK               0x0008
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN              0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS               1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT              3

/* RxB :: anaRxStatus :: rxck_i [02:02] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK                 0x0004
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN                0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS                 1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT                2

/* RxB :: anaRxStatus :: refclk [01:01] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK                 0x0002
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN                0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS                 1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT                1

/* RxB :: anaRxStatus :: pll_bypass [00:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK             0x0001
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN            0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS             1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT            0


/* union - case adc_CdrStatus2 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:06] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK              0xffc0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN             0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS              10
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT             6

/* RxB :: anaRxStatus :: rxMuxCkSel [05:05] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK             0x0020
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN            0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS             1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT            5

/* RxB :: anaRxStatus :: rxSeqStart [04:04] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK             0x0010
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN            0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS             1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT            4

/* RxB :: anaRxStatus :: reserved1 [03:01] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK              0x000e
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN             0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS              3
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT             1

/* RxB :: anaRxStatus :: rxSeqDone [00:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK              0x0001
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN             0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS              1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT             0


/* union - case adc_CdrStatus3 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:04] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK              0xfff0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN             0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS              12
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT             4

/* RxB :: anaRxStatus :: rxSeqStart [03:03] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK             0x0008
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN            0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS             1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT            3

/* RxB :: anaRxStatus :: reserved1 [02:01] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK              0x0006
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN             0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS              2
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT             1

/* RxB :: anaRxStatus :: allow_increment_PC [00:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK     0x0001
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN    0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS     1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT    0


/* union - case adc_CdrStatus4 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:08] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK              0xff00
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN             0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS              8
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT             8

/* RxB :: anaRxStatus :: rx_pwrdn [07:07] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK               0x0080
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN              0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS               1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT              7

/* RxB :: anaRxStatus :: freq_sel [06:06] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK               0x0040
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN              0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS               1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT              6

/* RxB :: anaRxStatus :: pll_lock_rstb [05:05] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK          0x0020
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN         0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS          1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT         5

/* RxB :: anaRxStatus :: pwrdn [04:04] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK                  0x0010
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN                 0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS                  1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT                 4

/* RxB :: anaRxStatus :: reserved1 [03:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK              0x000f
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN             0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS              4
#define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT             0


/* union - case adc_CdrStatus5 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK              0xffff
#define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN             0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS              16
#define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT             0


/* union - case adc_CdrStatus6 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:05] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK              0xffe0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN             0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS              11
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT             5

/* RxB :: anaRxStatus :: rx_reset [04:04] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK               0x0010
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN              0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS               1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT              4

/* RxB :: anaRxStatus :: rx_pwrdn [03:03] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK               0x0008
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN              0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS               1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT              3

/* RxB :: anaRxStatus :: reset_anlg [02:02] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK             0x0004
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN            0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS             1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT            2

/* RxB :: anaRxStatus :: pwrdn_rx [01:01] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK               0x0002
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN              0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS               1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT              1

/* RxB :: anaRxStatus :: pwrdn_pll [00:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK              0x0001
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN             0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS              1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT             0


/* union - case adc_CdrStatus7e [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:05] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK             0xffe0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN            0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS             11
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT            5

/* RxB :: anaRxStatus :: rxck0_even [04:04] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK            0x0010
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN           0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS            1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT           4

/* RxB :: anaRxStatus :: rxck1_even [03:03] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK            0x0008
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN           0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS            1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT           3

/* RxB :: anaRxStatus :: comdet_even [02:02] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK           0x0004
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN          0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS           1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT          2

/* RxB :: anaRxStatus :: en_cdet_even [01:01] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK          0x0002
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN         0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS          1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT         1

/* RxB :: anaRxStatus :: comma_adj_en_even [00:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK     0x0001
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN    0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS     1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT    0


/* union - case adc_CdrStatus7o [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:05] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK             0xffe0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN            0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS             11
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT            5

/* RxB :: anaRxStatus :: rxck0_odd [04:04] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK             0x0010
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN            0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS             1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT            4

/* RxB :: anaRxStatus :: rxck1_odd [03:03] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK             0x0008
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN            0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS             1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT            3

/* RxB :: anaRxStatus :: comdet_odd [02:02] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK            0x0004
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN           0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS            1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT           2

/* RxB :: anaRxStatus :: en_cdet_odd [01:01] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK           0x0002
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN          0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS           1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT          1

/* RxB :: anaRxStatus :: comma_adj_en_odd [00:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK      0x0001
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN     0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS      1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT     0


/* union - case adc_CdrStatus8 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:01] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK              0xfffe
#define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN             0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS              15
#define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT             1

/* RxB :: anaRxStatus :: sigdet [00:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK                 0x0001
#define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN                0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS                 1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT                0


/* union - case adc_CdrStatus9 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK              0xffff
#define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN             0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS              16
#define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT             0


/* union - case adc_CdrStatus10 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:07] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK             0xff80
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN            0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS             9
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT            7

/* RxB :: anaRxStatus :: prbs_en [06:06] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK               0x0040
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN              0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS               1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT              6

/* RxB :: anaRxStatus :: rstb_tst [05:05] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK              0x0020
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN             0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS              1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT             5

/* RxB :: anaRxStatus :: reserved1 [04:04] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK             0x0010
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN            0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS             1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT            4

/* RxB :: anaRxStatus :: prbs_state [03:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK            0x000f
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN           0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS            4
#define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT           0


/* union - case adc_CdrStatus11 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK             0xffff
#define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN            0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS             16
#define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT            0


/* union - case adc_CdrStatus12_1 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:06] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK           0xffc0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN          0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS           10
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT          6

/* RxB :: anaRxStatus :: enable4 [05:05] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK             0x0020
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN            0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS             1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT            5

/* RxB :: anaRxStatus :: radr_test [04:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK           0x001f
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN          0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS           5
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT          0


/* union - case adc_CdrStatus12_2 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:05] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK           0xffe0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN          0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS           11
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT          5

/* RxB :: anaRxStatus :: wadr_test [04:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK           0x001f
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN          0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS           5
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT          0


/* union - case adc_CdrStatus12_3 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:06] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK           0xffc0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN          0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS           10
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT          6

/* RxB :: anaRxStatus :: rxck_66B_tmux [05:05] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK       0x0020
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN      0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS       1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT      5

/* RxB :: anaRxStatus :: rstb_66B [04:04] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK            0x0010
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN           0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS            1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT           4

/* RxB :: anaRxStatus :: prstb_66B_mux [03:03] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK       0x0008
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN      0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS       1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT      3

/* RxB :: anaRxStatus :: rxck_i66_tmux [02:02] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK       0x0004
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN      0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS       1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT      2

/* RxB :: anaRxStatus :: rstb_i66 [01:01] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK            0x0002
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN           0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS            1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT           1

/* RxB :: anaRxStatus :: prstb_i66_mux [00:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK       0x0001
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN      0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS       1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT      0


/* union - case adc_CdrStatus12_4 [15:00] */
/* RxB :: anaRxStatus :: reserved0 [15:04] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK           0xfff0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN          0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS           12
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT          4

/* RxB :: anaRxStatus :: rfifo_error_r [03:02] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK       0x000c
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN      0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS       2
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT      2

/* RxB :: anaRxStatus :: rfifo_unflow [01:01] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK        0x0002
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN       0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS        1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT       1

/* RxB :: anaRxStatus :: rfifo_ovflow [00:00] */
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK        0x0001
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN       0
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS        1
#define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT       0


/* union - case integ_Status [15:00] */
/* RxB :: anaRxStatus :: integ_status [15:00] */
#define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK             0xffff
#define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN            0
#define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS             16
#define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT            0


/* union - case vco_Status [15:00] */
/* RxB :: anaRxStatus :: vco_status [15:00] */
#define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK                 0xffff
#define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN                0
#define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS                 16
#define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT                0


/* union - case prbs_Status [15:00] */
/* RxB :: anaRxStatus :: prbs_lock [15:15] */
#define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK                 0x8000
#define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN                0
#define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS                 1
#define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT                15

/* RxB :: anaRxStatus :: prbs_stky [14:14] */
#define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK                 0x4000
#define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN                0
#define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS                 1
#define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT                14

/* RxB :: anaRxStatus :: ptbs_errors [13:00] */
#define RXB_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK               0x3fff
#define RXB_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN              0
#define RXB_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS               14
#define RXB_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT              0



/****************************************************************************
 * RxB :: anaRxControl
 ***************************************************************************/
/* RxB :: anaRxControl :: reserved0 [15:10] */
#define RXB_ANARXCONTROL_RESERVED0_MASK                            0xfc00
#define RXB_ANARXCONTROL_RESERVED0_ALIGN                           0
#define RXB_ANARXCONTROL_RESERVED0_BITS                            6
#define RXB_ANARXCONTROL_RESERVED0_SHIFT                           10

/* RxB :: anaRxControl :: override_sigdet_en [09:09] */
#define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK                   0x0200
#define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN                  0
#define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS                   1
#define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT                  9

/* RxB :: anaRxControl :: override_sigdet_val [08:08] */
#define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK                  0x0100
#define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN                 0
#define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS                  1
#define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT                 8

/* RxB :: anaRxControl :: reserved1 [07:03] */
#define RXB_ANARXCONTROL_RESERVED1_MASK                            0x00f8
#define RXB_ANARXCONTROL_RESERVED1_ALIGN                           0
#define RXB_ANARXCONTROL_RESERVED1_BITS                            5
#define RXB_ANARXCONTROL_RESERVED1_SHIFT                           3

/* RxB :: anaRxControl :: status_sel [02:00] */
#define RXB_ANARXCONTROL_STATUS_SEL_MASK                           0x0007
#define RXB_ANARXCONTROL_STATUS_SEL_ALIGN                          0
#define RXB_ANARXCONTROL_STATUS_SEL_BITS                           3
#define RXB_ANARXCONTROL_STATUS_SEL_SHIFT                          0
#define RXB_ANARXCONTROL_STATUS_SEL_sigdetStatus                   0
#define RXB_ANARXCONTROL_STATUS_SEL_syncStatus                     1
#define RXB_ANARXCONTROL_STATUS_SEL_rxTestSel                      2
#define RXB_ANARXCONTROL_STATUS_SEL_scaleStatus                    3
#define RXB_ANARXCONTROL_STATUS_SEL_adcCdrStatus                   4
#define RXB_ANARXCONTROL_STATUS_SEL_integStatus                    5
#define RXB_ANARXCONTROL_STATUS_SEL_vcoStatus                      6
#define RXB_ANARXCONTROL_STATUS_SEL_prbsStatus                     7


/****************************************************************************
 * RxB :: anaRxTest
 ***************************************************************************/
/* RxB :: anaRxTest :: sigdet_mux_SM [15:12] */
#define RXB_ANARXTEST_SIGDET_MUX_SM_MASK                           0xf000
#define RXB_ANARXTEST_SIGDET_MUX_SM_ALIGN                          0
#define RXB_ANARXTEST_SIGDET_MUX_SM_BITS                           4
#define RXB_ANARXTEST_SIGDET_MUX_SM_SHIFT                          12

/* RxB :: anaRxTest :: reserved0 [11:09] */
#define RXB_ANARXTEST_RESERVED0_MASK                               0x0e00
#define RXB_ANARXTEST_RESERVED0_ALIGN                              0
#define RXB_ANARXTEST_RESERVED0_BITS                               3
#define RXB_ANARXTEST_RESERVED0_SHIFT                              9

/* RxB :: anaRxTest :: tpctrl_SM [08:04] */
#define RXB_ANARXTEST_TPCTRL_SM_MASK                               0x01f0
#define RXB_ANARXTEST_TPCTRL_SM_ALIGN                              0
#define RXB_ANARXTEST_TPCTRL_SM_BITS                               5
#define RXB_ANARXTEST_TPCTRL_SM_SHIFT                              4

/* RxB :: anaRxTest :: testMuxSelect_SM [03:00] */
#define RXB_ANARXTEST_TESTMUXSELECT_SM_MASK                        0x000f
#define RXB_ANARXTEST_TESTMUXSELECT_SM_ALIGN                       0
#define RXB_ANARXTEST_TESTMUXSELECT_SM_BITS                        4
#define RXB_ANARXTEST_TESTMUXSELECT_SM_SHIFT                       0


/****************************************************************************
 * RxB :: anaRxControl1G
 ***************************************************************************/
/* RxB :: anaRxControl1G :: fpat_md [15:15] */
#define RXB_ANARXCONTROL1G_FPAT_MD_MASK                            0x8000
#define RXB_ANARXCONTROL1G_FPAT_MD_ALIGN                           0
#define RXB_ANARXCONTROL1G_FPAT_MD_BITS                            1
#define RXB_ANARXCONTROL1G_FPAT_MD_SHIFT                           15

/* RxB :: anaRxControl1G :: pkt_count_en [14:14] */
#define RXB_ANARXCONTROL1G_PKT_COUNT_EN_MASK                       0x4000
#define RXB_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN                      0
#define RXB_ANARXCONTROL1G_PKT_COUNT_EN_BITS                       1
#define RXB_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT                      14

/* RxB :: anaRxControl1G :: staMuxRegDis [13:13] */
#define RXB_ANARXCONTROL1G_STAMUXREGDIS_MASK                       0x2000
#define RXB_ANARXCONTROL1G_STAMUXREGDIS_ALIGN                      0
#define RXB_ANARXCONTROL1G_STAMUXREGDIS_BITS                       1
#define RXB_ANARXCONTROL1G_STAMUXREGDIS_SHIFT                      13

/* RxB :: anaRxControl1G :: prbs_clr_dis [12:12] */
#define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_MASK                       0x1000
#define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN                      0
#define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_BITS                       1
#define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT                      12

/* RxB :: anaRxControl1G :: rxd_dec_sel [11:11] */
#define RXB_ANARXCONTROL1G_RXD_DEC_SEL_MASK                        0x0800
#define RXB_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN                       0
#define RXB_ANARXCONTROL1G_RXD_DEC_SEL_BITS                        1
#define RXB_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT                       11

/* RxB :: anaRxControl1G :: cgbad_tst [10:10] */
#define RXB_ANARXCONTROL1G_CGBAD_TST_MASK                          0x0400
#define RXB_ANARXCONTROL1G_CGBAD_TST_ALIGN                         0
#define RXB_ANARXCONTROL1G_CGBAD_TST_BITS                          1
#define RXB_ANARXCONTROL1G_CGBAD_TST_SHIFT                         10

/* RxB :: anaRxControl1G :: Emon_en [09:09] */
#define RXB_ANARXCONTROL1G_EMON_EN_MASK                            0x0200
#define RXB_ANARXCONTROL1G_EMON_EN_ALIGN                           0
#define RXB_ANARXCONTROL1G_EMON_EN_BITS                            1
#define RXB_ANARXCONTROL1G_EMON_EN_SHIFT                           9

/* RxB :: anaRxControl1G :: prbs_en [08:08] */
#define RXB_ANARXCONTROL1G_PRBS_EN_MASK                            0x0100
#define RXB_ANARXCONTROL1G_PRBS_EN_ALIGN                           0
#define RXB_ANARXCONTROL1G_PRBS_EN_BITS                            1
#define RXB_ANARXCONTROL1G_PRBS_EN_SHIFT                           8

/* RxB :: anaRxControl1G :: cgbad_en [07:07] */
#define RXB_ANARXCONTROL1G_CGBAD_EN_MASK                           0x0080
#define RXB_ANARXCONTROL1G_CGBAD_EN_ALIGN                          0
#define RXB_ANARXCONTROL1G_CGBAD_EN_BITS                           1
#define RXB_ANARXCONTROL1G_CGBAD_EN_SHIFT                          7

/* RxB :: anaRxControl1G :: cstretch [06:06] */
#define RXB_ANARXCONTROL1G_CSTRETCH_MASK                           0x0040
#define RXB_ANARXCONTROL1G_CSTRETCH_ALIGN                          0
#define RXB_ANARXCONTROL1G_CSTRETCH_BITS                           1
#define RXB_ANARXCONTROL1G_CSTRETCH_SHIFT                          6

/* RxB :: anaRxControl1G :: comma_low_byte_SM [05:05] */
#define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK                  0x0020
#define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN                 0
#define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS                  1
#define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT                 5

/* RxB :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */
#define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK               0x0010
#define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN              0
#define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS               1
#define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT              4

/* RxB :: anaRxControl1G :: reserved0 [03:02] */
#define RXB_ANARXCONTROL1G_RESERVED0_MASK                          0x000c
#define RXB_ANARXCONTROL1G_RESERVED0_ALIGN                         0
#define RXB_ANARXCONTROL1G_RESERVED0_BITS                          2
#define RXB_ANARXCONTROL1G_RESERVED0_SHIFT                         2

/* RxB :: anaRxControl1G :: freq_sel_force [01:01] */
#define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK                     0x0002
#define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN                    0
#define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS                     1
#define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT                    1

/* RxB :: anaRxControl1G :: freq_sel [00:00] */
#define RXB_ANARXCONTROL1G_FREQ_SEL_MASK                           0x0001
#define RXB_ANARXCONTROL1G_FREQ_SEL_ALIGN                          0
#define RXB_ANARXCONTROL1G_FREQ_SEL_BITS                           1
#define RXB_ANARXCONTROL1G_FREQ_SEL_SHIFT                          0


/****************************************************************************
 * RxB :: anaRxControlPci
 ***************************************************************************/
/* RxB :: anaRxControlPci :: comma_adj_sync_sel [15:15] */
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK                0x8000
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN               0
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS                1
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT               15

/* RxB :: anaRxControlPci :: comma_mask_force_r [14:14] */
#define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK                0x4000
#define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN               0
#define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS                1
#define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT               14

/* RxB :: anaRxControlPci :: comma_mask_r [13:13] */
#define RXB_ANARXCONTROLPCI_COMMA_MASK_R_MASK                      0x2000
#define RXB_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN                     0
#define RXB_ANARXCONTROLPCI_COMMA_MASK_R_BITS                      1
#define RXB_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT                     13

/* RxB :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */
#define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK         0x1000
#define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN        0
#define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS         1
#define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT        12

/* RxB :: anaRxControlPci :: sync_status_force_r_SM [11:11] */
#define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK            0x0800
#define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN           0
#define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS            1
#define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT           11

/* RxB :: anaRxControlPci :: sync_status_force_r [10:10] */
#define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK               0x0400
#define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN              0
#define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS               1
#define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT              10

/* RxB :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK         0x0200
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN        0
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS         1
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT        9

/* RxB :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK        0x0100
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN       0
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS        1
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT       8

/* RxB :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK           0x0080
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN          0
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS           1
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT          7

/* RxB :: anaRxControlPci :: comma_adj_en_r [06:06] */
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK                    0x0040
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN                   0
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS                    1
#define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT                   6

/* RxB :: anaRxControlPci :: link_en_force_SM [05:05] */
#define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK                  0x0020
#define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN                 0
#define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS                  1
#define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT                 5

/* RxB :: anaRxControlPci :: link_en_r [04:04] */
#define RXB_ANARXCONTROLPCI_LINK_EN_R_MASK                         0x0010
#define RXB_ANARXCONTROLPCI_LINK_EN_R_ALIGN                        0
#define RXB_ANARXCONTROLPCI_LINK_EN_R_BITS                         1
#define RXB_ANARXCONTROLPCI_LINK_EN_R_SHIFT                        4

/* RxB :: anaRxControlPci :: rx_polarity_force_SM [03:03] */
#define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK              0x0008
#define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN             0
#define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS              1
#define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT             3

/* RxB :: anaRxControlPci :: rx_polarity_r [02:02] */
#define RXB_ANARXCONTROLPCI_RX_POLARITY_R_MASK                     0x0004
#define RXB_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN                    0
#define RXB_ANARXCONTROLPCI_RX_POLARITY_R_BITS                     1
#define RXB_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT                    2

/* RxB :: anaRxControlPci :: integ_mode_SM [01:00] */
#define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_MASK                     0x0003
#define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN                    0
#define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_BITS                     2
#define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT                    0


/****************************************************************************
 * RxB :: anaRxAstatus
 ***************************************************************************/
/* RxB :: anaRxAstatus :: sigdet [15:15] */
#define RXB_ANARXASTATUS_SIGDET_MASK                               0x8000
#define RXB_ANARXASTATUS_SIGDET_ALIGN                              0
#define RXB_ANARXASTATUS_SIGDET_BITS                               1
#define RXB_ANARXASTATUS_SIGDET_SHIFT                              15

/* RxB :: anaRxAstatus :: rx_pf [14:12] */
#define RXB_ANARXASTATUS_RX_PF_MASK                                0x7000
#define RXB_ANARXASTATUS_RX_PF_ALIGN                               0
#define RXB_ANARXASTATUS_RX_PF_BITS                                3
#define RXB_ANARXASTATUS_RX_PF_SHIFT                               12

/* RxB :: anaRxAstatus :: dfe [11:06] */
#define RXB_ANARXASTATUS_DFE_MASK                                  0x0fc0
#define RXB_ANARXASTATUS_DFE_ALIGN                                 0
#define RXB_ANARXASTATUS_DFE_BITS                                  6
#define RXB_ANARXASTATUS_DFE_SHIFT                                 6

/* RxB :: anaRxAstatus :: reserved0 [05:05] */
#define RXB_ANARXASTATUS_RESERVED0_MASK                            0x0020
#define RXB_ANARXASTATUS_RESERVED0_ALIGN                           0
#define RXB_ANARXASTATUS_RESERVED0_BITS                            1
#define RXB_ANARXASTATUS_RESERVED0_SHIFT                           5

/* RxB :: anaRxAstatus :: vga [04:00] */
#define RXB_ANARXASTATUS_VGA_MASK                                  0x001f
#define RXB_ANARXASTATUS_VGA_ALIGN                                 0
#define RXB_ANARXASTATUS_VGA_BITS                                  5
#define RXB_ANARXASTATUS_VGA_SHIFT                                 0


/****************************************************************************
 * RxB :: anaRxAControl1
 ***************************************************************************/
/* RxB :: anaRxAControl1 :: imode_vcm [15:15] */
#define RXB_ANARXACONTROL1_IMODE_VCM_MASK                          0x8000
#define RXB_ANARXACONTROL1_IMODE_VCM_ALIGN                         0
#define RXB_ANARXACONTROL1_IMODE_VCM_BITS                          1
#define RXB_ANARXACONTROL1_IMODE_VCM_SHIFT                         15

/* RxB :: anaRxAControl1 :: imin_vcm [14:14] */
#define RXB_ANARXACONTROL1_IMIN_VCM_MASK                           0x4000
#define RXB_ANARXACONTROL1_IMIN_VCM_ALIGN                          0
#define RXB_ANARXACONTROL1_IMIN_VCM_BITS                           1
#define RXB_ANARXACONTROL1_IMIN_VCM_SHIFT                          14

/* RxB :: anaRxAControl1 :: imax_sigdet [13:13] */
#define RXB_ANARXACONTROL1_IMAX_SIGDET_MASK                        0x2000
#define RXB_ANARXACONTROL1_IMAX_SIGDET_ALIGN                       0
#define RXB_ANARXACONTROL1_IMAX_SIGDET_BITS                        1
#define RXB_ANARXACONTROL1_IMAX_SIGDET_SHIFT                       13

/* RxB :: anaRxAControl1 :: imode_sigdet [12:12] */
#define RXB_ANARXACONTROL1_IMODE_SIGDET_MASK                       0x1000
#define RXB_ANARXACONTROL1_IMODE_SIGDET_ALIGN                      0
#define RXB_ANARXACONTROL1_IMODE_SIGDET_BITS                       1
#define RXB_ANARXACONTROL1_IMODE_SIGDET_SHIFT                      12

/* RxB :: anaRxAControl1 :: imin_sigdet [11:11] */
#define RXB_ANARXACONTROL1_IMIN_SIGDET_MASK                        0x0800
#define RXB_ANARXACONTROL1_IMIN_SIGDET_ALIGN                       0
#define RXB_ANARXACONTROL1_IMIN_SIGDET_BITS                        1
#define RXB_ANARXACONTROL1_IMIN_SIGDET_SHIFT                       11

/* RxB :: anaRxAControl1 :: refh_rx [10:10] */
#define RXB_ANARXACONTROL1_REFH_RX_MASK                            0x0400
#define RXB_ANARXACONTROL1_REFH_RX_ALIGN                           0
#define RXB_ANARXACONTROL1_REFH_RX_BITS                            1
#define RXB_ANARXACONTROL1_REFH_RX_SHIFT                           10

/* RxB :: anaRxAControl1 :: refl_rx [09:09] */
#define RXB_ANARXACONTROL1_REFL_RX_MASK                            0x0200
#define RXB_ANARXACONTROL1_REFL_RX_ALIGN                           0
#define RXB_ANARXACONTROL1_REFL_RX_BITS                            1
#define RXB_ANARXACONTROL1_REFL_RX_SHIFT                           9

/* RxB :: anaRxAControl1 :: tport_en [08:08] */
#define RXB_ANARXACONTROL1_TPORT_EN_MASK                           0x0100
#define RXB_ANARXACONTROL1_TPORT_EN_ALIGN                          0
#define RXB_ANARXACONTROL1_TPORT_EN_BITS                           1
#define RXB_ANARXACONTROL1_TPORT_EN_SHIFT                          8

/* RxB :: anaRxAControl1 :: vddrb_bg [07:07] */
#define RXB_ANARXACONTROL1_VDDRB_BG_MASK                           0x0080
#define RXB_ANARXACONTROL1_VDDRB_BG_ALIGN                          0
#define RXB_ANARXACONTROL1_VDDRB_BG_BITS                           1
#define RXB_ANARXACONTROL1_VDDRB_BG_SHIFT                          7

/* RxB :: anaRxAControl1 :: sig_pwrdn [06:06] */
#define RXB_ANARXACONTROL1_SIG_PWRDN_MASK                          0x0040
#define RXB_ANARXACONTROL1_SIG_PWRDN_ALIGN                         0
#define RXB_ANARXACONTROL1_SIG_PWRDN_BITS                          1
#define RXB_ANARXACONTROL1_SIG_PWRDN_SHIFT                         6

/* RxB :: anaRxAControl1 :: offset_ctrl [05:03] */
#define RXB_ANARXACONTROL1_OFFSET_CTRL_MASK                        0x0038
#define RXB_ANARXACONTROL1_OFFSET_CTRL_ALIGN                       0
#define RXB_ANARXACONTROL1_OFFSET_CTRL_BITS                        3
#define RXB_ANARXACONTROL1_OFFSET_CTRL_SHIFT                       3

/* RxB :: anaRxAControl1 :: offset_sel [02:02] */
#define RXB_ANARXACONTROL1_OFFSET_SEL_MASK                         0x0004
#define RXB_ANARXACONTROL1_OFFSET_SEL_ALIGN                        0
#define RXB_ANARXACONTROL1_OFFSET_SEL_BITS                         1
#define RXB_ANARXACONTROL1_OFFSET_SEL_SHIFT                        2

/* RxB :: anaRxAControl1 :: reserved0 [01:00] */
#define RXB_ANARXACONTROL1_RESERVED0_MASK                          0x0003
#define RXB_ANARXACONTROL1_RESERVED0_ALIGN                         0
#define RXB_ANARXACONTROL1_RESERVED0_BITS                          2
#define RXB_ANARXACONTROL1_RESERVED0_SHIFT                         0


/****************************************************************************
 * RxB :: anaRxAControl2
 ***************************************************************************/
/* RxB :: anaRxAControl2 :: imax_clkbuf [15:15] */
#define RXB_ANARXACONTROL2_IMAX_CLKBUF_MASK                        0x8000
#define RXB_ANARXACONTROL2_IMAX_CLKBUF_ALIGN                       0
#define RXB_ANARXACONTROL2_IMAX_CLKBUF_BITS                        1
#define RXB_ANARXACONTROL2_IMAX_CLKBUF_SHIFT                       15

/* RxB :: anaRxAControl2 :: imode_clkbuf [14:14] */
#define RXB_ANARXACONTROL2_IMODE_CLKBUF_MASK                       0x4000
#define RXB_ANARXACONTROL2_IMODE_CLKBUF_ALIGN                      0
#define RXB_ANARXACONTROL2_IMODE_CLKBUF_BITS                       1
#define RXB_ANARXACONTROL2_IMODE_CLKBUF_SHIFT                      14

/* RxB :: anaRxAControl2 :: imin_clkbuf [13:13] */
#define RXB_ANARXACONTROL2_IMIN_CLKBUF_MASK                        0x2000
#define RXB_ANARXACONTROL2_IMIN_CLKBUF_ALIGN                       0
#define RXB_ANARXACONTROL2_IMIN_CLKBUF_BITS                        1
#define RXB_ANARXACONTROL2_IMIN_CLKBUF_SHIFT                       13

/* RxB :: anaRxAControl2 :: imax_eqfl [12:12] */
#define RXB_ANARXACONTROL2_IMAX_EQFL_MASK                          0x1000
#define RXB_ANARXACONTROL2_IMAX_EQFL_ALIGN                         0
#define RXB_ANARXACONTROL2_IMAX_EQFL_BITS                          1
#define RXB_ANARXACONTROL2_IMAX_EQFL_SHIFT                         12

/* RxB :: anaRxAControl2 :: imode_eqfl [11:11] */
#define RXB_ANARXACONTROL2_IMODE_EQFL_MASK                         0x0800
#define RXB_ANARXACONTROL2_IMODE_EQFL_ALIGN                        0
#define RXB_ANARXACONTROL2_IMODE_EQFL_BITS                         1
#define RXB_ANARXACONTROL2_IMODE_EQFL_SHIFT                        11

/* RxB :: anaRxAControl2 :: imin_eqfl [10:10] */
#define RXB_ANARXACONTROL2_IMIN_EQFL_MASK                          0x0400
#define RXB_ANARXACONTROL2_IMIN_EQFL_ALIGN                         0
#define RXB_ANARXACONTROL2_IMIN_EQFL_BITS                          1
#define RXB_ANARXACONTROL2_IMIN_EQFL_SHIFT                         10

/* RxB :: anaRxAControl2 :: imax_dfesum [09:09] */
#define RXB_ANARXACONTROL2_IMAX_DFESUM_MASK                        0x0200
#define RXB_ANARXACONTROL2_IMAX_DFESUM_ALIGN                       0
#define RXB_ANARXACONTROL2_IMAX_DFESUM_BITS                        1
#define RXB_ANARXACONTROL2_IMAX_DFESUM_SHIFT                       9

/* RxB :: anaRxAControl2 :: imode_dfesum [08:08] */
#define RXB_ANARXACONTROL2_IMODE_DFESUM_MASK                       0x0100
#define RXB_ANARXACONTROL2_IMODE_DFESUM_ALIGN                      0
#define RXB_ANARXACONTROL2_IMODE_DFESUM_BITS                       1
#define RXB_ANARXACONTROL2_IMODE_DFESUM_SHIFT                      8

/* RxB :: anaRxAControl2 :: imin_dfesum [07:07] */
#define RXB_ANARXACONTROL2_IMIN_DFESUM_MASK                        0x0080
#define RXB_ANARXACONTROL2_IMIN_DFESUM_ALIGN                       0
#define RXB_ANARXACONTROL2_IMIN_DFESUM_BITS                        1
#define RXB_ANARXACONTROL2_IMIN_DFESUM_SHIFT                       7

/* RxB :: anaRxAControl2 :: imax_vga [06:06] */
#define RXB_ANARXACONTROL2_IMAX_VGA_MASK                           0x0040
#define RXB_ANARXACONTROL2_IMAX_VGA_ALIGN                          0
#define RXB_ANARXACONTROL2_IMAX_VGA_BITS                           1
#define RXB_ANARXACONTROL2_IMAX_VGA_SHIFT                          6

/* RxB :: anaRxAControl2 :: imode_vga [05:05] */
#define RXB_ANARXACONTROL2_IMODE_VGA_MASK                          0x0020
#define RXB_ANARXACONTROL2_IMODE_VGA_ALIGN                         0
#define RXB_ANARXACONTROL2_IMODE_VGA_BITS                          1
#define RXB_ANARXACONTROL2_IMODE_VGA_SHIFT                         5

/* RxB :: anaRxAControl2 :: imin_vga [04:04] */
#define RXB_ANARXACONTROL2_IMIN_VGA_MASK                           0x0010
#define RXB_ANARXACONTROL2_IMIN_VGA_ALIGN                          0
#define RXB_ANARXACONTROL2_IMIN_VGA_BITS                           1
#define RXB_ANARXACONTROL2_IMIN_VGA_SHIFT                          4

/* RxB :: anaRxAControl2 :: imax_interp [03:03] */
#define RXB_ANARXACONTROL2_IMAX_INTERP_MASK                        0x0008
#define RXB_ANARXACONTROL2_IMAX_INTERP_ALIGN                       0
#define RXB_ANARXACONTROL2_IMAX_INTERP_BITS                        1
#define RXB_ANARXACONTROL2_IMAX_INTERP_SHIFT                       3

/* RxB :: anaRxAControl2 :: imode_interp [02:02] */
#define RXB_ANARXACONTROL2_IMODE_INTERP_MASK                       0x0004
#define RXB_ANARXACONTROL2_IMODE_INTERP_ALIGN                      0
#define RXB_ANARXACONTROL2_IMODE_INTERP_BITS                       1
#define RXB_ANARXACONTROL2_IMODE_INTERP_SHIFT                      2

/* RxB :: anaRxAControl2 :: imin_interp [01:01] */
#define RXB_ANARXACONTROL2_IMIN_INTERP_MASK                        0x0002
#define RXB_ANARXACONTROL2_IMIN_INTERP_ALIGN                       0
#define RXB_ANARXACONTROL2_IMIN_INTERP_BITS                        1
#define RXB_ANARXACONTROL2_IMIN_INTERP_SHIFT                       1

/* RxB :: anaRxAControl2 :: imax_vcm [00:00] */
#define RXB_ANARXACONTROL2_IMAX_VCM_MASK                           0x0001
#define RXB_ANARXACONTROL2_IMAX_VCM_ALIGN                          0
#define RXB_ANARXACONTROL2_IMAX_VCM_BITS                           1
#define RXB_ANARXACONTROL2_IMAX_VCM_SHIFT                          0


/****************************************************************************
 * RxB :: anaRxAControl3
 ***************************************************************************/
/* RxB :: anaRxAControl3 :: en_clk16 [15:15] */
#define RXB_ANARXACONTROL3_EN_CLK16_MASK                           0x8000
#define RXB_ANARXACONTROL3_EN_CLK16_ALIGN                          0
#define RXB_ANARXACONTROL3_EN_CLK16_BITS                           1
#define RXB_ANARXACONTROL3_EN_CLK16_SHIFT                          15

/* RxB :: anaRxAControl3 :: pd_ch_p1 [14:14] */
#define RXB_ANARXACONTROL3_PD_CH_P1_MASK                           0x4000
#define RXB_ANARXACONTROL3_PD_CH_P1_ALIGN                          0
#define RXB_ANARXACONTROL3_PD_CH_P1_BITS                           1
#define RXB_ANARXACONTROL3_PD_CH_P1_SHIFT                          14

/* RxB :: anaRxAControl3 :: en_vcctrl [13:13] */
#define RXB_ANARXACONTROL3_EN_VCCTRL_MASK                          0x2000
#define RXB_ANARXACONTROL3_EN_VCCTRL_ALIGN                         0
#define RXB_ANARXACONTROL3_EN_VCCTRL_BITS                          1
#define RXB_ANARXACONTROL3_EN_VCCTRL_SHIFT                         13

/* RxB :: anaRxAControl3 :: en_dfeclk [12:12] */
#define RXB_ANARXACONTROL3_EN_DFECLK_MASK                          0x1000
#define RXB_ANARXACONTROL3_EN_DFECLK_ALIGN                         0
#define RXB_ANARXACONTROL3_EN_DFECLK_BITS                          1
#define RXB_ANARXACONTROL3_EN_DFECLK_SHIFT                         12

/* RxB :: anaRxAControl3 :: en_hgain [11:11] */
#define RXB_ANARXACONTROL3_EN_HGAIN_MASK                           0x0800
#define RXB_ANARXACONTROL3_EN_HGAIN_ALIGN                          0
#define RXB_ANARXACONTROL3_EN_HGAIN_BITS                           1
#define RXB_ANARXACONTROL3_EN_HGAIN_SHIFT                          11

/* RxB :: anaRxAControl3 :: en_dfeckpwr [10:10] */
#define RXB_ANARXACONTROL3_EN_DFECKPWR_MASK                        0x0400
#define RXB_ANARXACONTROL3_EN_DFECKPWR_ALIGN                       0
#define RXB_ANARXACONTROL3_EN_DFECKPWR_BITS                        1
#define RXB_ANARXACONTROL3_EN_DFECKPWR_SHIFT                       10

/* RxB :: anaRxAControl3 :: offset_pd [09:09] */
#define RXB_ANARXACONTROL3_OFFSET_PD_MASK                          0x0200
#define RXB_ANARXACONTROL3_OFFSET_PD_ALIGN                         0
#define RXB_ANARXACONTROL3_OFFSET_PD_BITS                          1
#define RXB_ANARXACONTROL3_OFFSET_PD_SHIFT                         9

/* RxB :: anaRxAControl3 :: imax_dfetap [08:08] */
#define RXB_ANARXACONTROL3_IMAX_DFETAP_MASK                        0x0100
#define RXB_ANARXACONTROL3_IMAX_DFETAP_ALIGN                       0
#define RXB_ANARXACONTROL3_IMAX_DFETAP_BITS                        1
#define RXB_ANARXACONTROL3_IMAX_DFETAP_SHIFT                       8

/* RxB :: anaRxAControl3 :: imode_dfetap [07:07] */
#define RXB_ANARXACONTROL3_IMODE_DFETAP_MASK                       0x0080
#define RXB_ANARXACONTROL3_IMODE_DFETAP_ALIGN                      0
#define RXB_ANARXACONTROL3_IMODE_DFETAP_BITS                       1
#define RXB_ANARXACONTROL3_IMODE_DFETAP_SHIFT                      7

/* RxB :: anaRxAControl3 :: imin_dfetap [06:06] */
#define RXB_ANARXACONTROL3_IMIN_DFETAP_MASK                        0x0040
#define RXB_ANARXACONTROL3_IMIN_DFETAP_ALIGN                       0
#define RXB_ANARXACONTROL3_IMIN_DFETAP_BITS                        1
#define RXB_ANARXACONTROL3_IMIN_DFETAP_SHIFT                       6

/* RxB :: anaRxAControl3 :: imax_slcd2c [05:05] */
#define RXB_ANARXACONTROL3_IMAX_SLCD2C_MASK                        0x0020
#define RXB_ANARXACONTROL3_IMAX_SLCD2C_ALIGN                       0
#define RXB_ANARXACONTROL3_IMAX_SLCD2C_BITS                        1
#define RXB_ANARXACONTROL3_IMAX_SLCD2C_SHIFT                       5

/* RxB :: anaRxAControl3 :: imode_slcd2c [04:04] */
#define RXB_ANARXACONTROL3_IMODE_SLCD2C_MASK                       0x0010
#define RXB_ANARXACONTROL3_IMODE_SLCD2C_ALIGN                      0
#define RXB_ANARXACONTROL3_IMODE_SLCD2C_BITS                       1
#define RXB_ANARXACONTROL3_IMODE_SLCD2C_SHIFT                      4

/* RxB :: anaRxAControl3 :: imin_slcd2c [03:03] */
#define RXB_ANARXACONTROL3_IMIN_SLCD2C_MASK                        0x0008
#define RXB_ANARXACONTROL3_IMIN_SLCD2C_ALIGN                       0
#define RXB_ANARXACONTROL3_IMIN_SLCD2C_BITS                        1
#define RXB_ANARXACONTROL3_IMIN_SLCD2C_SHIFT                       3

/* RxB :: anaRxAControl3 :: imax_dfevref [02:02] */
#define RXB_ANARXACONTROL3_IMAX_DFEVREF_MASK                       0x0004
#define RXB_ANARXACONTROL3_IMAX_DFEVREF_ALIGN                      0
#define RXB_ANARXACONTROL3_IMAX_DFEVREF_BITS                       1
#define RXB_ANARXACONTROL3_IMAX_DFEVREF_SHIFT                      2

/* RxB :: anaRxAControl3 :: imode_dfevref [01:01] */
#define RXB_ANARXACONTROL3_IMODE_DFEVREF_MASK                      0x0002
#define RXB_ANARXACONTROL3_IMODE_DFEVREF_ALIGN                     0
#define RXB_ANARXACONTROL3_IMODE_DFEVREF_BITS                      1
#define RXB_ANARXACONTROL3_IMODE_DFEVREF_SHIFT                     1

/* RxB :: anaRxAControl3 :: imin_dfevref [00:00] */
#define RXB_ANARXACONTROL3_IMIN_DFEVREF_MASK                       0x0001
#define RXB_ANARXACONTROL3_IMIN_DFEVREF_ALIGN                      0
#define RXB_ANARXACONTROL3_IMIN_DFEVREF_BITS                       1
#define RXB_ANARXACONTROL3_IMIN_DFEVREF_SHIFT                      0


/****************************************************************************
 * Hypercore_USER_XgxsBlk2
 ***************************************************************************/
/****************************************************************************
 * XgxsBlk2 :: rxLnSwap
 ***************************************************************************/
/* XgxsBlk2 :: rxLnSwap :: rx_lnswap_en [15:15] */
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_MASK                        0x8000
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_ALIGN                       0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_BITS                        1
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_SHIFT                       15

/* XgxsBlk2 :: rxLnSwap :: rx_lnswap_force_en [14:14] */
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_MASK                  0x4000
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_ALIGN                 0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_BITS                  1
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_SHIFT                 14

/* XgxsBlk2 :: rxLnSwap :: Qset_prog_en [13:13] */
#define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_MASK                        0x2000
#define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_ALIGN                       0
#define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_BITS                        1
#define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_SHIFT                       13

/* XgxsBlk2 :: rxLnSwap :: rx_lnswap_link_en [12:12] */
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_MASK                   0x1000
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_ALIGN                  0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_BITS                   1
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_SHIFT                  12

/* XgxsBlk2 :: rxLnSwap :: Q0_msb [11:11] */
#define XGXSBLK2_RXLNSWAP_Q0_MSB_MASK                              0x0800
#define XGXSBLK2_RXLNSWAP_Q0_MSB_ALIGN                             0
#define XGXSBLK2_RXLNSWAP_Q0_MSB_BITS                              1
#define XGXSBLK2_RXLNSWAP_Q0_MSB_SHIFT                             11

/* XgxsBlk2 :: rxLnSwap :: Q1_msb [10:10] */
#define XGXSBLK2_RXLNSWAP_Q1_MSB_MASK                              0x0400
#define XGXSBLK2_RXLNSWAP_Q1_MSB_ALIGN                             0
#define XGXSBLK2_RXLNSWAP_Q1_MSB_BITS                              1
#define XGXSBLK2_RXLNSWAP_Q1_MSB_SHIFT                             10

/* XgxsBlk2 :: rxLnSwap :: Q2_msb [09:09] */
#define XGXSBLK2_RXLNSWAP_Q2_MSB_MASK                              0x0200
#define XGXSBLK2_RXLNSWAP_Q2_MSB_ALIGN                             0
#define XGXSBLK2_RXLNSWAP_Q2_MSB_BITS                              1
#define XGXSBLK2_RXLNSWAP_Q2_MSB_SHIFT                             9

/* XgxsBlk2 :: rxLnSwap :: Q3_msb [08:08] */
#define XGXSBLK2_RXLNSWAP_Q3_MSB_MASK                              0x0100
#define XGXSBLK2_RXLNSWAP_Q3_MSB_ALIGN                             0
#define XGXSBLK2_RXLNSWAP_Q3_MSB_BITS                              1
#define XGXSBLK2_RXLNSWAP_Q3_MSB_SHIFT                             8

/* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force0 [07:06] */
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_MASK                    0x00c0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_ALIGN                   0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_BITS                    2
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_SHIFT                   6

/* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force1 [05:04] */
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_MASK                    0x0030
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_ALIGN                   0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_BITS                    2
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_SHIFT                   4

/* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force2 [03:02] */
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_MASK                    0x000c
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_ALIGN                   0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_BITS                    2
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_SHIFT                   2

/* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force3 [01:00] */
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_MASK                    0x0003
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_ALIGN                   0
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_BITS                    2
#define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_SHIFT                   0


/****************************************************************************
 * XgxsBlk2 :: txLnSwap
 ***************************************************************************/
/* XgxsBlk2 :: txLnSwap :: tx_lnswap_en [15:15] */
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_MASK                        0x8000
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_ALIGN                       0
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_BITS                        1
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_SHIFT                       15

/* XgxsBlk2 :: txLnSwap :: reserved0 [14:08] */
#define XGXSBLK2_TXLNSWAP_RESERVED0_MASK                           0x7f00
#define XGXSBLK2_TXLNSWAP_RESERVED0_ALIGN                          0
#define XGXSBLK2_TXLNSWAP_RESERVED0_BITS                           7
#define XGXSBLK2_TXLNSWAP_RESERVED0_SHIFT                          8

/* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force0 [07:06] */
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_MASK                    0x00c0
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_ALIGN                   0
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_BITS                    2
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_SHIFT                   6

/* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force1 [05:04] */
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_MASK                    0x0030
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_ALIGN                   0
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_BITS                    2
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_SHIFT                   4

/* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force2 [03:02] */
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_MASK                    0x000c
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_ALIGN                   0
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_BITS                    2
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_SHIFT                   2

/* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force3 [01:00] */
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_MASK                    0x0003
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_ALIGN                   0
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_BITS                    2
#define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_SHIFT                   0


/****************************************************************************
 * XgxsBlk2 :: QsetLns01
 ***************************************************************************/
/* XgxsBlk2 :: QsetLns01 :: Q1 [15:08] */
#define XGXSBLK2_QSETLNS01_Q1_MASK                                 0xff00
#define XGXSBLK2_QSETLNS01_Q1_ALIGN                                0
#define XGXSBLK2_QSETLNS01_Q1_BITS                                 8
#define XGXSBLK2_QSETLNS01_Q1_SHIFT                                8

/* XgxsBlk2 :: QsetLns01 :: Q0 [07:00] */
#define XGXSBLK2_QSETLNS01_Q0_MASK                                 0x00ff
#define XGXSBLK2_QSETLNS01_Q0_ALIGN                                0
#define XGXSBLK2_QSETLNS01_Q0_BITS                                 8
#define XGXSBLK2_QSETLNS01_Q0_SHIFT                                0


/****************************************************************************
 * XgxsBlk2 :: QsetLns23
 ***************************************************************************/
/* XgxsBlk2 :: QsetLns23 :: Q3 [15:08] */
#define XGXSBLK2_QSETLNS23_Q3_MASK                                 0xff00
#define XGXSBLK2_QSETLNS23_Q3_ALIGN                                0
#define XGXSBLK2_QSETLNS23_Q3_BITS                                 8
#define XGXSBLK2_QSETLNS23_Q3_SHIFT                                8

/* XgxsBlk2 :: QsetLns23 :: Q2 [07:00] */
#define XGXSBLK2_QSETLNS23_Q2_MASK                                 0x00ff
#define XGXSBLK2_QSETLNS23_Q2_ALIGN                                0
#define XGXSBLK2_QSETLNS23_Q2_BITS                                 8
#define XGXSBLK2_QSETLNS23_Q2_SHIFT                                0


/****************************************************************************
 * XgxsBlk2 :: unicoreMode10g
 ***************************************************************************/
/* XgxsBlk2 :: unicoreMode10g :: reserved0 [15:08] */
#define XGXSBLK2_UNICOREMODE10G_RESERVED0_MASK                     0xff00
#define XGXSBLK2_UNICOREMODE10G_RESERVED0_ALIGN                    0
#define XGXSBLK2_UNICOREMODE10G_RESERVED0_BITS                     8
#define XGXSBLK2_UNICOREMODE10G_RESERVED0_SHIFT                    8

/* XgxsBlk2 :: unicoreMode10g :: unicoreMode10gHiG [07:04] */
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_MASK             0x00f0
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_ALIGN            0
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_BITS             4
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT            4
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS             0
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXG_nCC         1
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_IndLane_OS5      5
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_Indlanes         6
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_PCI              7
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS_nLQ         8
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS_nLQnCC      9
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_PBypass          10
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_PBypass_nDSK     11
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_ComboCoreMode    12
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_Clocks_off       15

/* XgxsBlk2 :: unicoreMode10g :: unicoreMode10gCx4 [03:00] */
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_MASK             0x000f
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_ALIGN            0
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_BITS             4
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_SHIFT            0
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS             0
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXG_nCC         1
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_IndLane_OS5      5
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_Indlanes         6
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_PCI              7
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS_nLQ         8
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS_nLQnCC      9
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_PBypass          10
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_PBypass_nDSK     11
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_ComboCoreMode    12
#define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_Clocks_off       15


/****************************************************************************
 * XgxsBlk2 :: indCombCtrl
 ***************************************************************************/
/* XgxsBlk2 :: indCombCtrl :: reserved0 [15:02] */
#define XGXSBLK2_INDCOMBCTRL_RESERVED0_MASK                        0xfffc
#define XGXSBLK2_INDCOMBCTRL_RESERVED0_ALIGN                       0
#define XGXSBLK2_INDCOMBCTRL_RESERVED0_BITS                        14
#define XGXSBLK2_INDCOMBCTRL_RESERVED0_SHIFT                       2

/* XgxsBlk2 :: indCombCtrl :: masterLn_indx [01:00] */
#define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_MASK                    0x0003
#define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_ALIGN                   0
#define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_BITS                    2
#define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_SHIFT                   0


/****************************************************************************
 * XgxsBlk2 :: TestModeLane
 ***************************************************************************/
/* XgxsBlk2 :: TestModeLane :: reserved0 [15:02] */
#define XGXSBLK2_TESTMODELANE_RESERVED0_MASK                       0xfffc
#define XGXSBLK2_TESTMODELANE_RESERVED0_ALIGN                      0
#define XGXSBLK2_TESTMODELANE_RESERVED0_BITS                       14
#define XGXSBLK2_TESTMODELANE_RESERVED0_SHIFT                      2

/* XgxsBlk2 :: TestModeLane :: slice_selector [01:00] */
#define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_MASK                  0x0003
#define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_ALIGN                 0
#define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_BITS                  2
#define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_SHIFT                 0


/****************************************************************************
 * XgxsBlk2 :: TestModeCombo
 ***************************************************************************/
/* XgxsBlk2 :: TestModeCombo :: reserved0 [15:12] */
#define XGXSBLK2_TESTMODECOMBO_RESERVED0_MASK                      0xf000
#define XGXSBLK2_TESTMODECOMBO_RESERVED0_ALIGN                     0
#define XGXSBLK2_TESTMODECOMBO_RESERVED0_BITS                      4
#define XGXSBLK2_TESTMODECOMBO_RESERVED0_SHIFT                     12

/* XgxsBlk2 :: TestModeCombo :: test_monitor_mode2 [11:06] */
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_MASK             0x0fc0
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_ALIGN            0
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_BITS             6
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_SHIFT            6

/* XgxsBlk2 :: TestModeCombo :: test_monitor_mode1 [05:00] */
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_MASK             0x003f
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_ALIGN            0
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_BITS             6
#define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_SHIFT            0


/****************************************************************************
 * XgxsBlk2 :: TestModeMux
 ***************************************************************************/
/* XgxsBlk2 :: TestModeMux :: reserved0 [15:04] */
#define XGXSBLK2_TESTMODEMUX_RESERVED0_MASK                        0xfff0
#define XGXSBLK2_TESTMODEMUX_RESERVED0_ALIGN                       0
#define XGXSBLK2_TESTMODEMUX_RESERVED0_BITS                        12
#define XGXSBLK2_TESTMODEMUX_RESERVED0_SHIFT                       4

/* XgxsBlk2 :: TestModeMux :: tmux_sel [03:01] */
#define XGXSBLK2_TESTMODEMUX_TMUX_SEL_MASK                         0x000e
#define XGXSBLK2_TESTMODEMUX_TMUX_SEL_ALIGN                        0
#define XGXSBLK2_TESTMODEMUX_TMUX_SEL_BITS                         3
#define XGXSBLK2_TESTMODEMUX_TMUX_SEL_SHIFT                        1

/* XgxsBlk2 :: TestModeMux :: tmux_en [00:00] */
#define XGXSBLK2_TESTMODEMUX_TMUX_EN_MASK                          0x0001
#define XGXSBLK2_TESTMODEMUX_TMUX_EN_ALIGN                         0
#define XGXSBLK2_TESTMODEMUX_TMUX_EN_BITS                          1
#define XGXSBLK2_TESTMODEMUX_TMUX_EN_SHIFT                         0


/****************************************************************************
 * XgxsBlk2 :: cx4SigdetCnt
 ***************************************************************************/
/* XgxsBlk2 :: cx4SigdetCnt :: cx4SigdetCnt [15:00] */
#define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_MASK                    0xffff
#define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_ALIGN                   0
#define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_BITS                    16
#define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_SHIFT                   0


/****************************************************************************
 * XgxsBlk2 :: laneReset
 ***************************************************************************/
/* XgxsBlk2 :: laneReset :: reset_mdio [15:15] */
#define XGXSBLK2_LANERESET_RESET_MDIO_MASK                         0x8000
#define XGXSBLK2_LANERESET_RESET_MDIO_ALIGN                        0
#define XGXSBLK2_LANERESET_RESET_MDIO_BITS                         1
#define XGXSBLK2_LANERESET_RESET_MDIO_SHIFT                        15

/* XgxsBlk2 :: laneReset :: reserved0 [14:09] */
#define XGXSBLK2_LANERESET_RESERVED0_MASK                          0x7e00
#define XGXSBLK2_LANERESET_RESERVED0_ALIGN                         0
#define XGXSBLK2_LANERESET_RESERVED0_BITS                          6
#define XGXSBLK2_LANERESET_RESERVED0_SHIFT                         9

/* XgxsBlk2 :: laneReset :: reset_pll [08:08] */
#define XGXSBLK2_LANERESET_RESET_PLL_MASK                          0x0100
#define XGXSBLK2_LANERESET_RESET_PLL_ALIGN                         0
#define XGXSBLK2_LANERESET_RESET_PLL_BITS                          1
#define XGXSBLK2_LANERESET_RESET_PLL_SHIFT                         8

/* XgxsBlk2 :: laneReset :: reset_tx [07:04] */
#define XGXSBLK2_LANERESET_RESET_TX_MASK                           0x00f0
#define XGXSBLK2_LANERESET_RESET_TX_ALIGN                          0
#define XGXSBLK2_LANERESET_RESET_TX_BITS                           4
#define XGXSBLK2_LANERESET_RESET_TX_SHIFT                          4

/* XgxsBlk2 :: laneReset :: reset_rx [03:00] */
#define XGXSBLK2_LANERESET_RESET_RX_MASK                           0x000f
#define XGXSBLK2_LANERESET_RESET_RX_ALIGN                          0
#define XGXSBLK2_LANERESET_RESET_RX_BITS                           4
#define XGXSBLK2_LANERESET_RESET_RX_SHIFT                          0


/****************************************************************************
 * XgxsBlk2 :: xgxsStatus6
 ***************************************************************************/
/* XgxsBlk2 :: xgxsStatus6 :: reserved0 [15:11] */
#define XGXSBLK2_XGXSSTATUS6_RESERVED0_MASK                        0xf800
#define XGXSBLK2_XGXSSTATUS6_RESERVED0_ALIGN                       0
#define XGXSBLK2_XGXSSTATUS6_RESERVED0_BITS                        5
#define XGXSBLK2_XGXSSTATUS6_RESERVED0_SHIFT                       11

/* XgxsBlk2 :: xgxsStatus6 :: hcd_over_1g [10:00] */
#define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_MASK                      0x07ff
#define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_ALIGN                     0
#define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_BITS                      11
#define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_SHIFT                     0


/****************************************************************************
 * XgxsBlk2 :: cl73Control7
 ***************************************************************************/
/* XgxsBlk2 :: cl73Control7 :: cl73_an_switch_cntL [15:00] */
#define XGXSBLK2_CL73CONTROL7_CL73_AN_SWITCH_CNTL_MASK             0xffff
#define XGXSBLK2_CL73CONTROL7_CL73_AN_SWITCH_CNTL_ALIGN            0
#define XGXSBLK2_CL73CONTROL7_CL73_AN_SWITCH_CNTL_BITS             16
#define XGXSBLK2_CL73CONTROL7_CL73_AN_SWITCH_CNTL_SHIFT            0


/****************************************************************************
 * XgxsBlk2 :: cl73Control8
 ***************************************************************************/
/* XgxsBlk2 :: cl73Control8 :: reserved0 [15:08] */
#define XGXSBLK2_CL73CONTROL8_RESERVED0_MASK                       0xff00
#define XGXSBLK2_CL73CONTROL8_RESERVED0_ALIGN                      0
#define XGXSBLK2_CL73CONTROL8_RESERVED0_BITS                       8
#define XGXSBLK2_CL73CONTROL8_RESERVED0_SHIFT                      8

/* XgxsBlk2 :: cl73Control8 :: cl73_an_switch_cntH [07:00] */
#define XGXSBLK2_CL73CONTROL8_CL73_AN_SWITCH_CNTH_MASK             0x00ff
#define XGXSBLK2_CL73CONTROL8_CL73_AN_SWITCH_CNTH_ALIGN            0
#define XGXSBLK2_CL73CONTROL8_CL73_AN_SWITCH_CNTH_BITS             8
#define XGXSBLK2_CL73CONTROL8_CL73_AN_SWITCH_CNTH_SHIFT            0


/****************************************************************************
 * Hypercore_USER_XgxsBlk3
 ***************************************************************************/
/****************************************************************************
 * XgxsBlk3 :: localStatus
 ***************************************************************************/
/* XgxsBlk3 :: localStatus :: reserved0 [15:03] */
#define XGXSBLK3_LOCALSTATUS_RESERVED0_MASK                        0xfff8
#define XGXSBLK3_LOCALSTATUS_RESERVED0_ALIGN                       0
#define XGXSBLK3_LOCALSTATUS_RESERVED0_BITS                        13
#define XGXSBLK3_LOCALSTATUS_RESERVED0_SHIFT                       3

/* XgxsBlk3 :: localStatus :: localIACRdy [02:02] */
#define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_MASK                      0x0004
#define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_ALIGN                     0
#define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_BITS                      1
#define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_SHIFT                     2

/* XgxsBlk3 :: localStatus :: localRdDataRdy [01:01] */
#define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_MASK                   0x0002
#define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_ALIGN                  0
#define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_BITS                   1
#define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_SHIFT                  1

/* XgxsBlk3 :: localStatus :: localMdioEn [00:00] */
#define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_MASK                      0x0001
#define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_ALIGN                     0
#define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_BITS                      1
#define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_SHIFT                     0


/****************************************************************************
 * XgxsBlk3 :: localControl0
 ***************************************************************************/
/* XgxsBlk3 :: localControl0 :: remoteWrite_ln3_msb [15:15] */
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_MASK            0x8000
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_ALIGN           0
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_BITS            1
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_SHIFT           15

/* XgxsBlk3 :: localControl0 :: remoteWrite_ln2_msb [14:14] */
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_MASK            0x4000
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_ALIGN           0
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_BITS            1
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_SHIFT           14

/* XgxsBlk3 :: localControl0 :: remoteWrite_ln1_msb [13:13] */
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_MASK            0x2000
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_ALIGN           0
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_BITS            1
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_SHIFT           13

/* XgxsBlk3 :: localControl0 :: remoteWrite_ln0_msb [12:12] */
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_MASK            0x1000
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_ALIGN           0
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_BITS            1
#define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_SHIFT           12

/* XgxsBlk3 :: localControl0 :: reserved0 [11:08] */
#define XGXSBLK3_LOCALCONTROL0_RESERVED0_MASK                      0x0f00
#define XGXSBLK3_LOCALCONTROL0_RESERVED0_ALIGN                     0
#define XGXSBLK3_LOCALCONTROL0_RESERVED0_BITS                      4
#define XGXSBLK3_LOCALCONTROL0_RESERVED0_SHIFT                     8

/* XgxsBlk3 :: localControl0 :: Q0_DetDis [07:07] */
#define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_MASK                      0x0080
#define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_ALIGN                     0
#define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_BITS                      1
#define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_SHIFT                     7

/* XgxsBlk3 :: localControl0 :: remoteMdioPassThru [06:06] */
#define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_MASK             0x0040
#define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_ALIGN            0
#define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_BITS             1
#define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_SHIFT            6

/* XgxsBlk3 :: localControl0 :: remoteMdioEndPnt [05:05] */
#define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_MASK               0x0020
#define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_ALIGN              0
#define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_BITS               1
#define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_SHIFT              5

/* XgxsBlk3 :: localControl0 :: extRemoteMdioEn [04:04] */
#define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_MASK                0x0010
#define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_ALIGN               0
#define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_BITS                1
#define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_SHIFT               4

/* XgxsBlk3 :: localControl0 :: rx_inBandMdio_rst [03:03] */
#define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_MASK              0x0008
#define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_ALIGN             0
#define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_BITS              1
#define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_SHIFT             3

/* XgxsBlk3 :: localControl0 :: tx_inBandMdio_rst [02:02] */
#define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_MASK              0x0004
#define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_ALIGN             0
#define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_BITS              1
#define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_SHIFT             2

/* XgxsBlk3 :: localControl0 :: localWriteReq [01:01] */
#define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_MASK                  0x0002
#define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_ALIGN                 0
#define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_BITS                  1
#define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_SHIFT                 1

/* XgxsBlk3 :: localControl0 :: remoteMdioEn_reg [00:00] */
#define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_MASK               0x0001
#define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_ALIGN              0
#define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_BITS               1
#define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_SHIFT              0


/****************************************************************************
 * XgxsBlk3 :: localControl1
 ***************************************************************************/
/* XgxsBlk3 :: localControl1 :: rx_inBandMdio_Q0 [15:08] */
#define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_MASK               0xff00
#define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_ALIGN              0
#define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_BITS               8
#define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_SHIFT              8

/* XgxsBlk3 :: localControl1 :: reserved0 [07:04] */
#define XGXSBLK3_LOCALCONTROL1_RESERVED0_MASK                      0x00f0
#define XGXSBLK3_LOCALCONTROL1_RESERVED0_ALIGN                     0
#define XGXSBLK3_LOCALCONTROL1_RESERVED0_BITS                      4
#define XGXSBLK3_LOCALCONTROL1_RESERVED0_SHIFT                     4

/* XgxsBlk3 :: localControl1 :: localRemoteErrorClr [03:03] */
#define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_MASK            0x0008
#define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_ALIGN           0
#define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_BITS            1
#define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_SHIFT           3

/* XgxsBlk3 :: localControl1 :: rx_inBandMdioStatSel [02:00] */
#define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_MASK           0x0007
#define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_ALIGN          0
#define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_BITS           3
#define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_SHIFT          0


/****************************************************************************
 * XgxsBlk3 :: remoteWrite03
 ***************************************************************************/
/* XgxsBlk3 :: remoteWrite03 :: localWrite_ln0_lsb [15:08] */
#define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_MASK             0xff00
#define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_ALIGN            0
#define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_BITS             8
#define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_SHIFT            8

/* XgxsBlk3 :: remoteWrite03 :: localWrite_ln3_lsb [07:00] */
#define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_MASK             0x00ff
#define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_ALIGN            0
#define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_BITS             8
#define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_SHIFT            0


/****************************************************************************
 * XgxsBlk3 :: remoteWrite12
 ***************************************************************************/
/* XgxsBlk3 :: remoteWrite12 :: localWrite_ln1_lsb [15:08] */
#define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_MASK             0xff00
#define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_ALIGN            0
#define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_BITS             8
#define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_SHIFT            8

/* XgxsBlk3 :: remoteWrite12 :: localWrite_ln2_lsb [07:00] */
#define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_MASK             0x00ff
#define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_ALIGN            0
#define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_BITS             8
#define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_SHIFT            0


/****************************************************************************
 * XgxsBlk3 :: remoteRead12
 ***************************************************************************/
/* XgxsBlk3 :: remoteRead12 :: localRdData [15:00] */
#define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_MASK                     0xffff
#define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_ALIGN                    0
#define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_BITS                     16
#define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_SHIFT                    0


/****************************************************************************
 * XgxsBlk3 :: remoteReadx3
 ***************************************************************************/
/* XgxsBlk3 :: remoteReadx3 :: reserved0 [15:08] */
#define XGXSBLK3_REMOTEREADX3_RESERVED0_MASK                       0xff00
#define XGXSBLK3_REMOTEREADX3_RESERVED0_ALIGN                      0
#define XGXSBLK3_REMOTEREADX3_RESERVED0_BITS                       8
#define XGXSBLK3_REMOTEREADX3_RESERVED0_SHIFT                      8

/* XgxsBlk3 :: remoteReadx3 :: localRdDataId [07:00] */
#define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_MASK                   0x00ff
#define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_ALIGN                  0
#define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_BITS                   8
#define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_SHIFT                  0


/****************************************************************************
 * XgxsBlk3 :: rx_inBandMdioStat
 ***************************************************************************/
/* union - case remoteStatus [15:00] */
/* XgxsBlk3 :: rx_inBandMdioStat :: remoteStatus [15:00] */
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_MASK  0xffff
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_ALIGN 0
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_BITS  16
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_SHIFT 0


/* union - case remoteControl [15:00] */
/* XgxsBlk3 :: rx_inBandMdioStat :: remoteControl [15:00] */
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_MASK 0xffff
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_ALIGN 0
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_BITS 16
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_SHIFT 0


/* union - case remoteAddr [15:00] */
/* XgxsBlk3 :: rx_inBandMdioStat :: remoteAddr [15:00] */
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_MASK      0xffff
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_ALIGN     0
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_BITS      16
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_SHIFT     0


/* union - case remoteWrtData [15:00] */
/* XgxsBlk3 :: rx_inBandMdioStat :: remoteWrtData [15:00] */
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_MASK 0xffff
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_ALIGN 0
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_BITS 16
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_SHIFT 0


/* union - case remoteIACn_sel [15:00] */
/* XgxsBlk3 :: rx_inBandMdioStat :: reserved0 [15:08] */
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_MASK   0xff00
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_ALIGN  0
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_BITS   8
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_SHIFT  8

/* XgxsBlk3 :: rx_inBandMdioStat :: remoteIACn [07:00] */
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_MASK  0x00ff
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_ALIGN 0
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_BITS  8
#define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_SHIFT 0


/* union - case rx_inBandTestBus [15:00] */
/* XgxsBlk3 :: rx_inBandMdioStat :: rx_inBandTestBus [15:00] */
#define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_MASK 0xffff
#define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_ALIGN 0
#define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_BITS 16
#define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_SHIFT 0


/* union - case StatusOff [15:00] */
/* XgxsBlk3 :: rx_inBandMdioStat :: reserved0 [15:00] */
#define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_MASK        0xffff
#define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_ALIGN       0
#define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_BITS        16
#define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_SHIFT       0



/****************************************************************************
 * XgxsBlk3 :: localIAC
 ***************************************************************************/
/* XgxsBlk3 :: localIAC :: IAC_ln1_ln2 [15:08] */
#define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_MASK                         0xff00
#define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_ALIGN                        0
#define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_BITS                         8
#define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_SHIFT                        8

/* XgxsBlk3 :: localIAC :: reserved0 [07:01] */
#define XGXSBLK3_LOCALIAC_RESERVED0_MASK                           0x00fe
#define XGXSBLK3_LOCALIAC_RESERVED0_ALIGN                          0
#define XGXSBLK3_LOCALIAC_RESERVED0_BITS                           7
#define XGXSBLK3_LOCALIAC_RESERVED0_SHIFT                          1

/* XgxsBlk3 :: localIAC :: localIACReq [00:00] */
#define XGXSBLK3_LOCALIAC_LOCALIACREQ_MASK                         0x0001
#define XGXSBLK3_LOCALIAC_LOCALIACREQ_ALIGN                        0
#define XGXSBLK3_LOCALIAC_LOCALIACREQ_BITS                         1
#define XGXSBLK3_LOCALIAC_LOCALIACREQ_SHIFT                        0


/****************************************************************************
 * XgxsBlk3 :: remoteIACn
 ***************************************************************************/
/* XgxsBlk3 :: remoteIACn :: reserved0 [15:08] */
#define XGXSBLK3_REMOTEIACN_RESERVED0_MASK                         0xff00
#define XGXSBLK3_REMOTEIACN_RESERVED0_ALIGN                        0
#define XGXSBLK3_REMOTEIACN_RESERVED0_BITS                         8
#define XGXSBLK3_REMOTEIACN_RESERVED0_SHIFT                        8

/* XgxsBlk3 :: remoteIACn :: localIACn [07:00] */
#define XGXSBLK3_REMOTEIACN_LOCALIACN_MASK                         0x00ff
#define XGXSBLK3_REMOTEIACN_LOCALIACN_ALIGN                        0
#define XGXSBLK3_REMOTEIACN_LOCALIACN_BITS                         8
#define XGXSBLK3_REMOTEIACN_LOCALIACN_SHIFT                        0


/****************************************************************************
 * Hypercore_USER_GP_Status
 ***************************************************************************/
/****************************************************************************
 * GP_Status :: MiscRxStatus
 ***************************************************************************/
/* union - case statusSelect0 [15:00] */
/* GP_Status :: MiscRxStatus :: capture_NP_lh [15:15] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_MASK    0x8000
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_ALIGN   0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_BITS    1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_SHIFT   15

/* GP_Status :: MiscRxStatus :: teton_brk_link_lh [14:14] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_MASK 0x4000
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_SHIFT 14

/* GP_Status :: MiscRxStatus :: UP3_lh [13:13] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_MASK           0x2000
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_ALIGN          0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_BITS           1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_SHIFT          13

/* GP_Status :: MiscRxStatus :: MP5_lh [12:12] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_MASK           0x1000
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_ALIGN          0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_BITS           1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_SHIFT          12

/* GP_Status :: MiscRxStatus :: nonMatchingOUI_lh [11:11] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_MASK 0x0800
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_SHIFT 11

/* GP_Status :: MiscRxStatus :: matchingOUI_msb_lh [10:10] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_MASK 0x0400
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_SHIFT 10

/* GP_Status :: MiscRxStatus :: matchingOUI_lsb_lh [09:09] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_MASK 0x0200
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_SHIFT 9

/* GP_Status :: MiscRxStatus :: invalidSeq_lh [08:08] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_MASK    0x0100
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_ALIGN   0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_BITS    1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_SHIFT   8

/* GP_Status :: MiscRxStatus :: nullMP_lh [07:07] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_MASK        0x0080
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_ALIGN       0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_BITS        1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_SHIFT       7

/* GP_Status :: MiscRxStatus :: remotePhyMP_lh [06:06] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_MASK   0x0040
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_ALIGN  0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_BITS   1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_SHIFT  6

/* GP_Status :: MiscRxStatus :: nonMatchingMP_lh [05:05] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_MASK 0x0020
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_SHIFT 5

/* GP_Status :: MiscRxStatus :: over1gMP_lh [04:04] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_MASK      0x0010
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_ALIGN     0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_BITS      1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_SHIFT     4

/* GP_Status :: MiscRxStatus :: rx_config_is_0_lh [03:03] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_MASK 0x0008
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_SHIFT 3

/* GP_Status :: MiscRxStatus :: np_toggle_err_lh [02:02] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_MASK 0x0004
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_SHIFT 2

/* GP_Status :: MiscRxStatus :: mr_np_lh [01:01] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_MASK         0x0002
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_ALIGN        0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_BITS         1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_SHIFT        1

/* GP_Status :: MiscRxStatus :: mr_bp_lh [00:00] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_MASK         0x0001
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_ALIGN        0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_BITS         1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_SHIFT        0


/* union - case statusSelect1 [15:00] */
/* GP_Status :: MiscRxStatus :: reserved0 [15:04] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_MASK        0xfff0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_ALIGN       0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_BITS        12
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_SHIFT       4

/* GP_Status :: MiscRxStatus :: np_count [03:00] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_MASK         0x000f
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_ALIGN        0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_BITS         4
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_SHIFT        0


/* union - case statusSelect2 [15:00] */
/* GP_Status :: MiscRxStatus :: reserved0 [15:06] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_MASK        0xffc0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_ALIGN       0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_BITS        10
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_SHIFT       6

/* GP_Status :: MiscRxStatus :: remote_phy_enable [05:05] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_MASK 0x0020
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_SHIFT 5

/* GP_Status :: MiscRxStatus :: det_teton_mode [04:04] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_MASK   0x0010
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_ALIGN  0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_BITS   1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_SHIFT  4

/* GP_Status :: MiscRxStatus :: cu_linkdown [03:03] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_MASK      0x0008
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_ALIGN     0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_BITS      1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_SHIFT     3

/* GP_Status :: MiscRxStatus :: cu_resolution_error [02:02] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_MASK 0x0004
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_SHIFT 2

/* GP_Status :: MiscRxStatus :: remotePhy_autosel [01:01] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_MASK 0x0002
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_SHIFT 1

/* GP_Status :: MiscRxStatus :: rx_config_isNot_0_lh [00:00] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_MASK 0x0001
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_SHIFT 0


/* union - case statusSelect3 [15:00] */
/* GP_Status :: MiscRxStatus :: reserved0 [15:06] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_RESERVED0_MASK        0xffc0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_RESERVED0_ALIGN       0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_RESERVED0_BITS        10
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_RESERVED0_SHIFT       6

/* GP_Status :: MiscRxStatus :: sgmii_selector_mismatch [05:05] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_MASK 0x0020
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_SHIFT 5

/* GP_Status :: MiscRxStatus :: autoneg_enable_ov [04:04] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_MASK 0x0010
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_BITS 1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_SHIFT 4

/* GP_Status :: MiscRxStatus :: s_mr_an_enable [03:03] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_MASK   0x0008
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_ALIGN  0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_BITS   1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_SHIFT  3

/* GP_Status :: MiscRxStatus :: s_cl73_rslv_KX4 [02:02] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_MASK  0x0004
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_ALIGN 0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_BITS  1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_SHIFT 2

/* GP_Status :: MiscRxStatus :: s_cl73_rslv_KX [01:01] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_MASK   0x0002
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_ALIGN  0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_BITS   1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_SHIFT  1

/* GP_Status :: MiscRxStatus :: KX_detect [00:00] */
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_MASK        0x0001
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_ALIGN       0
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_BITS        1
#define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_SHIFT       0



/****************************************************************************
 * GP_Status :: xgxsStatus0
 ***************************************************************************/
/* GP_Status :: xgxsStatus0 :: status_en [15:15] */
#define GP_STATUS_XGXSSTATUS0_STATUS_EN_MASK                       0x8000
#define GP_STATUS_XGXSSTATUS0_STATUS_EN_ALIGN                      0
#define GP_STATUS_XGXSSTATUS0_STATUS_EN_BITS                       1
#define GP_STATUS_XGXSSTATUS0_STATUS_EN_SHIFT                      15

/* GP_Status :: xgxsStatus0 :: reserved0 [14:14] */
#define GP_STATUS_XGXSSTATUS0_RESERVED0_MASK                       0x4000
#define GP_STATUS_XGXSSTATUS0_RESERVED0_ALIGN                      0
#define GP_STATUS_XGXSSTATUS0_RESERVED0_BITS                       1
#define GP_STATUS_XGXSSTATUS0_RESERVED0_SHIFT                      14

/* GP_Status :: xgxsStatus0 :: tx_remote_fault [13:13] */
#define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_MASK                 0x2000
#define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_ALIGN                0
#define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_BITS                 1
#define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_SHIFT                13

/* GP_Status :: xgxsStatus0 :: rx_remote_fault [12:12] */
#define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_MASK                 0x1000
#define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_ALIGN                0
#define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_BITS                 1
#define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_SHIFT                12

/* GP_Status :: xgxsStatus0 :: txpll_lock [11:11] */
#define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_MASK                      0x0800
#define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_ALIGN                     0
#define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_BITS                      1
#define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_SHIFT                     11

/* GP_Status :: xgxsStatus0 :: txd_fifo_err [10:10] */
#define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_MASK                    0x0400
#define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_ALIGN                   0
#define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_BITS                    1
#define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_SHIFT                   10

/* GP_Status :: xgxsStatus0 :: sequencer_done [09:09] */
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_MASK                  0x0200
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_ALIGN                 0
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_BITS                  1
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_SHIFT                 9

/* GP_Status :: xgxsStatus0 :: sequencer_pass [08:08] */
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_MASK                  0x0100
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_ALIGN                 0
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_BITS                  1
#define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_SHIFT                 8

/* GP_Status :: xgxsStatus0 :: rxferr [07:04] */
#define GP_STATUS_XGXSSTATUS0_RXFERR_MASK                          0x00f0
#define GP_STATUS_XGXSSTATUS0_RXFERR_ALIGN                         0
#define GP_STATUS_XGXSSTATUS0_RXFERR_BITS                          4
#define GP_STATUS_XGXSSTATUS0_RXFERR_SHIFT                         4

/* GP_Status :: xgxsStatus0 :: pll_mode_afe [03:03] */
#define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_MASK                    0x0008
#define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_ALIGN                   0
#define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_BITS                    1
#define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_SHIFT                   3

/* GP_Status :: xgxsStatus0 :: ckcmp_unflow [02:02] */
#define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_MASK                    0x0004
#define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_ALIGN                   0
#define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_BITS                    1
#define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_SHIFT                   2

/* GP_Status :: xgxsStatus0 :: ckcmp_ovflow [01:01] */
#define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_MASK                    0x0002
#define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_ALIGN                   0
#define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_BITS                    1
#define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_SHIFT                   1

/* GP_Status :: xgxsStatus0 :: skew_status [00:00] */
#define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_MASK                     0x0001
#define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_ALIGN                    0
#define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_BITS                     1
#define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_SHIFT                    0


/****************************************************************************
 * GP_Status :: xgxsStatus1
 ***************************************************************************/
/* GP_Status :: xgxsStatus1 :: mode_10g_tx [15:12] */
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_MASK                     0xf000
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_ALIGN                    0
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_BITS                     4
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_SHIFT                    12
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXS                     0
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXG_nCC                 1
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_IndLane_OS5              5
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_Indlanes                 6
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_PCI                      7
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXS_nLQ                 8
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXS_nLQnCC              9
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_PBypass                  10
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_PBypass_nDSK             11
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_ComboCoreMode            12
#define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_Clocks_off               15

/* GP_Status :: xgxsStatus1 :: serdesMode_en_tx [11:11] */
#define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_MASK                0x0800
#define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_ALIGN               0
#define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_BITS                1
#define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_SHIFT               11

/* GP_Status :: xgxsStatus1 :: sgmii_mode [10:10] */
#define GP_STATUS_XGXSSTATUS1_SGMII_MODE_MASK                      0x0400
#define GP_STATUS_XGXSSTATUS1_SGMII_MODE_ALIGN                     0
#define GP_STATUS_XGXSSTATUS1_SGMII_MODE_BITS                      1
#define GP_STATUS_XGXSSTATUS1_SGMII_MODE_SHIFT                     10

/* GP_Status :: xgxsStatus1 :: link10g [09:09] */
#define GP_STATUS_XGXSSTATUS1_LINK10G_MASK                         0x0200
#define GP_STATUS_XGXSSTATUS1_LINK10G_ALIGN                        0
#define GP_STATUS_XGXSSTATUS1_LINK10G_BITS                         1
#define GP_STATUS_XGXSSTATUS1_LINK10G_SHIFT                        9

/* GP_Status :: xgxsStatus1 :: linkstat [08:08] */
#define GP_STATUS_XGXSSTATUS1_LINKSTAT_MASK                        0x0100
#define GP_STATUS_XGXSSTATUS1_LINKSTAT_ALIGN                       0
#define GP_STATUS_XGXSSTATUS1_LINKSTAT_BITS                        1
#define GP_STATUS_XGXSSTATUS1_LINKSTAT_SHIFT                       8

/* GP_Status :: xgxsStatus1 :: autoneg_complete [07:07] */
#define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_MASK                0x0080
#define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_ALIGN               0
#define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_BITS                1
#define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_SHIFT               7

/* GP_Status :: xgxsStatus1 :: reserved0 [06:06] */
#define GP_STATUS_XGXSSTATUS1_RESERVED0_MASK                       0x0040
#define GP_STATUS_XGXSSTATUS1_RESERVED0_ALIGN                      0
#define GP_STATUS_XGXSSTATUS1_RESERVED0_BITS                       1
#define GP_STATUS_XGXSSTATUS1_RESERVED0_SHIFT                      6

/* GP_Status :: xgxsStatus1 :: pll_mode_afe [05:04] */
#define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_MASK                    0x0030
#define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_ALIGN                   0
#define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_BITS                    2
#define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_SHIFT                   4

/* GP_Status :: xgxsStatus1 :: actual_speed_ln0 [03:00] */
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_MASK                0x000f
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_ALIGN               0
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_BITS                4
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_SHIFT               0
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10M              0
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_100M             1
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_1G               2
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_2p5G             3
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_5G_X4            4
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_6G_X4            5
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_HiG          6
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_CX4          7
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_12G_HiG          8
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_12p5G_X4         9
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_13G_X4           10
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_15G_X4           11
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_16G_X4           12
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_1G_KX            13
#define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_KX4          14


/****************************************************************************
 * GP_Status :: xgxsStatus2
 ***************************************************************************/
/* GP_Status :: xgxsStatus2 :: gpwrdwn_rx [15:12] */
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_MASK                      0xf000
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_ALIGN                     0
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_BITS                      4
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_SHIFT                     12

/* GP_Status :: xgxsStatus2 :: gpwrdwn_tx [11:08] */
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_MASK                      0x0f00
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_ALIGN                     0
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_BITS                      4
#define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_SHIFT                     8

/* GP_Status :: xgxsStatus2 :: freq_sel_rx [07:04] */
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_MASK                     0x00f0
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_ALIGN                    0
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_BITS                     4
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_SHIFT                    4

/* GP_Status :: xgxsStatus2 :: freq_sel_tx [03:00] */
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_MASK                     0x000f
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_ALIGN                    0
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_BITS                     4
#define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_SHIFT                    0


/****************************************************************************
 * GP_Status :: Status1000X1
 ***************************************************************************/
/* GP_Status :: Status1000X1 :: txfifo_err_detected [15:15] */
#define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK            0x8000
#define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN           0
#define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS            1
#define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT           15

/* GP_Status :: Status1000X1 :: rxfifo_err_detected [14:14] */
#define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK            0x4000
#define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN           0
#define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS            1
#define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT           14

/* GP_Status :: Status1000X1 :: false_carrier_detected [13:13] */
#define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK         0x2000
#define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN        0
#define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS         1
#define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT        13

/* GP_Status :: Status1000X1 :: crc_err_detected [12:12] */
#define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_MASK               0x1000
#define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_ALIGN              0
#define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_BITS               1
#define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_SHIFT              12

/* GP_Status :: Status1000X1 :: tx_err_detected [11:11] */
#define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_MASK                0x0800
#define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_ALIGN               0
#define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_BITS                1
#define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_SHIFT               11

/* GP_Status :: Status1000X1 :: rx_err_detected [10:10] */
#define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_MASK                0x0400
#define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_ALIGN               0
#define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_BITS                1
#define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_SHIFT               10

/* GP_Status :: Status1000X1 :: carrier_extend_err_detected [09:09] */
#define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK    0x0200
#define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN   0
#define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS    1
#define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT   9

/* GP_Status :: Status1000X1 :: early_end_extension_detected [08:08] */
#define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK   0x0100
#define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN  0
#define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS   1
#define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT  8

/* GP_Status :: Status1000X1 :: link_status_change [07:07] */
#define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_MASK             0x0080
#define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN            0
#define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_BITS             1
#define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT            7

/* GP_Status :: Status1000X1 :: pause_resolution_rxside [06:06] */
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK        0x0040
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN       0
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS        1
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT       6

/* GP_Status :: Status1000X1 :: pause_resolution_txside [05:05] */
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK        0x0020
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN       0
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS        1
#define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT       5

/* GP_Status :: Status1000X1 :: speed_status [04:03] */
#define GP_STATUS_STATUS1000X1_SPEED_STATUS_MASK                   0x0018
#define GP_STATUS_STATUS1000X1_SPEED_STATUS_ALIGN                  0
#define GP_STATUS_STATUS1000X1_SPEED_STATUS_BITS                   2
#define GP_STATUS_STATUS1000X1_SPEED_STATUS_SHIFT                  3

/* GP_Status :: Status1000X1 :: duplex_status [02:02] */
#define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_MASK                  0x0004
#define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_ALIGN                 0
#define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_BITS                  1
#define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_SHIFT                 2

/* GP_Status :: Status1000X1 :: link_status [01:01] */
#define GP_STATUS_STATUS1000X1_LINK_STATUS_MASK                    0x0002
#define GP_STATUS_STATUS1000X1_LINK_STATUS_ALIGN                   0
#define GP_STATUS_STATUS1000X1_LINK_STATUS_BITS                    1
#define GP_STATUS_STATUS1000X1_LINK_STATUS_SHIFT                   1

/* GP_Status :: Status1000X1 :: sgmii_mode [00:00] */
#define GP_STATUS_STATUS1000X1_SGMII_MODE_MASK                     0x0001
#define GP_STATUS_STATUS1000X1_SGMII_MODE_ALIGN                    0
#define GP_STATUS_STATUS1000X1_SGMII_MODE_BITS                     1
#define GP_STATUS_STATUS1000X1_SGMII_MODE_SHIFT                    0


/****************************************************************************
 * GP_Status :: Status1000X2
 ***************************************************************************/
/* GP_Status :: Status1000X2 :: sgmii_mode_change [15:15] */
#define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_MASK              0x8000
#define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN             0
#define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_BITS              1
#define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT             15

/* GP_Status :: Status1000X2 :: consistency_mismatch [14:14] */
#define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_MASK           0x4000
#define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN          0
#define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_BITS           1
#define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT          14

/* GP_Status :: Status1000X2 :: autoneg_resolution_err [13:13] */
#define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK         0x2000
#define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN        0
#define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS         1
#define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT        13

/* GP_Status :: Status1000X2 :: sgmii_selector_mismatch [12:12] */
#define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK        0x1000
#define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN       0
#define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS        1
#define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT       12

/* GP_Status :: Status1000X2 :: sync_status_fail [11:11] */
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_MASK               0x0800
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN              0
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_BITS               1
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT              11

/* GP_Status :: Status1000X2 :: sync_status_ok [10:10] */
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_MASK                 0x0400
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_ALIGN                0
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_BITS                 1
#define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_SHIFT                10

/* GP_Status :: Status1000X2 :: rudi_c [09:09] */
#define GP_STATUS_STATUS1000X2_RUDI_C_MASK                         0x0200
#define GP_STATUS_STATUS1000X2_RUDI_C_ALIGN                        0
#define GP_STATUS_STATUS1000X2_RUDI_C_BITS                         1
#define GP_STATUS_STATUS1000X2_RUDI_C_SHIFT                        9

/* GP_Status :: Status1000X2 :: rudi_I [08:08] */
#define GP_STATUS_STATUS1000X2_RUDI_I_MASK                         0x0100
#define GP_STATUS_STATUS1000X2_RUDI_I_ALIGN                        0
#define GP_STATUS_STATUS1000X2_RUDI_I_BITS                         1
#define GP_STATUS_STATUS1000X2_RUDI_I_SHIFT                        8

/* GP_Status :: Status1000X2 :: rudi_invalid [07:07] */
#define GP_STATUS_STATUS1000X2_RUDI_INVALID_MASK                   0x0080
#define GP_STATUS_STATUS1000X2_RUDI_INVALID_ALIGN                  0
#define GP_STATUS_STATUS1000X2_RUDI_INVALID_BITS                   1
#define GP_STATUS_STATUS1000X2_RUDI_INVALID_SHIFT                  7

/* GP_Status :: Status1000X2 :: linkDown_syncLoss [06:06] */
#define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK              0x0040
#define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN             0
#define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS              1
#define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT             6

/* GP_Status :: Status1000X2 :: idle_detect_state [05:05] */
#define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_MASK              0x0020
#define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_ALIGN             0
#define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_BITS              1
#define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_SHIFT             5

/* GP_Status :: Status1000X2 :: complete_acknowledge_state [04:04] */
#define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK     0x0010
#define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN    0
#define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS     1
#define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT    4

/* GP_Status :: Status1000X2 :: acknowledge_detect_state [03:03] */
#define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK       0x0008
#define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN      0
#define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS       1
#define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT      3

/* GP_Status :: Status1000X2 :: ability_detect_state [02:02] */
#define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_MASK           0x0004
#define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN          0
#define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_BITS           1
#define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT          2

/* union - case anError [01:01] */
/* GP_Status :: Status1000X2 :: an_error_state [01:01] */
#define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK         0x0002
#define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN        0
#define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS         1
#define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT        1


/* union - case anDisableLink [01:01] */
/* GP_Status :: Status1000X2 :: an_disable_link_ok_state [01:01] */
#define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002
#define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0
#define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1
#define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1


/* GP_Status :: Status1000X2 :: an_enable_state [00:00] */
#define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_MASK                0x0001
#define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_ALIGN               0
#define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_BITS                1
#define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_SHIFT               0


/****************************************************************************
 * GP_Status :: Status1000X3
 ***************************************************************************/
/* GP_Status :: Status1000X3 :: reserved0 [15:13] */
#define GP_STATUS_STATUS1000X3_RESERVED0_MASK                      0xe000
#define GP_STATUS_STATUS1000X3_RESERVED0_ALIGN                     0
#define GP_STATUS_STATUS1000X3_RESERVED0_BITS                      3
#define GP_STATUS_STATUS1000X3_RESERVED0_SHIFT                     13

/* GP_Status :: Status1000X3 :: pd_park_an [12:12] */
#define GP_STATUS_STATUS1000X3_PD_PARK_AN_MASK                     0x1000
#define GP_STATUS_STATUS1000X3_PD_PARK_AN_ALIGN                    0
#define GP_STATUS_STATUS1000X3_PD_PARK_AN_BITS                     1
#define GP_STATUS_STATUS1000X3_PD_PARK_AN_SHIFT                    12

/* GP_Status :: Status1000X3 :: remotePhy_autosel [11:11] */
#define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK              0x0800
#define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN             0
#define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS              1
#define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT             11

/* GP_Status :: Status1000X3 :: latch_linkdown [10:10] */
#define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_MASK                 0x0400
#define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_ALIGN                0
#define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_BITS                 1
#define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_SHIFT                10

/* GP_Status :: Status1000X3 :: sd_filter [09:09] */
#define GP_STATUS_STATUS1000X3_SD_FILTER_MASK                      0x0200
#define GP_STATUS_STATUS1000X3_SD_FILTER_ALIGN                     0
#define GP_STATUS_STATUS1000X3_SD_FILTER_BITS                      1
#define GP_STATUS_STATUS1000X3_SD_FILTER_SHIFT                     9

/* GP_Status :: Status1000X3 :: sd_mux [08:08] */
#define GP_STATUS_STATUS1000X3_SD_MUX_MASK                         0x0100
#define GP_STATUS_STATUS1000X3_SD_MUX_ALIGN                        0
#define GP_STATUS_STATUS1000X3_SD_MUX_BITS                         1
#define GP_STATUS_STATUS1000X3_SD_MUX_SHIFT                        8

/* GP_Status :: Status1000X3 :: sd_filter_chg [07:07] */
#define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_MASK                  0x0080
#define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_ALIGN                 0
#define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_BITS                  1
#define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_SHIFT                 7

/* GP_Status :: Status1000X3 :: reserved1 [06:00] */
#define GP_STATUS_STATUS1000X3_RESERVED1_MASK                      0x007f
#define GP_STATUS_STATUS1000X3_RESERVED1_ALIGN                     0
#define GP_STATUS_STATUS1000X3_RESERVED1_BITS                      7
#define GP_STATUS_STATUS1000X3_RESERVED1_SHIFT                     0


/****************************************************************************
 * GP_Status :: TPOUT_1
 ***************************************************************************/
/* GP_Status :: TPOUT_1 :: tpout1 [15:00] */
#define GP_STATUS_TPOUT_1_TPOUT1_MASK                              0xffff
#define GP_STATUS_TPOUT_1_TPOUT1_ALIGN                             0
#define GP_STATUS_TPOUT_1_TPOUT1_BITS                              16
#define GP_STATUS_TPOUT_1_TPOUT1_SHIFT                             0


/****************************************************************************
 * GP_Status :: TPOUT_2
 ***************************************************************************/
/* GP_Status :: TPOUT_2 :: tpout2 [15:00] */
#define GP_STATUS_TPOUT_2_TPOUT2_MASK                              0xffff
#define GP_STATUS_TPOUT_2_TPOUT2_ALIGN                             0
#define GP_STATUS_TPOUT_2_TPOUT2_BITS                              16
#define GP_STATUS_TPOUT_2_TPOUT2_SHIFT                             0


/****************************************************************************
 * GP_Status :: xgxsStatus3
 ***************************************************************************/
/* GP_Status :: xgxsStatus3 :: link [15:15] */
#define GP_STATUS_XGXSSTATUS3_LINK_MASK                            0x8000
#define GP_STATUS_XGXSSTATUS3_LINK_ALIGN                           0
#define GP_STATUS_XGXSSTATUS3_LINK_BITS                            1
#define GP_STATUS_XGXSSTATUS3_LINK_SHIFT                           15

/* GP_Status :: xgxsStatus3 :: link_latchdown [14:14] */
#define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_MASK                  0x4000
#define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_ALIGN                 0
#define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_BITS                  1
#define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_SHIFT                 14

/* GP_Status :: xgxsStatus3 :: latch_linkdown_10g_o [13:13] */
#define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_MASK            0x2000
#define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_ALIGN           0
#define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_BITS            1
#define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_SHIFT           13

/* GP_Status :: xgxsStatus3 :: pd_park_an [12:12] */
#define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_MASK                      0x1000
#define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_ALIGN                     0
#define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_BITS                      1
#define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_SHIFT                     12

/* GP_Status :: xgxsStatus3 :: gpwrdwn_pll [11:11] */
#define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_MASK                     0x0800
#define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_ALIGN                    0
#define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_BITS                     1
#define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_SHIFT                    11

/* GP_Status :: xgxsStatus3 :: hcd_over_1g [10:00] */
#define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_MASK                     0x07ff
#define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_ALIGN                    0
#define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_BITS                     11
#define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_SHIFT                    0


/****************************************************************************
 * GP_Status :: x2500Status1
 ***************************************************************************/
/* GP_Status :: x2500Status1 :: hcd_over_1g_or [15:15] */
#define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_MASK                 0x8000
#define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_ALIGN                0
#define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_BITS                 1
#define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_SHIFT                15

/* GP_Status :: x2500Status1 :: latch_hcd_over_1g [14:14] */
#define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_MASK              0x4000
#define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_ALIGN             0
#define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_BITS              1
#define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_SHIFT             14

/* GP_Status :: x2500Status1 :: latchmdio [13:13] */
#define GP_STATUS_X2500STATUS1_LATCHMDIO_MASK                      0x2000
#define GP_STATUS_X2500STATUS1_LATCHMDIO_ALIGN                     0
#define GP_STATUS_X2500STATUS1_LATCHMDIO_BITS                      1
#define GP_STATUS_X2500STATUS1_LATCHMDIO_SHIFT                     13

/* GP_Status :: x2500Status1 :: s_bc_reg_rst [12:12] */
#define GP_STATUS_X2500STATUS1_S_BC_REG_RST_MASK                   0x1000
#define GP_STATUS_X2500STATUS1_S_BC_REG_RST_ALIGN                  0
#define GP_STATUS_X2500STATUS1_S_BC_REG_RST_BITS                   1
#define GP_STATUS_X2500STATUS1_S_BC_REG_RST_SHIFT                  12

/* GP_Status :: x2500Status1 :: s_wait2res [11:11] */
#define GP_STATUS_X2500STATUS1_S_WAIT2RES_MASK                     0x0800
#define GP_STATUS_X2500STATUS1_S_WAIT2RES_ALIGN                    0
#define GP_STATUS_X2500STATUS1_S_WAIT2RES_BITS                     1
#define GP_STATUS_X2500STATUS1_S_WAIT2RES_SHIFT                    11

/* GP_Status :: x2500Status1 :: s_wait30ms [10:10] */
#define GP_STATUS_X2500STATUS1_S_WAIT30MS_MASK                     0x0400
#define GP_STATUS_X2500STATUS1_S_WAIT30MS_ALIGN                    0
#define GP_STATUS_X2500STATUS1_S_WAIT30MS_BITS                     1
#define GP_STATUS_X2500STATUS1_S_WAIT30MS_SHIFT                    10

/* GP_Status :: x2500Status1 :: s_clockswit [09:09] */
#define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_MASK                    0x0200
#define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_ALIGN                   0
#define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_BITS                    1
#define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_SHIFT                   9

/* GP_Status :: x2500Status1 :: s_pllswit [08:08] */
#define GP_STATUS_X2500STATUS1_S_PLLSWIT_MASK                      0x0100
#define GP_STATUS_X2500STATUS1_S_PLLSWIT_ALIGN                     0
#define GP_STATUS_X2500STATUS1_S_PLLSWIT_BITS                      1
#define GP_STATUS_X2500STATUS1_S_PLLSWIT_SHIFT                     8

/* GP_Status :: x2500Status1 :: s_wait4link [07:07] */
#define GP_STATUS_X2500STATUS1_S_WAIT4LINK_MASK                    0x0080
#define GP_STATUS_X2500STATUS1_S_WAIT4LINK_ALIGN                   0
#define GP_STATUS_X2500STATUS1_S_WAIT4LINK_BITS                    1
#define GP_STATUS_X2500STATUS1_S_WAIT4LINK_SHIFT                   7

/* GP_Status :: x2500Status1 :: s_complete [06:06] */
#define GP_STATUS_X2500STATUS1_S_COMPLETE_MASK                     0x0040
#define GP_STATUS_X2500STATUS1_S_COMPLETE_ALIGN                    0
#define GP_STATUS_X2500STATUS1_S_COMPLETE_BITS                     1
#define GP_STATUS_X2500STATUS1_S_COMPLETE_SHIFT                    6

/* GP_Status :: x2500Status1 :: s_lostlink [05:05] */
#define GP_STATUS_X2500STATUS1_S_LOSTLINK_MASK                     0x0020
#define GP_STATUS_X2500STATUS1_S_LOSTLINK_ALIGN                    0
#define GP_STATUS_X2500STATUS1_S_LOSTLINK_BITS                     1
#define GP_STATUS_X2500STATUS1_S_LOSTLINK_SHIFT                    5

/* GP_Status :: x2500Status1 :: s_dead [04:04] */
#define GP_STATUS_X2500STATUS1_S_DEAD_MASK                         0x0010
#define GP_STATUS_X2500STATUS1_S_DEAD_ALIGN                        0
#define GP_STATUS_X2500STATUS1_S_DEAD_BITS                         1
#define GP_STATUS_X2500STATUS1_S_DEAD_SHIFT                        4

/* GP_Status :: x2500Status1 :: fail_cnt [03:00] */
#define GP_STATUS_X2500STATUS1_FAIL_CNT_MASK                       0x000f
#define GP_STATUS_X2500STATUS1_FAIL_CNT_ALIGN                      0
#define GP_STATUS_X2500STATUS1_FAIL_CNT_BITS                       4
#define GP_STATUS_X2500STATUS1_FAIL_CNT_SHIFT                      0


/****************************************************************************
 * GP_Status :: topANStatus1
 ***************************************************************************/
/* GP_Status :: topANStatus1 :: reserved0 [15:14] */
#define GP_STATUS_TOPANSTATUS1_RESERVED0_MASK                      0xc000
#define GP_STATUS_TOPANSTATUS1_RESERVED0_ALIGN                     0
#define GP_STATUS_TOPANSTATUS1_RESERVED0_BITS                      2
#define GP_STATUS_TOPANSTATUS1_RESERVED0_SHIFT                     14

/* GP_Status :: topANStatus1 :: actual_speed [13:08] */
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_MASK                   0x3f00
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_ALIGN                  0
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_BITS                   6
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_SHIFT                  8
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_10M                 0
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_100M                1
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_1G                  2
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_2p5G                3
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_5G_X4               4
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_6G_X4               5
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_HiG             6
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_CX4             7
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_12G_HiG             8
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_12p5G_X4            9
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_13G_X4              10
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_15G_X4              11
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_16G_X4              12
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_5G                  16
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_6p4G                17
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_20G_X4              18
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_21G_X4              19
#define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_25G_X4              20

/* GP_Status :: topANStatus1 :: pause_resolution_rxside [07:07] */
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_MASK        0x0080
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_ALIGN       0
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_BITS        1
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_SHIFT       7

/* GP_Status :: topANStatus1 :: pause_resolution_txside [06:06] */
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_MASK        0x0040
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_ALIGN       0
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_BITS        1
#define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_SHIFT       6

/* GP_Status :: topANStatus1 :: cl73_lp_np_BAM_able [05:05] */
#define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_MASK            0x0020
#define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_ALIGN           0
#define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_BITS            1
#define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_SHIFT           5

/* GP_Status :: topANStatus1 :: cl73_mr_lp_autoneg_able [04:04] */
#define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_MASK        0x0010
#define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_ALIGN       0
#define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_BITS        1
#define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_SHIFT       4

/* GP_Status :: topANStatus1 :: duplex_status [03:03] */
#define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_MASK                  0x0008
#define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_ALIGN                 0
#define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_BITS                  1
#define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_SHIFT                 3

/* GP_Status :: topANStatus1 :: link_status [02:02] */
#define GP_STATUS_TOPANSTATUS1_LINK_STATUS_MASK                    0x0004
#define GP_STATUS_TOPANSTATUS1_LINK_STATUS_ALIGN                   0
#define GP_STATUS_TOPANSTATUS1_LINK_STATUS_BITS                    1
#define GP_STATUS_TOPANSTATUS1_LINK_STATUS_SHIFT                   2

/* GP_Status :: topANStatus1 :: cl37_autoneg_complete [01:01] */
#define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_MASK          0x0002
#define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_ALIGN         0
#define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_BITS          1
#define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_SHIFT         1

/* GP_Status :: topANStatus1 :: cl73_autoneg_complete [00:00] */
#define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_MASK          0x0001
#define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_ALIGN         0
#define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_BITS          1
#define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_SHIFT         0


/****************************************************************************
 * GP_Status :: LP_UP1
 ***************************************************************************/
/* GP_Status :: LP_UP1 :: reserved0 [15:11] */
#define GP_STATUS_LP_UP1_RESERVED0_MASK                            0xf800
#define GP_STATUS_LP_UP1_RESERVED0_ALIGN                           0
#define GP_STATUS_LP_UP1_RESERVED0_BITS                            5
#define GP_STATUS_LP_UP1_RESERVED0_SHIFT                           11

/* GP_Status :: LP_UP1 :: dataRate_20GX4 [10:10] */
#define GP_STATUS_LP_UP1_DATARATE_20GX4_MASK                       0x0400
#define GP_STATUS_LP_UP1_DATARATE_20GX4_ALIGN                      0
#define GP_STATUS_LP_UP1_DATARATE_20GX4_BITS                       1
#define GP_STATUS_LP_UP1_DATARATE_20GX4_SHIFT                      10

/* GP_Status :: LP_UP1 :: dataRate_16GX4 [09:09] */
#define GP_STATUS_LP_UP1_DATARATE_16GX4_MASK                       0x0200
#define GP_STATUS_LP_UP1_DATARATE_16GX4_ALIGN                      0
#define GP_STATUS_LP_UP1_DATARATE_16GX4_BITS                       1
#define GP_STATUS_LP_UP1_DATARATE_16GX4_SHIFT                      9

/* GP_Status :: LP_UP1 :: dataRate_15GX4 [08:08] */
#define GP_STATUS_LP_UP1_DATARATE_15GX4_MASK                       0x0100
#define GP_STATUS_LP_UP1_DATARATE_15GX4_ALIGN                      0
#define GP_STATUS_LP_UP1_DATARATE_15GX4_BITS                       1
#define GP_STATUS_LP_UP1_DATARATE_15GX4_SHIFT                      8

/* GP_Status :: LP_UP1 :: dataRate_13GX4 [07:07] */
#define GP_STATUS_LP_UP1_DATARATE_13GX4_MASK                       0x0080
#define GP_STATUS_LP_UP1_DATARATE_13GX4_ALIGN                      0
#define GP_STATUS_LP_UP1_DATARATE_13GX4_BITS                       1
#define GP_STATUS_LP_UP1_DATARATE_13GX4_SHIFT                      7

/* GP_Status :: LP_UP1 :: dataRate_12p5GX4 [06:06] */
#define GP_STATUS_LP_UP1_DATARATE_12P5GX4_MASK                     0x0040
#define GP_STATUS_LP_UP1_DATARATE_12P5GX4_ALIGN                    0
#define GP_STATUS_LP_UP1_DATARATE_12P5GX4_BITS                     1
#define GP_STATUS_LP_UP1_DATARATE_12P5GX4_SHIFT                    6

/* GP_Status :: LP_UP1 :: dataRate_12GX4 [05:05] */
#define GP_STATUS_LP_UP1_DATARATE_12GX4_MASK                       0x0020
#define GP_STATUS_LP_UP1_DATARATE_12GX4_ALIGN                      0
#define GP_STATUS_LP_UP1_DATARATE_12GX4_BITS                       1
#define GP_STATUS_LP_UP1_DATARATE_12GX4_SHIFT                      5

/* GP_Status :: LP_UP1 :: dataRate_10GCX4 [04:04] */
#define GP_STATUS_LP_UP1_DATARATE_10GCX4_MASK                      0x0010
#define GP_STATUS_LP_UP1_DATARATE_10GCX4_ALIGN                     0
#define GP_STATUS_LP_UP1_DATARATE_10GCX4_BITS                      1
#define GP_STATUS_LP_UP1_DATARATE_10GCX4_SHIFT                     4

/* GP_Status :: LP_UP1 :: dataRate_10GX4 [03:03] */
#define GP_STATUS_LP_UP1_DATARATE_10GX4_MASK                       0x0008
#define GP_STATUS_LP_UP1_DATARATE_10GX4_ALIGN                      0
#define GP_STATUS_LP_UP1_DATARATE_10GX4_BITS                       1
#define GP_STATUS_LP_UP1_DATARATE_10GX4_SHIFT                      3

/* GP_Status :: LP_UP1 :: dataRate_6GX4 [02:02] */
#define GP_STATUS_LP_UP1_DATARATE_6GX4_MASK                        0x0004
#define GP_STATUS_LP_UP1_DATARATE_6GX4_ALIGN                       0
#define GP_STATUS_LP_UP1_DATARATE_6GX4_BITS                        1
#define GP_STATUS_LP_UP1_DATARATE_6GX4_SHIFT                       2

/* GP_Status :: LP_UP1 :: dataRate_5GX4 [01:01] */
#define GP_STATUS_LP_UP1_DATARATE_5GX4_MASK                        0x0002
#define GP_STATUS_LP_UP1_DATARATE_5GX4_ALIGN                       0
#define GP_STATUS_LP_UP1_DATARATE_5GX4_BITS                        1
#define GP_STATUS_LP_UP1_DATARATE_5GX4_SHIFT                       1

/* GP_Status :: LP_UP1 :: dataRate_2p5GX1 [00:00] */
#define GP_STATUS_LP_UP1_DATARATE_2P5GX1_MASK                      0x0001
#define GP_STATUS_LP_UP1_DATARATE_2P5GX1_ALIGN                     0
#define GP_STATUS_LP_UP1_DATARATE_2P5GX1_BITS                      1
#define GP_STATUS_LP_UP1_DATARATE_2P5GX1_SHIFT                     0


/****************************************************************************
 * GP_Status :: LP_UP2
 ***************************************************************************/
/* GP_Status :: LP_UP2 :: reserved0 [15:11] */
#define GP_STATUS_LP_UP2_RESERVED0_MASK                            0xf800
#define GP_STATUS_LP_UP2_RESERVED0_ALIGN                           0
#define GP_STATUS_LP_UP2_RESERVED0_BITS                            5
#define GP_STATUS_LP_UP2_RESERVED0_SHIFT                           11

/* GP_Status :: LP_UP2 :: valid [10:10] */
#define GP_STATUS_LP_UP2_VALID_MASK                                0x0400
#define GP_STATUS_LP_UP2_VALID_ALIGN                               0
#define GP_STATUS_LP_UP2_VALID_BITS                                1
#define GP_STATUS_LP_UP2_VALID_SHIFT                               10

/* GP_Status :: LP_UP2 :: preemphasis [09:06] */
#define GP_STATUS_LP_UP2_PREEMPHASIS_MASK                          0x03c0
#define GP_STATUS_LP_UP2_PREEMPHASIS_ALIGN                         0
#define GP_STATUS_LP_UP2_PREEMPHASIS_BITS                          4
#define GP_STATUS_LP_UP2_PREEMPHASIS_SHIFT                         6

/* GP_Status :: LP_UP2 :: idriver [05:03] */
#define GP_STATUS_LP_UP2_IDRIVER_MASK                              0x0038
#define GP_STATUS_LP_UP2_IDRIVER_ALIGN                             0
#define GP_STATUS_LP_UP2_IDRIVER_BITS                              3
#define GP_STATUS_LP_UP2_IDRIVER_SHIFT                             3

/* GP_Status :: LP_UP2 :: ipredriver [02:00] */
#define GP_STATUS_LP_UP2_IPREDRIVER_MASK                           0x0007
#define GP_STATUS_LP_UP2_IPREDRIVER_ALIGN                          0
#define GP_STATUS_LP_UP2_IPREDRIVER_BITS                           3
#define GP_STATUS_LP_UP2_IPREDRIVER_SHIFT                          0


/****************************************************************************
 * GP_Status :: LP_UP3
 ***************************************************************************/
/* GP_Status :: LP_UP3 :: reserved0 [15:11] */
#define GP_STATUS_LP_UP3_RESERVED0_MASK                            0xf800
#define GP_STATUS_LP_UP3_RESERVED0_ALIGN                           0
#define GP_STATUS_LP_UP3_RESERVED0_BITS                            5
#define GP_STATUS_LP_UP3_RESERVED0_SHIFT                           11

/* GP_Status :: LP_UP3 :: last [10:10] */
#define GP_STATUS_LP_UP3_LAST_MASK                                 0x0400
#define GP_STATUS_LP_UP3_LAST_ALIGN                                0
#define GP_STATUS_LP_UP3_LAST_BITS                                 1
#define GP_STATUS_LP_UP3_LAST_SHIFT                                10

/* GP_Status :: LP_UP3 :: dataRate_21GX4 [09:09] */
#define GP_STATUS_LP_UP3_DATARATE_21GX4_MASK                       0x0200
#define GP_STATUS_LP_UP3_DATARATE_21GX4_ALIGN                      0
#define GP_STATUS_LP_UP3_DATARATE_21GX4_BITS                       1
#define GP_STATUS_LP_UP3_DATARATE_21GX4_SHIFT                      9

/* GP_Status :: LP_UP3 :: dataRate_25p45GX4 [08:08] */
#define GP_STATUS_LP_UP3_DATARATE_25P45GX4_MASK                    0x0100
#define GP_STATUS_LP_UP3_DATARATE_25P45GX4_ALIGN                   0
#define GP_STATUS_LP_UP3_DATARATE_25P45GX4_BITS                    1
#define GP_STATUS_LP_UP3_DATARATE_25P45GX4_SHIFT                   8

/* GP_Status :: LP_UP3 :: reserved1 [07:02] */
#define GP_STATUS_LP_UP3_RESERVED1_MASK                            0x00fc
#define GP_STATUS_LP_UP3_RESERVED1_ALIGN                           0
#define GP_STATUS_LP_UP3_RESERVED1_BITS                            6
#define GP_STATUS_LP_UP3_RESERVED1_SHIFT                           2

/* GP_Status :: LP_UP3 :: scramble_8B10B [01:01] */
#define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_MASK                       0x0002
#define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_ALIGN                      0
#define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_BITS                       1
#define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_SHIFT                      1

/* GP_Status :: LP_UP3 :: HiGig2 [00:00] */
#define GP_STATUS_LP_UP3_HIGIG2_MASK                               0x0001
#define GP_STATUS_LP_UP3_HIGIG2_ALIGN                              0
#define GP_STATUS_LP_UP3_HIGIG2_BITS                               1
#define GP_STATUS_LP_UP3_HIGIG2_SHIFT                              0


/****************************************************************************
 * Hypercore_USER_AN73_pdet
 ***************************************************************************/
/****************************************************************************
 * AN73_pdet :: parDet10GStatus
 ***************************************************************************/
/* union - case pdStatus0 [15:00] */
/* AN73_pdet :: parDet10GStatus :: pd_link [15:15] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_MASK           0x8000
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_ALIGN          0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_BITS           1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_SHIFT          15

/* AN73_pdet :: parDet10GStatus :: pd_CX4_en [14:14] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_MASK         0x4000
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_ALIGN        0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_BITS         1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_SHIFT        14

/* AN73_pdet :: parDet10GStatus :: pd_lssFaultCount_en [13:13] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_MASK 0x2000
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_ALIGN 0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_BITS 1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_SHIFT 13

/* AN73_pdet :: parDet10GStatus :: pd_tunePll12g [12:12] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_MASK     0x1000
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_ALIGN    0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_BITS     1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_SHIFT    12

/* AN73_pdet :: parDet10GStatus :: pd_tunePll10g [11:11] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_MASK     0x0800
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_ALIGN    0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_BITS     1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_SHIFT    11

/* AN73_pdet :: parDet10GStatus :: pd_txdLaneOff [10:10] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_MASK     0x0400
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_ALIGN    0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_BITS     1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_SHIFT    10

/* AN73_pdet :: parDet10GStatus :: pd_busy [09:09] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_MASK           0x0200
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_ALIGN          0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_BITS           1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_SHIFT          9

/* AN73_pdet :: parDet10GStatus :: pd_park_an [08:08] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_MASK        0x0100
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_ALIGN       0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_BITS        1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_SHIFT       8

/* AN73_pdet :: parDet10GStatus :: pd_lssFaultCount [07:04] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_MASK  0x00f0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_ALIGN 0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_BITS  4
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_SHIFT 4

/* AN73_pdet :: parDet10GStatus :: rxSeqDone [03:00] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_MASK         0x000f
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_ALIGN        0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_BITS         4
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_SHIFT        0


/* union - case pdStatus1 [15:00] */
/* AN73_pdet :: parDet10GStatus :: reserved0 [15:09] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_MASK         0xfe00
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_ALIGN        0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_BITS         7
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_SHIFT        9

/* AN73_pdet :: parDet10GStatus :: fail_lh [08:08] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_MASK           0x0100
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_ALIGN          0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_BITS           1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_SHIFT          8

/* AN73_pdet :: parDet10GStatus :: complete_lh [07:07] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_MASK       0x0080
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_ALIGN      0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_BITS       1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_SHIFT      7

/* AN73_pdet :: parDet10GStatus :: link12gretry_lh [06:06] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_MASK   0x0040
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_ALIGN  0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_BITS   1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_SHIFT  6

/* AN73_pdet :: parDet10GStatus :: wait4link12g_lh [05:05] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_MASK   0x0020
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_ALIGN  0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_BITS   1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_SHIFT  5

/* AN73_pdet :: parDet10GStatus :: samplefault_lh [04:04] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_MASK    0x0010
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_ALIGN   0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_BITS    1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_SHIFT   4

/* AN73_pdet :: parDet10GStatus :: link10gretry_lh [03:03] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_MASK   0x0008
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_ALIGN  0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_BITS   1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_SHIFT  3

/* AN73_pdet :: parDet10GStatus :: wait4link10g_lh [02:02] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_MASK   0x0004
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_ALIGN  0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_BITS   1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_SHIFT  2

/* AN73_pdet :: parDet10GStatus :: wait4sigdet_lh [01:01] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_MASK    0x0002
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_ALIGN   0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_BITS    1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_SHIFT   1

/* AN73_pdet :: parDet10GStatus :: wait4lock_lh [00:00] */
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_MASK      0x0001
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_ALIGN     0
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_BITS      1
#define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_SHIFT     0



/****************************************************************************
 * AN73_pdet :: parDet10GControl
 ***************************************************************************/
/* AN73_pdet :: parDet10GControl :: force_parDet10g_en [15:15] */
#define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_MASK         0x8000
#define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_ALIGN        0
#define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_BITS         1
#define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_SHIFT        15

/* AN73_pdet :: parDet10GControl :: pd_cx4_init [14:14] */
#define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_MASK                0x4000
#define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_ALIGN               0
#define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_BITS                1
#define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_SHIFT               14

/* AN73_pdet :: parDet10GControl :: pd_sw_overide [13:13] */
#define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_MASK              0x2000
#define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_ALIGN             0
#define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_BITS              1
#define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_SHIFT             13

/* AN73_pdet :: parDet10GControl :: pd_sw_busy_an [12:12] */
#define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_MASK              0x1000
#define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_ALIGN             0
#define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_BITS              1
#define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_SHIFT             12

/* AN73_pdet :: parDet10GControl :: pd_sw_CX4_en [11:11] */
#define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_MASK               0x0800
#define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_ALIGN              0
#define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_BITS               1
#define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_SHIFT              11

/* AN73_pdet :: parDet10GControl :: pd_sw_tunePll12g [10:10] */
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_MASK           0x0400
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_ALIGN          0
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_BITS           1
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_SHIFT          10

/* AN73_pdet :: parDet10GControl :: pd_sw_tunePll10g [09:09] */
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_MASK           0x0200
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_ALIGN          0
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_BITS           1
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_SHIFT          9

/* AN73_pdet :: parDet10GControl :: pd_sw_lssFaultCount_en [08:08] */
#define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_MASK     0x0100
#define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_ALIGN    0
#define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_BITS     1
#define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_SHIFT    8

/* AN73_pdet :: parDet10GControl :: pd_sw_txdOff [07:07] */
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_MASK               0x0080
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_ALIGN              0
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_BITS               1
#define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_SHIFT              7

/* AN73_pdet :: parDet10GControl :: pd_12g_txdOn_disable [06:06] */
#define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_MASK       0x0040
#define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_ALIGN      0
#define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_BITS       1
#define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_SHIFT      6

/* AN73_pdet :: parDet10GControl :: pd_12g_disable [05:05] */
#define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_MASK             0x0020
#define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_ALIGN            0
#define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_BITS             1
#define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_SHIFT            5

/* AN73_pdet :: parDet10GControl :: pd_10g_txdOn_disable [04:04] */
#define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_MASK       0x0010
#define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_ALIGN      0
#define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_BITS       1
#define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_SHIFT      4

/* AN73_pdet :: parDet10GControl :: pd_10g_disable [03:03] */
#define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_MASK             0x0008
#define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_ALIGN            0
#define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_BITS             1
#define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_SHIFT            3

/* AN73_pdet :: parDet10GControl :: pd_stat_sel [02:02] */
#define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_MASK                0x0004
#define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_ALIGN               0
#define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_BITS                1
#define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_SHIFT               2

/* AN73_pdet :: parDet10GControl :: pd_fast_timer_en [01:01] */
#define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_MASK           0x0002
#define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_ALIGN          0
#define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_BITS           1
#define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_SHIFT          1

/* AN73_pdet :: parDet10GControl :: parDet10g_en [00:00] */
#define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_MASK               0x0001
#define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_ALIGN              0
#define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_BITS               1
#define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_SHIFT              0


/****************************************************************************
 * AN73_pdet :: parDet10GSigDet
 ***************************************************************************/
/* AN73_pdet :: parDet10GSigDet :: pd_sd_count [15:00] */
#define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_MASK                 0xffff
#define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_ALIGN                0
#define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_BITS                 16
#define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_SHIFT                0


/****************************************************************************
 * AN73_pdet :: parDet10GLink
 ***************************************************************************/
/* AN73_pdet :: parDet10GLink :: pd_link_count [15:00] */
#define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_MASK                 0xffff
#define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_ALIGN                0
#define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_BITS                 16
#define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_SHIFT                0


/****************************************************************************
 * AN73_pdet :: parDet10GLostLink
 ***************************************************************************/
/* AN73_pdet :: parDet10GLostLink :: pd_lostlink_count [15:00] */
#define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_MASK         0xffff
#define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_ALIGN        0
#define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_BITS         16
#define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_SHIFT        0


/****************************************************************************
 * AN73_pdet :: cl73Control1
 ***************************************************************************/
/* AN73_pdet :: cl73Control1 :: reserved0 [15:08] */
#define AN73_PDET_CL73CONTROL1_RESERVED0_MASK                      0xff00
#define AN73_PDET_CL73CONTROL1_RESERVED0_ALIGN                     0
#define AN73_PDET_CL73CONTROL1_RESERVED0_BITS                      8
#define AN73_PDET_CL73CONTROL1_RESERVED0_SHIFT                     8

/* AN73_pdet :: cl73Control1 :: cl73_internal_10us_timer_val [07:00] */
#define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_MASK   0x00ff
#define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_ALIGN  0
#define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_BITS   8
#define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_SHIFT  0


/****************************************************************************
 * AN73_pdet :: cl73Control2
 ***************************************************************************/
/* AN73_pdet :: cl73Control2 :: reserved0 [15:13] */
#define AN73_PDET_CL73CONTROL2_RESERVED0_MASK                      0xe000
#define AN73_PDET_CL73CONTROL2_RESERVED0_ALIGN                     0
#define AN73_PDET_CL73CONTROL2_RESERVED0_BITS                      3
#define AN73_PDET_CL73CONTROL2_RESERVED0_SHIFT                     13

/* AN73_pdet :: cl73Control2 :: cl73_link_fail_inhibit_timer_val [12:00] */
#define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_MASK 0x1fff
#define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_ALIGN 0
#define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_BITS 13
#define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_SHIFT 0


/****************************************************************************
 * AN73_pdet :: cl73Control3
 ***************************************************************************/
/* AN73_pdet :: cl73Control3 :: reserved0 [15:13] */
#define AN73_PDET_CL73CONTROL3_RESERVED0_MASK                      0xe000
#define AN73_PDET_CL73CONTROL3_RESERVED0_ALIGN                     0
#define AN73_PDET_CL73CONTROL3_RESERVED0_BITS                      3
#define AN73_PDET_CL73CONTROL3_RESERVED0_SHIFT                     13

/* AN73_pdet :: cl73Control3 :: cl73_an_wait_timer_val [12:00] */
#define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_MASK         0x1fff
#define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_ALIGN        0
#define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_BITS         13
#define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_SHIFT        0


/****************************************************************************
 * AN73_pdet :: cl73Control4
 ***************************************************************************/
/* AN73_pdet :: cl73Control4 :: reserved0 [15:13] */
#define AN73_PDET_CL73CONTROL4_RESERVED0_MASK                      0xe000
#define AN73_PDET_CL73CONTROL4_RESERVED0_ALIGN                     0
#define AN73_PDET_CL73CONTROL4_RESERVED0_BITS                      3
#define AN73_PDET_CL73CONTROL4_RESERVED0_SHIFT                     13

/* AN73_pdet :: cl73Control4 :: cl73_break_link_timer_val [12:00] */
#define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_MASK      0x1fff
#define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_ALIGN     0
#define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_BITS      13
#define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_SHIFT     0


/****************************************************************************
 * AN73_pdet :: cl73Control5
 ***************************************************************************/
/* AN73_pdet :: cl73Control5 :: reserved0 [15:13] */
#define AN73_PDET_CL73CONTROL5_RESERVED0_MASK                      0xe000
#define AN73_PDET_CL73CONTROL5_RESERVED0_ALIGN                     0
#define AN73_PDET_CL73CONTROL5_RESERVED0_BITS                      3
#define AN73_PDET_CL73CONTROL5_RESERVED0_SHIFT                     13

/* AN73_pdet :: cl73Control5 :: cl73_link_fail_inhibit_timer_bam_val [12:00] */
#define AN73_PDET_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_MASK 0x1fff
#define AN73_PDET_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_ALIGN 0
#define AN73_PDET_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_BITS 13
#define AN73_PDET_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_SHIFT 0


/****************************************************************************
 * AN73_pdet :: cl73Control6
 ***************************************************************************/
/* AN73_pdet :: cl73Control6 :: reserved0 [15:13] */
#define AN73_PDET_CL73CONTROL6_RESERVED0_MASK                      0xe000
#define AN73_PDET_CL73CONTROL6_RESERVED0_ALIGN                     0
#define AN73_PDET_CL73CONTROL6_RESERVED0_BITS                      3
#define AN73_PDET_CL73CONTROL6_RESERVED0_SHIFT                     13

/* AN73_pdet :: cl73Control6 :: cl73_ignore_link_timer_val [12:00] */
#define AN73_PDET_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_MASK     0x1fff
#define AN73_PDET_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_ALIGN    0
#define AN73_PDET_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_BITS     13
#define AN73_PDET_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_SHIFT    0


/****************************************************************************
 * AN73_pdet :: cl73DmeTmrs
 ***************************************************************************/
/* AN73_pdet :: cl73DmeTmrs :: cl73_dme_page_test_max_cnt_val [15:08] */
#define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_MASK  0xff00
#define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_ALIGN 0
#define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_BITS  8
#define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_SHIFT 8

/* AN73_pdet :: cl73DmeTmrs :: cl73_dme_page_test_min_cnt_val [07:00] */
#define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_MASK  0x00ff
#define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_ALIGN 0
#define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_BITS  8
#define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_SHIFT 0


/****************************************************************************
 * AN73_pdet :: xgxsStatus4
 ***************************************************************************/
/* AN73_pdet :: xgxsStatus4 :: reserved0 [15:15] */
#define AN73_PDET_XGXSSTATUS4_RESERVED0_MASK                       0x8000
#define AN73_PDET_XGXSSTATUS4_RESERVED0_ALIGN                      0
#define AN73_PDET_XGXSSTATUS4_RESERVED0_BITS                       1
#define AN73_PDET_XGXSSTATUS4_RESERVED0_SHIFT                      15

/* AN73_pdet :: xgxsStatus4 :: sgmii_mode [14:14] */
#define AN73_PDET_XGXSSTATUS4_SGMII_MODE_MASK                      0x4000
#define AN73_PDET_XGXSSTATUS4_SGMII_MODE_ALIGN                     0
#define AN73_PDET_XGXSSTATUS4_SGMII_MODE_BITS                      1
#define AN73_PDET_XGXSSTATUS4_SGMII_MODE_SHIFT                     14

/* AN73_pdet :: xgxsStatus4 :: link10g [13:13] */
#define AN73_PDET_XGXSSTATUS4_LINK10G_MASK                         0x2000
#define AN73_PDET_XGXSSTATUS4_LINK10G_ALIGN                        0
#define AN73_PDET_XGXSSTATUS4_LINK10G_BITS                         1
#define AN73_PDET_XGXSSTATUS4_LINK10G_SHIFT                        13

/* AN73_pdet :: xgxsStatus4 :: link_status [12:12] */
#define AN73_PDET_XGXSSTATUS4_LINK_STATUS_MASK                     0x1000
#define AN73_PDET_XGXSSTATUS4_LINK_STATUS_ALIGN                    0
#define AN73_PDET_XGXSSTATUS4_LINK_STATUS_BITS                     1
#define AN73_PDET_XGXSSTATUS4_LINK_STATUS_SHIFT                    12

/* AN73_pdet :: xgxsStatus4 :: pll_mode_afe [11:08] */
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_MASK                    0x0f00
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_ALIGN                   0
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_BITS                    4
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_SHIFT                   8
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div16                   0
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div20                   1
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div24                   2
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div26                   3
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div30                   4
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div32                   5
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div36                   6
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div40                   7
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div42                   8
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div48                   9
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div50                   10
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div52                   11
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div60                   12
#define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div64                   13

/* AN73_pdet :: xgxsStatus4 :: reserved1 [07:06] */
#define AN73_PDET_XGXSSTATUS4_RESERVED1_MASK                       0x00c0
#define AN73_PDET_XGXSSTATUS4_RESERVED1_ALIGN                      0
#define AN73_PDET_XGXSSTATUS4_RESERVED1_BITS                       2
#define AN73_PDET_XGXSSTATUS4_RESERVED1_SHIFT                      6

/* AN73_pdet :: xgxsStatus4 :: actual_speed_ln0 [05:00] */
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_MASK                0x003f
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_ALIGN               0
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_BITS                6
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_SHIFT               0
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10M              0
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_100M             1
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_1G               2
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_2p5G             3
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_5G_X4            4
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_6G_X4            5
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_HiG          6
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_CX4          7
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12G_HiG          8
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12p5G_X4         9
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_13G_X4           10
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_15G_X4           11
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_16G_X4           12
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_5G               16
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_6p4G             17
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_20G_X4           18
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_21G_X4           19
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_25G_X4           20
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_HiG_DXGXS    21
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_DXGXS        22
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10p5G_HiG_DXGXS  23
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10p5G_DXGXS      24
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12p773G_HiG_DXGXS  25
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12p773G_DXGXS    26
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_5G_HiG_DXGXS     42
#define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_5G_DXGXS         43

/****************************************************************************
 * AN73_pdet :: xgxsStatus5
 ***************************************************************************/
/* AN73_pdet :: xgxsStatus5 :: tx1g_mode_ln3 [15:14] */
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_MASK                   0xc000
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_ALIGN                  0
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_BITS                   2
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_SHIFT                  14
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_SWSDR_div2             0
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_SWSDR_div1             1
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_DWSDR_div2             2
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_DWSDR_div1             3

/* AN73_pdet :: xgxsStatus5 :: tx1g_mode_ln2 [13:12] */
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_MASK                   0x3000
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_ALIGN                  0
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_BITS                   2
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_SHIFT                  12
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_SWSDR_div2             0
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_SWSDR_div1             1
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_DWSDR_div2             2
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_DWSDR_div1             3

/* AN73_pdet :: xgxsStatus5 :: tx1g_mode_ln1 [11:10] */
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_MASK                   0x0c00
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_ALIGN                  0
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_BITS                   2
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_SHIFT                  10
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_SWSDR_div2             0
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_SWSDR_div1             1
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_DWSDR_div2             2
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_DWSDR_div1             3

/* AN73_pdet :: xgxsStatus5 :: tx1g_mode_ln0 [09:08] */
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_MASK                   0x0300
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_ALIGN                  0
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_BITS                   2
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_SHIFT                  8
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_SWSDR_div2             0
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_SWSDR_div1             1
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_DWSDR_div2             2
#define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_DWSDR_div1             3

/* AN73_pdet :: xgxsStatus5 :: rx1g_mode_ln3 [07:06] */
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_MASK                   0x00c0
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_ALIGN                  0
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_BITS                   2
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_SHIFT                  6
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_SWSDR_div2             0
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_SWSDR_div1             1
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_DWSDR_div2             2
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_DWSDR_div1             3

/* AN73_pdet :: xgxsStatus5 :: rx1g_mode_ln2 [05:04] */
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_MASK                   0x0030
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_ALIGN                  0
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_BITS                   2
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_SHIFT                  4
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_SWSDR_div2             0
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_SWSDR_div1             1
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_DWSDR_div2             2
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_DWSDR_div1             3

/* AN73_pdet :: xgxsStatus5 :: rx1g_mode_ln1 [03:02] */
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_MASK                   0x000c
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_ALIGN                  0
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_BITS                   2
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_SHIFT                  2
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_SWSDR_div2             0
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_SWSDR_div1             1
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_DWSDR_div2             2
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_DWSDR_div1             3

/* AN73_pdet :: xgxsStatus5 :: rx1g_mode_ln0 [01:00] */
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_MASK                   0x0003
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_ALIGN                  0
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_BITS                   2
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_SHIFT                  0
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_SWSDR_div2             0
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_SWSDR_div1             1
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_DWSDR_div2             2
#define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_DWSDR_div1             3


/****************************************************************************
 * AN73_pdet :: parDet10GControl2
 ***************************************************************************/
/* AN73_pdet :: parDet10GControl2 :: reserved0 [15:04] */
#define AN73_PDET_PARDET10GCONTROL2_RESERVED0_MASK                 0xfff0
#define AN73_PDET_PARDET10GCONTROL2_RESERVED0_ALIGN                0
#define AN73_PDET_PARDET10GCONTROL2_RESERVED0_BITS                 12
#define AN73_PDET_PARDET10GCONTROL2_RESERVED0_SHIFT                4

/* AN73_pdet :: parDet10GControl2 :: pd_parkFail [03:03] */
#define AN73_PDET_PARDET10GCONTROL2_PD_PARKFAIL_MASK               0x0008
#define AN73_PDET_PARDET10GCONTROL2_PD_PARKFAIL_ALIGN              0
#define AN73_PDET_PARDET10GCONTROL2_PD_PARKFAIL_BITS               1
#define AN73_PDET_PARDET10GCONTROL2_PD_PARKFAIL_SHIFT              3

/* AN73_pdet :: parDet10GControl2 :: pd_useLinkStatus [02:02] */
#define AN73_PDET_PARDET10GCONTROL2_PD_USELINKSTATUS_MASK          0x0004
#define AN73_PDET_PARDET10GCONTROL2_PD_USELINKSTATUS_ALIGN         0
#define AN73_PDET_PARDET10GCONTROL2_PD_USELINKSTATUS_BITS          1
#define AN73_PDET_PARDET10GCONTROL2_PD_USELINKSTATUS_SHIFT         2

/* AN73_pdet :: parDet10GControl2 :: pd_cl73_couple_dis [01:01] */
#define AN73_PDET_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_MASK        0x0002
#define AN73_PDET_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_ALIGN       0
#define AN73_PDET_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_BITS        1
#define AN73_PDET_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_SHIFT       1

/* AN73_pdet :: parDet10GControl2 :: pd_IgnoreLink_dis [00:00] */
#define AN73_PDET_PARDET10GCONTROL2_PD_IGNORELINK_DIS_MASK         0x0001
#define AN73_PDET_PARDET10GCONTROL2_PD_IGNORELINK_DIS_ALIGN        0
#define AN73_PDET_PARDET10GCONTROL2_PD_IGNORELINK_DIS_BITS         1
#define AN73_PDET_PARDET10GCONTROL2_PD_IGNORELINK_DIS_SHIFT        0


/****************************************************************************
 * Hypercore_USER_tx66_0
 ***************************************************************************/
/****************************************************************************
 * tx66_0 :: Control
 ***************************************************************************/
/* tx66_0 :: Control :: reserved_for_eco0 [15:04] */
#define TX66_0_CONTROL_RESERVED_FOR_ECO0_MASK                      0xfff0
#define TX66_0_CONTROL_RESERVED_FOR_ECO0_ALIGN                     0
#define TX66_0_CONTROL_RESERVED_FOR_ECO0_BITS                      12
#define TX66_0_CONTROL_RESERVED_FOR_ECO0_SHIFT                     4

/* tx66_0 :: Control :: scramblerControl [03:02] */
#define TX66_0_CONTROL_SCRAMBLERCONTROL_MASK                       0x000c
#define TX66_0_CONTROL_SCRAMBLERCONTROL_ALIGN                      0
#define TX66_0_CONTROL_SCRAMBLERCONTROL_BITS                       2
#define TX66_0_CONTROL_SCRAMBLERCONTROL_SHIFT                      2

/* tx66_0 :: Control :: tfifo_sbitclr [01:01] */
#define TX66_0_CONTROL_TFIFO_SBITCLR_MASK                          0x0002
#define TX66_0_CONTROL_TFIFO_SBITCLR_ALIGN                         0
#define TX66_0_CONTROL_TFIFO_SBITCLR_BITS                          1
#define TX66_0_CONTROL_TFIFO_SBITCLR_SHIFT                         1

/* tx66_0 :: Control :: tfifo_afrst_en [00:00] */
#define TX66_0_CONTROL_TFIFO_AFRST_EN_MASK                         0x0001
#define TX66_0_CONTROL_TFIFO_AFRST_EN_ALIGN                        0
#define TX66_0_CONTROL_TFIFO_AFRST_EN_BITS                         1
#define TX66_0_CONTROL_TFIFO_AFRST_EN_SHIFT                        0


/****************************************************************************
 * tx66_0 :: Status
 ***************************************************************************/
/* tx66_0 :: Status :: reserved_for_eco0 [15:03] */
#define TX66_0_STATUS_RESERVED_FOR_ECO0_MASK                       0xfff8
#define TX66_0_STATUS_RESERVED_FOR_ECO0_ALIGN                      0
#define TX66_0_STATUS_RESERVED_FOR_ECO0_BITS                       13
#define TX66_0_STATUS_RESERVED_FOR_ECO0_SHIFT                      3

/* tx66_0 :: Status :: ovflow [02:02] */
#define TX66_0_STATUS_OVFLOW_MASK                                  0x0004
#define TX66_0_STATUS_OVFLOW_ALIGN                                 0
#define TX66_0_STATUS_OVFLOW_BITS                                  1
#define TX66_0_STATUS_OVFLOW_SHIFT                                 2

/* tx66_0 :: Status :: unflow [01:01] */
#define TX66_0_STATUS_UNFLOW_MASK                                  0x0002
#define TX66_0_STATUS_UNFLOW_ALIGN                                 0
#define TX66_0_STATUS_UNFLOW_BITS                                  1
#define TX66_0_STATUS_UNFLOW_SHIFT                                 1

/* tx66_0 :: Status :: ferr [00:00] */
#define TX66_0_STATUS_FERR_MASK                                    0x0001
#define TX66_0_STATUS_FERR_ALIGN                                   0
#define TX66_0_STATUS_FERR_BITS                                    1
#define TX66_0_STATUS_FERR_SHIFT                                   0


/****************************************************************************
 * Hypercore_USER_tx66_1
 ***************************************************************************/
/****************************************************************************
 * tx66_1 :: Control
 ***************************************************************************/
/* tx66_1 :: Control :: reserved_for_eco0 [15:04] */
#define TX66_1_CONTROL_RESERVED_FOR_ECO0_MASK                      0xfff0
#define TX66_1_CONTROL_RESERVED_FOR_ECO0_ALIGN                     0
#define TX66_1_CONTROL_RESERVED_FOR_ECO0_BITS                      12
#define TX66_1_CONTROL_RESERVED_FOR_ECO0_SHIFT                     4

/* tx66_1 :: Control :: scramblerControl [03:02] */
#define TX66_1_CONTROL_SCRAMBLERCONTROL_MASK                       0x000c
#define TX66_1_CONTROL_SCRAMBLERCONTROL_ALIGN                      0
#define TX66_1_CONTROL_SCRAMBLERCONTROL_BITS                       2
#define TX66_1_CONTROL_SCRAMBLERCONTROL_SHIFT                      2

/* tx66_1 :: Control :: tfifo_sbitclr [01:01] */
#define TX66_1_CONTROL_TFIFO_SBITCLR_MASK                          0x0002
#define TX66_1_CONTROL_TFIFO_SBITCLR_ALIGN                         0
#define TX66_1_CONTROL_TFIFO_SBITCLR_BITS                          1
#define TX66_1_CONTROL_TFIFO_SBITCLR_SHIFT                         1

/* tx66_1 :: Control :: tfifo_afrst_en [00:00] */
#define TX66_1_CONTROL_TFIFO_AFRST_EN_MASK                         0x0001
#define TX66_1_CONTROL_TFIFO_AFRST_EN_ALIGN                        0
#define TX66_1_CONTROL_TFIFO_AFRST_EN_BITS                         1
#define TX66_1_CONTROL_TFIFO_AFRST_EN_SHIFT                        0


/****************************************************************************
 * tx66_1 :: Status
 ***************************************************************************/
/* tx66_1 :: Status :: reserved_for_eco0 [15:03] */
#define TX66_1_STATUS_RESERVED_FOR_ECO0_MASK                       0xfff8
#define TX66_1_STATUS_RESERVED_FOR_ECO0_ALIGN                      0
#define TX66_1_STATUS_RESERVED_FOR_ECO0_BITS                       13
#define TX66_1_STATUS_RESERVED_FOR_ECO0_SHIFT                      3

/* tx66_1 :: Status :: ovflow [02:02] */
#define TX66_1_STATUS_OVFLOW_MASK                                  0x0004
#define TX66_1_STATUS_OVFLOW_ALIGN                                 0
#define TX66_1_STATUS_OVFLOW_BITS                                  1
#define TX66_1_STATUS_OVFLOW_SHIFT                                 2

/* tx66_1 :: Status :: unflow [01:01] */
#define TX66_1_STATUS_UNFLOW_MASK                                  0x0002
#define TX66_1_STATUS_UNFLOW_ALIGN                                 0
#define TX66_1_STATUS_UNFLOW_BITS                                  1
#define TX66_1_STATUS_UNFLOW_SHIFT                                 1

/* tx66_1 :: Status :: ferr [00:00] */
#define TX66_1_STATUS_FERR_MASK                                    0x0001
#define TX66_1_STATUS_FERR_ALIGN                                   0
#define TX66_1_STATUS_FERR_BITS                                    1
#define TX66_1_STATUS_FERR_SHIFT                                   0


/****************************************************************************
 * Hypercore_USER_tx66_2
 ***************************************************************************/
/****************************************************************************
 * tx66_2 :: Control
 ***************************************************************************/
/* tx66_2 :: Control :: reserved_for_eco0 [15:04] */
#define TX66_2_CONTROL_RESERVED_FOR_ECO0_MASK                      0xfff0
#define TX66_2_CONTROL_RESERVED_FOR_ECO0_ALIGN                     0
#define TX66_2_CONTROL_RESERVED_FOR_ECO0_BITS                      12
#define TX66_2_CONTROL_RESERVED_FOR_ECO0_SHIFT                     4

/* tx66_2 :: Control :: scramblerControl [03:02] */
#define TX66_2_CONTROL_SCRAMBLERCONTROL_MASK                       0x000c
#define TX66_2_CONTROL_SCRAMBLERCONTROL_ALIGN                      0
#define TX66_2_CONTROL_SCRAMBLERCONTROL_BITS                       2
#define TX66_2_CONTROL_SCRAMBLERCONTROL_SHIFT                      2

/* tx66_2 :: Control :: tfifo_sbitclr [01:01] */
#define TX66_2_CONTROL_TFIFO_SBITCLR_MASK                          0x0002
#define TX66_2_CONTROL_TFIFO_SBITCLR_ALIGN                         0
#define TX66_2_CONTROL_TFIFO_SBITCLR_BITS                          1
#define TX66_2_CONTROL_TFIFO_SBITCLR_SHIFT                         1

/* tx66_2 :: Control :: tfifo_afrst_en [00:00] */
#define TX66_2_CONTROL_TFIFO_AFRST_EN_MASK                         0x0001
#define TX66_2_CONTROL_TFIFO_AFRST_EN_ALIGN                        0
#define TX66_2_CONTROL_TFIFO_AFRST_EN_BITS                         1
#define TX66_2_CONTROL_TFIFO_AFRST_EN_SHIFT                        0


/****************************************************************************
 * tx66_2 :: Status
 ***************************************************************************/
/* tx66_2 :: Status :: reserved_for_eco0 [15:03] */
#define TX66_2_STATUS_RESERVED_FOR_ECO0_MASK                       0xfff8
#define TX66_2_STATUS_RESERVED_FOR_ECO0_ALIGN                      0
#define TX66_2_STATUS_RESERVED_FOR_ECO0_BITS                       13
#define TX66_2_STATUS_RESERVED_FOR_ECO0_SHIFT                      3

/* tx66_2 :: Status :: ovflow [02:02] */
#define TX66_2_STATUS_OVFLOW_MASK                                  0x0004
#define TX66_2_STATUS_OVFLOW_ALIGN                                 0
#define TX66_2_STATUS_OVFLOW_BITS                                  1
#define TX66_2_STATUS_OVFLOW_SHIFT                                 2

/* tx66_2 :: Status :: unflow [01:01] */
#define TX66_2_STATUS_UNFLOW_MASK                                  0x0002
#define TX66_2_STATUS_UNFLOW_ALIGN                                 0
#define TX66_2_STATUS_UNFLOW_BITS                                  1
#define TX66_2_STATUS_UNFLOW_SHIFT                                 1

/* tx66_2 :: Status :: ferr [00:00] */
#define TX66_2_STATUS_FERR_MASK                                    0x0001
#define TX66_2_STATUS_FERR_ALIGN                                   0
#define TX66_2_STATUS_FERR_BITS                                    1
#define TX66_2_STATUS_FERR_SHIFT                                   0


/****************************************************************************
 * Hypercore_USER_tx66_3
 ***************************************************************************/
/****************************************************************************
 * tx66_3 :: Control
 ***************************************************************************/
/* tx66_3 :: Control :: reserved_for_eco0 [15:04] */
#define TX66_3_CONTROL_RESERVED_FOR_ECO0_MASK                      0xfff0
#define TX66_3_CONTROL_RESERVED_FOR_ECO0_ALIGN                     0
#define TX66_3_CONTROL_RESERVED_FOR_ECO0_BITS                      12
#define TX66_3_CONTROL_RESERVED_FOR_ECO0_SHIFT                     4

/* tx66_3 :: Control :: scramblerControl [03:02] */
#define TX66_3_CONTROL_SCRAMBLERCONTROL_MASK                       0x000c
#define TX66_3_CONTROL_SCRAMBLERCONTROL_ALIGN                      0
#define TX66_3_CONTROL_SCRAMBLERCONTROL_BITS                       2
#define TX66_3_CONTROL_SCRAMBLERCONTROL_SHIFT                      2

/* tx66_3 :: Control :: tfifo_sbitclr [01:01] */
#define TX66_3_CONTROL_TFIFO_SBITCLR_MASK                          0x0002
#define TX66_3_CONTROL_TFIFO_SBITCLR_ALIGN                         0
#define TX66_3_CONTROL_TFIFO_SBITCLR_BITS                          1
#define TX66_3_CONTROL_TFIFO_SBITCLR_SHIFT                         1

/* tx66_3 :: Control :: tfifo_afrst_en [00:00] */
#define TX66_3_CONTROL_TFIFO_AFRST_EN_MASK                         0x0001
#define TX66_3_CONTROL_TFIFO_AFRST_EN_ALIGN                        0
#define TX66_3_CONTROL_TFIFO_AFRST_EN_BITS                         1
#define TX66_3_CONTROL_TFIFO_AFRST_EN_SHIFT                        0


/****************************************************************************
 * tx66_3 :: Status
 ***************************************************************************/
/* tx66_3 :: Status :: reserved_for_eco0 [15:03] */
#define TX66_3_STATUS_RESERVED_FOR_ECO0_MASK                       0xfff8
#define TX66_3_STATUS_RESERVED_FOR_ECO0_ALIGN                      0
#define TX66_3_STATUS_RESERVED_FOR_ECO0_BITS                       13
#define TX66_3_STATUS_RESERVED_FOR_ECO0_SHIFT                      3

/* tx66_3 :: Status :: ovflow [02:02] */
#define TX66_3_STATUS_OVFLOW_MASK                                  0x0004
#define TX66_3_STATUS_OVFLOW_ALIGN                                 0
#define TX66_3_STATUS_OVFLOW_BITS                                  1
#define TX66_3_STATUS_OVFLOW_SHIFT                                 2

/* tx66_3 :: Status :: unflow [01:01] */
#define TX66_3_STATUS_UNFLOW_MASK                                  0x0002
#define TX66_3_STATUS_UNFLOW_ALIGN                                 0
#define TX66_3_STATUS_UNFLOW_BITS                                  1
#define TX66_3_STATUS_UNFLOW_SHIFT                                 1

/* tx66_3 :: Status :: ferr [00:00] */
#define TX66_3_STATUS_FERR_MASK                                    0x0001
#define TX66_3_STATUS_FERR_ALIGN                                   0
#define TX66_3_STATUS_FERR_BITS                                    1
#define TX66_3_STATUS_FERR_SHIFT                                   0


/****************************************************************************
 * Hypercore_USER_tx66_A
 ***************************************************************************/
/****************************************************************************
 * tx66_A :: Control
 ***************************************************************************/
/* tx66_A :: Control :: reserved_for_eco0 [15:04] */
#define TX66_A_CONTROL_RESERVED_FOR_ECO0_MASK                      0xfff0
#define TX66_A_CONTROL_RESERVED_FOR_ECO0_ALIGN                     0
#define TX66_A_CONTROL_RESERVED_FOR_ECO0_BITS                      12
#define TX66_A_CONTROL_RESERVED_FOR_ECO0_SHIFT                     4

/* tx66_A :: Control :: scramblerControl [03:02] */
#define TX66_A_CONTROL_SCRAMBLERCONTROL_MASK                       0x000c
#define TX66_A_CONTROL_SCRAMBLERCONTROL_ALIGN                      0
#define TX66_A_CONTROL_SCRAMBLERCONTROL_BITS                       2
#define TX66_A_CONTROL_SCRAMBLERCONTROL_SHIFT                      2

/* tx66_A :: Control :: tfifo_sbitclr [01:01] */
#define TX66_A_CONTROL_TFIFO_SBITCLR_MASK                          0x0002
#define TX66_A_CONTROL_TFIFO_SBITCLR_ALIGN                         0
#define TX66_A_CONTROL_TFIFO_SBITCLR_BITS                          1
#define TX66_A_CONTROL_TFIFO_SBITCLR_SHIFT                         1

/* tx66_A :: Control :: tfifo_afrst_en [00:00] */
#define TX66_A_CONTROL_TFIFO_AFRST_EN_MASK                         0x0001
#define TX66_A_CONTROL_TFIFO_AFRST_EN_ALIGN                        0
#define TX66_A_CONTROL_TFIFO_AFRST_EN_BITS                         1
#define TX66_A_CONTROL_TFIFO_AFRST_EN_SHIFT                        0


/****************************************************************************
 * tx66_A :: Status
 ***************************************************************************/
/* tx66_A :: Status :: reserved_for_eco0 [15:03] */
#define TX66_A_STATUS_RESERVED_FOR_ECO0_MASK                       0xfff8
#define TX66_A_STATUS_RESERVED_FOR_ECO0_ALIGN                      0
#define TX66_A_STATUS_RESERVED_FOR_ECO0_BITS                       13
#define TX66_A_STATUS_RESERVED_FOR_ECO0_SHIFT                      3

/* tx66_A :: Status :: ovflow [02:02] */
#define TX66_A_STATUS_OVFLOW_MASK                                  0x0004
#define TX66_A_STATUS_OVFLOW_ALIGN                                 0
#define TX66_A_STATUS_OVFLOW_BITS                                  1
#define TX66_A_STATUS_OVFLOW_SHIFT                                 2

/* tx66_A :: Status :: unflow [01:01] */
#define TX66_A_STATUS_UNFLOW_MASK                                  0x0002
#define TX66_A_STATUS_UNFLOW_ALIGN                                 0
#define TX66_A_STATUS_UNFLOW_BITS                                  1
#define TX66_A_STATUS_UNFLOW_SHIFT                                 1

/* tx66_A :: Status :: ferr [00:00] */
#define TX66_A_STATUS_FERR_MASK                                    0x0001
#define TX66_A_STATUS_FERR_ALIGN                                   0
#define TX66_A_STATUS_FERR_BITS                                    1
#define TX66_A_STATUS_FERR_SHIFT                                   0


/****************************************************************************
 * Hypercore_USER_rx66_0
 ***************************************************************************/
/****************************************************************************
 * rx66_0 :: Control
 ***************************************************************************/
/* rx66_0 :: Control :: reserved0 [15:10] */
#define RX66_0_CONTROL_RESERVED0_MASK                              0xfc00
#define RX66_0_CONTROL_RESERVED0_ALIGN                             0
#define RX66_0_CONTROL_RESERVED0_BITS                              6
#define RX66_0_CONTROL_RESERVED0_SHIFT                             10

/* rx66_0 :: Control :: rxSeqDoneMask [09:09] */
#define RX66_0_CONTROL_RXSEQDONEMASK_MASK                          0x0200
#define RX66_0_CONTROL_RXSEQDONEMASK_ALIGN                         0
#define RX66_0_CONTROL_RXSEQDONEMASK_BITS                          1
#define RX66_0_CONTROL_RXSEQDONEMASK_SHIFT                         9

/* rx66_0 :: Control :: cwCount_sel [08:08] */
#define RX66_0_CONTROL_CWCOUNT_SEL_MASK                            0x0100
#define RX66_0_CONTROL_CWCOUNT_SEL_ALIGN                           0
#define RX66_0_CONTROL_CWCOUNT_SEL_BITS                            1
#define RX66_0_CONTROL_CWCOUNT_SEL_SHIFT                           8

/* rx66_0 :: Control :: cwCount_en [07:07] */
#define RX66_0_CONTROL_CWCOUNT_EN_MASK                             0x0080
#define RX66_0_CONTROL_CWCOUNT_EN_ALIGN                            0
#define RX66_0_CONTROL_CWCOUNT_EN_BITS                             1
#define RX66_0_CONTROL_CWCOUNT_EN_SHIFT                            7

/* rx66_0 :: Control :: sync66ErrCount_en [06:06] */
#define RX66_0_CONTROL_SYNC66ERRCOUNT_EN_MASK                      0x0040
#define RX66_0_CONTROL_SYNC66ERRCOUNT_EN_ALIGN                     0
#define RX66_0_CONTROL_SYNC66ERRCOUNT_EN_BITS                      1
#define RX66_0_CONTROL_SYNC66ERRCOUNT_EN_SHIFT                     6

/* rx66_0 :: Control :: kcode66ErrCount_en [05:05] */
#define RX66_0_CONTROL_KCODE66ERRCOUNT_EN_MASK                     0x0020
#define RX66_0_CONTROL_KCODE66ERRCOUNT_EN_ALIGN                    0
#define RX66_0_CONTROL_KCODE66ERRCOUNT_EN_BITS                     1
#define RX66_0_CONTROL_KCODE66ERRCOUNT_EN_SHIFT                    5

/* rx66_0 :: Control :: cgbad_kcode66Err_en [04:04] */
#define RX66_0_CONTROL_CGBAD_KCODE66ERR_EN_MASK                    0x0010
#define RX66_0_CONTROL_CGBAD_KCODE66ERR_EN_ALIGN                   0
#define RX66_0_CONTROL_CGBAD_KCODE66ERR_EN_BITS                    1
#define RX66_0_CONTROL_CGBAD_KCODE66ERR_EN_SHIFT                   4

/* rx66_0 :: Control :: descramblerControl [03:02] */
#define RX66_0_CONTROL_DESCRAMBLERCONTROL_MASK                     0x000c
#define RX66_0_CONTROL_DESCRAMBLERCONTROL_ALIGN                    0
#define RX66_0_CONTROL_DESCRAMBLERCONTROL_BITS                     2
#define RX66_0_CONTROL_DESCRAMBLERCONTROL_SHIFT                    2

/* rx66_0 :: Control :: rfifo_sbitclr [01:01] */
#define RX66_0_CONTROL_RFIFO_SBITCLR_MASK                          0x0002
#define RX66_0_CONTROL_RFIFO_SBITCLR_ALIGN                         0
#define RX66_0_CONTROL_RFIFO_SBITCLR_BITS                          1
#define RX66_0_CONTROL_RFIFO_SBITCLR_SHIFT                         1

/* rx66_0 :: Control :: rfifo_afrst_en [00:00] */
#define RX66_0_CONTROL_RFIFO_AFRST_EN_MASK                         0x0001
#define RX66_0_CONTROL_RFIFO_AFRST_EN_ALIGN                        0
#define RX66_0_CONTROL_RFIFO_AFRST_EN_BITS                         1
#define RX66_0_CONTROL_RFIFO_AFRST_EN_SHIFT                        0


/****************************************************************************
 * rx66_0 :: Status
 ***************************************************************************/
/* rx66_0 :: Status :: LOSS_OF_SYNC [15:15] */
#define RX66_0_STATUS_LOSS_OF_SYNC_MASK                            0x8000
#define RX66_0_STATUS_LOSS_OF_SYNC_ALIGN                           0
#define RX66_0_STATUS_LOSS_OF_SYNC_BITS                            1
#define RX66_0_STATUS_LOSS_OF_SYNC_SHIFT                           15

/* rx66_0 :: Status :: COMMA_DETECT [14:14] */
#define RX66_0_STATUS_COMMA_DETECT_MASK                            0x4000
#define RX66_0_STATUS_COMMA_DETECT_ALIGN                           0
#define RX66_0_STATUS_COMMA_DETECT_BITS                            1
#define RX66_0_STATUS_COMMA_DETECT_SHIFT                           14

/* rx66_0 :: Status :: SYNC_ACQD1 [13:13] */
#define RX66_0_STATUS_SYNC_ACQD1_MASK                              0x2000
#define RX66_0_STATUS_SYNC_ACQD1_ALIGN                             0
#define RX66_0_STATUS_SYNC_ACQD1_BITS                              1
#define RX66_0_STATUS_SYNC_ACQD1_SHIFT                             13

/* rx66_0 :: Status :: SYNC_ACQD2 [12:12] */
#define RX66_0_STATUS_SYNC_ACQD2_MASK                              0x1000
#define RX66_0_STATUS_SYNC_ACQD2_ALIGN                             0
#define RX66_0_STATUS_SYNC_ACQD2_BITS                              1
#define RX66_0_STATUS_SYNC_ACQD2_SHIFT                             12

/* rx66_0 :: Status :: reserved0 [11:04] */
#define RX66_0_STATUS_RESERVED0_MASK                               0x0ff0
#define RX66_0_STATUS_RESERVED0_ALIGN                              0
#define RX66_0_STATUS_RESERVED0_BITS                               8
#define RX66_0_STATUS_RESERVED0_SHIFT                              4

/* rx66_0 :: Status :: syncDone [03:03] */
#define RX66_0_STATUS_SYNCDONE_MASK                                0x0008
#define RX66_0_STATUS_SYNCDONE_ALIGN                               0
#define RX66_0_STATUS_SYNCDONE_BITS                                1
#define RX66_0_STATUS_SYNCDONE_SHIFT                               3

/* rx66_0 :: Status :: unflow [02:02] */
#define RX66_0_STATUS_UNFLOW_MASK                                  0x0004
#define RX66_0_STATUS_UNFLOW_ALIGN                                 0
#define RX66_0_STATUS_UNFLOW_BITS                                  1
#define RX66_0_STATUS_UNFLOW_SHIFT                                 2

/* rx66_0 :: Status :: ovflow [01:01] */
#define RX66_0_STATUS_OVFLOW_MASK                                  0x0002
#define RX66_0_STATUS_OVFLOW_ALIGN                                 0
#define RX66_0_STATUS_OVFLOW_BITS                                  1
#define RX66_0_STATUS_OVFLOW_SHIFT                                 1

/* rx66_0 :: Status :: ferr [00:00] */
#define RX66_0_STATUS_FERR_MASK                                    0x0001
#define RX66_0_STATUS_FERR_ALIGN                                   0
#define RX66_0_STATUS_FERR_BITS                                    1
#define RX66_0_STATUS_FERR_SHIFT                                   0


/****************************************************************************
 * rx66_0 :: scw0
 ***************************************************************************/
/* rx66_0 :: scw0 :: scw0 [15:00] */
#define RX66_0_SCW0_SCW0_MASK                                      0xffff
#define RX66_0_SCW0_SCW0_ALIGN                                     0
#define RX66_0_SCW0_SCW0_BITS                                      16
#define RX66_0_SCW0_SCW0_SHIFT                                     0


/****************************************************************************
 * rx66_0 :: scw1
 ***************************************************************************/
/* rx66_0 :: scw1 :: scw1 [15:00] */
#define RX66_0_SCW1_SCW1_MASK                                      0xffff
#define RX66_0_SCW1_SCW1_ALIGN                                     0
#define RX66_0_SCW1_SCW1_BITS                                      16
#define RX66_0_SCW1_SCW1_SHIFT                                     0


/****************************************************************************
 * rx66_0 :: scw2
 ***************************************************************************/
/* rx66_0 :: scw2 :: scw2 [15:00] */
#define RX66_0_SCW2_SCW2_MASK                                      0xffff
#define RX66_0_SCW2_SCW2_ALIGN                                     0
#define RX66_0_SCW2_SCW2_BITS                                      16
#define RX66_0_SCW2_SCW2_SHIFT                                     0


/****************************************************************************
 * rx66_0 :: scw3
 ***************************************************************************/
/* rx66_0 :: scw3 :: scw3 [15:00] */
#define RX66_0_SCW3_SCW3_MASK                                      0xffff
#define RX66_0_SCW3_SCW3_ALIGN                                     0
#define RX66_0_SCW3_SCW3_BITS                                      16
#define RX66_0_SCW3_SCW3_SHIFT                                     0


/****************************************************************************
 * rx66_0 :: scw0_mask
 ***************************************************************************/
/* rx66_0 :: scw0_mask :: scw0_mask [15:00] */
#define RX66_0_SCW0_MASK_SCW0_MASK_MASK                            0xffff
#define RX66_0_SCW0_MASK_SCW0_MASK_ALIGN                           0
#define RX66_0_SCW0_MASK_SCW0_MASK_BITS                            16
#define RX66_0_SCW0_MASK_SCW0_MASK_SHIFT                           0


/****************************************************************************
 * rx66_0 :: scw1_mask
 ***************************************************************************/
/* rx66_0 :: scw1_mask :: scw1_mask [15:00] */
#define RX66_0_SCW1_MASK_SCW1_MASK_MASK                            0xffff
#define RX66_0_SCW1_MASK_SCW1_MASK_ALIGN                           0
#define RX66_0_SCW1_MASK_SCW1_MASK_BITS                            16
#define RX66_0_SCW1_MASK_SCW1_MASK_SHIFT                           0


/****************************************************************************
 * rx66_0 :: scw2_mask
 ***************************************************************************/
/* rx66_0 :: scw2_mask :: scw2_mask [15:00] */
#define RX66_0_SCW2_MASK_SCW2_MASK_MASK                            0xffff
#define RX66_0_SCW2_MASK_SCW2_MASK_ALIGN                           0
#define RX66_0_SCW2_MASK_SCW2_MASK_BITS                            16
#define RX66_0_SCW2_MASK_SCW2_MASK_SHIFT                           0


/****************************************************************************
 * rx66_0 :: scw3_mask
 ***************************************************************************/
/* rx66_0 :: scw3_mask :: scw3_mask [15:00] */
#define RX66_0_SCW3_MASK_SCW3_MASK_MASK                            0xffff
#define RX66_0_SCW3_MASK_SCW3_MASK_ALIGN                           0
#define RX66_0_SCW3_MASK_SCW3_MASK_BITS                            16
#define RX66_0_SCW3_MASK_SCW3_MASK_SHIFT                           0


/****************************************************************************
 * rx66_0 :: syncbits
 ***************************************************************************/
/* rx66_0 :: syncbits :: reserved0 [15:04] */
#define RX66_0_SYNCBITS_RESERVED0_MASK                             0xfff0
#define RX66_0_SYNCBITS_RESERVED0_ALIGN                            0
#define RX66_0_SYNCBITS_RESERVED0_BITS                             12
#define RX66_0_SYNCBITS_RESERVED0_SHIFT                            4

/* rx66_0 :: syncbits :: syncbits [03:02] */
#define RX66_0_SYNCBITS_SYNCBITS_MASK                              0x000c
#define RX66_0_SYNCBITS_SYNCBITS_ALIGN                             0
#define RX66_0_SYNCBITS_SYNCBITS_BITS                              2
#define RX66_0_SYNCBITS_SYNCBITS_SHIFT                             2

/* rx66_0 :: syncbits :: syncbits_mask [01:00] */
#define RX66_0_SYNCBITS_SYNCBITS_MASK_MASK                         0x0003
#define RX66_0_SYNCBITS_SYNCBITS_MASK_ALIGN                        0
#define RX66_0_SYNCBITS_SYNCBITS_MASK_BITS                         2
#define RX66_0_SYNCBITS_SYNCBITS_MASK_SHIFT                        0


/****************************************************************************
 * rx66_0 :: scwControl
 ***************************************************************************/
/* rx66_0 :: scwControl :: reserved0 [15:15] */
#define RX66_0_SCWCONTROL_RESERVED0_MASK                           0x8000
#define RX66_0_SCWCONTROL_RESERVED0_ALIGN                          0
#define RX66_0_SCWCONTROL_RESERVED0_BITS                           1
#define RX66_0_SCWCONTROL_RESERVED0_SHIFT                          15

/* rx66_0 :: scwControl :: scwCount [14:10] */
#define RX66_0_SCWCONTROL_SCWCOUNT_MASK                            0x7c00
#define RX66_0_SCWCONTROL_SCWCOUNT_ALIGN                           0
#define RX66_0_SCWCONTROL_SCWCOUNT_BITS                            5
#define RX66_0_SCWCONTROL_SCWCOUNT_SHIFT                           10

/* rx66_0 :: scwControl :: gcwCount [09:05] */
#define RX66_0_SCWCONTROL_GCWCOUNT_MASK                            0x03e0
#define RX66_0_SCWCONTROL_GCWCOUNT_ALIGN                           0
#define RX66_0_SCWCONTROL_GCWCOUNT_BITS                            5
#define RX66_0_SCWCONTROL_GCWCOUNT_SHIFT                           5

/* rx66_0 :: scwControl :: hystCount [04:00] */
#define RX66_0_SCWCONTROL_HYSTCOUNT_MASK                           0x001f
#define RX66_0_SCWCONTROL_HYSTCOUNT_ALIGN                          0
#define RX66_0_SCWCONTROL_HYSTCOUNT_BITS                           5
#define RX66_0_SCWCONTROL_HYSTCOUNT_SHIFT                          0


/****************************************************************************
 * rx66_0 :: scwCount
 ***************************************************************************/
/* rx66_0 :: scwCount :: reserved0 [15:15] */
#define RX66_0_SCWCOUNT_RESERVED0_MASK                             0x8000
#define RX66_0_SCWCOUNT_RESERVED0_ALIGN                            0
#define RX66_0_SCWCOUNT_RESERVED0_BITS                             1
#define RX66_0_SCWCOUNT_RESERVED0_SHIFT                            15

/* rx66_0 :: scwCount :: scwShift [14:08] */
#define RX66_0_SCWCOUNT_SCWSHIFT_MASK                              0x7f00
#define RX66_0_SCWCOUNT_SCWSHIFT_ALIGN                             0
#define RX66_0_SCWCOUNT_SCWSHIFT_BITS                              7
#define RX66_0_SCWCOUNT_SCWSHIFT_SHIFT                             8

/* union - case COMMA_DETECT [07:00] */
/* rx66_0 :: scwCount :: cwCount [07:00] */
#define RX66_0_SCWCOUNT_COMMA_DETECT_CWCOUNT_MASK                  0x00ff
#define RX66_0_SCWCOUNT_COMMA_DETECT_CWCOUNT_ALIGN                 0
#define RX66_0_SCWCOUNT_COMMA_DETECT_CWCOUNT_BITS                  8
#define RX66_0_SCWCOUNT_COMMA_DETECT_CWCOUNT_SHIFT                 0


/* union - case SYNC_ACQD2 [07:00] */
/* rx66_0 :: scwCount :: cwCount [07:00] */
#define RX66_0_SCWCOUNT_SYNC_ACQD2_CWCOUNT_MASK                    0x00ff
#define RX66_0_SCWCOUNT_SYNC_ACQD2_CWCOUNT_ALIGN                   0
#define RX66_0_SCWCOUNT_SYNC_ACQD2_CWCOUNT_BITS                    8
#define RX66_0_SCWCOUNT_SYNC_ACQD2_CWCOUNT_SHIFT                   0



/****************************************************************************
 * rx66_0 :: errCount
 ***************************************************************************/
/* rx66_0 :: errCount :: sync66ErrCount [15:08] */
#define RX66_0_ERRCOUNT_SYNC66ERRCOUNT_MASK                        0xff00
#define RX66_0_ERRCOUNT_SYNC66ERRCOUNT_ALIGN                       0
#define RX66_0_ERRCOUNT_SYNC66ERRCOUNT_BITS                        8
#define RX66_0_ERRCOUNT_SYNC66ERRCOUNT_SHIFT                       8

/* rx66_0 :: errCount :: kcode66ErrCount [07:00] */
#define RX66_0_ERRCOUNT_KCODE66ERRCOUNT_MASK                       0x00ff
#define RX66_0_ERRCOUNT_KCODE66ERRCOUNT_ALIGN                      0
#define RX66_0_ERRCOUNT_KCODE66ERRCOUNT_BITS                       8
#define RX66_0_ERRCOUNT_KCODE66ERRCOUNT_SHIFT                      0


/****************************************************************************
 * Hypercore_USER_rx66_1
 ***************************************************************************/
/****************************************************************************
 * rx66_1 :: Control
 ***************************************************************************/
/* rx66_1 :: Control :: reserved0 [15:10] */
#define RX66_1_CONTROL_RESERVED0_MASK                              0xfc00
#define RX66_1_CONTROL_RESERVED0_ALIGN                             0
#define RX66_1_CONTROL_RESERVED0_BITS                              6
#define RX66_1_CONTROL_RESERVED0_SHIFT                             10

/* rx66_1 :: Control :: rxSeqDoneMask [09:09] */
#define RX66_1_CONTROL_RXSEQDONEMASK_MASK                          0x0200
#define RX66_1_CONTROL_RXSEQDONEMASK_ALIGN                         0
#define RX66_1_CONTROL_RXSEQDONEMASK_BITS                          1
#define RX66_1_CONTROL_RXSEQDONEMASK_SHIFT                         9

/* rx66_1 :: Control :: cwCount_sel [08:08] */
#define RX66_1_CONTROL_CWCOUNT_SEL_MASK                            0x0100
#define RX66_1_CONTROL_CWCOUNT_SEL_ALIGN                           0
#define RX66_1_CONTROL_CWCOUNT_SEL_BITS                            1
#define RX66_1_CONTROL_CWCOUNT_SEL_SHIFT                           8

/* rx66_1 :: Control :: cwCount_en [07:07] */
#define RX66_1_CONTROL_CWCOUNT_EN_MASK                             0x0080
#define RX66_1_CONTROL_CWCOUNT_EN_ALIGN                            0
#define RX66_1_CONTROL_CWCOUNT_EN_BITS                             1
#define RX66_1_CONTROL_CWCOUNT_EN_SHIFT                            7

/* rx66_1 :: Control :: sync66ErrCount_en [06:06] */
#define RX66_1_CONTROL_SYNC66ERRCOUNT_EN_MASK                      0x0040
#define RX66_1_CONTROL_SYNC66ERRCOUNT_EN_ALIGN                     0
#define RX66_1_CONTROL_SYNC66ERRCOUNT_EN_BITS                      1
#define RX66_1_CONTROL_SYNC66ERRCOUNT_EN_SHIFT                     6

/* rx66_1 :: Control :: kcode66ErrCount_en [05:05] */
#define RX66_1_CONTROL_KCODE66ERRCOUNT_EN_MASK                     0x0020
#define RX66_1_CONTROL_KCODE66ERRCOUNT_EN_ALIGN                    0
#define RX66_1_CONTROL_KCODE66ERRCOUNT_EN_BITS                     1
#define RX66_1_CONTROL_KCODE66ERRCOUNT_EN_SHIFT                    5

/* rx66_1 :: Control :: cgbad_kcode66Err_en [04:04] */
#define RX66_1_CONTROL_CGBAD_KCODE66ERR_EN_MASK                    0x0010
#define RX66_1_CONTROL_CGBAD_KCODE66ERR_EN_ALIGN                   0
#define RX66_1_CONTROL_CGBAD_KCODE66ERR_EN_BITS                    1
#define RX66_1_CONTROL_CGBAD_KCODE66ERR_EN_SHIFT                   4

/* rx66_1 :: Control :: descramblerControl [03:02] */
#define RX66_1_CONTROL_DESCRAMBLERCONTROL_MASK                     0x000c
#define RX66_1_CONTROL_DESCRAMBLERCONTROL_ALIGN                    0
#define RX66_1_CONTROL_DESCRAMBLERCONTROL_BITS                     2
#define RX66_1_CONTROL_DESCRAMBLERCONTROL_SHIFT                    2

/* rx66_1 :: Control :: rfifo_sbitclr [01:01] */
#define RX66_1_CONTROL_RFIFO_SBITCLR_MASK                          0x0002
#define RX66_1_CONTROL_RFIFO_SBITCLR_ALIGN                         0
#define RX66_1_CONTROL_RFIFO_SBITCLR_BITS                          1
#define RX66_1_CONTROL_RFIFO_SBITCLR_SHIFT                         1

/* rx66_1 :: Control :: rfifo_afrst_en [00:00] */
#define RX66_1_CONTROL_RFIFO_AFRST_EN_MASK                         0x0001
#define RX66_1_CONTROL_RFIFO_AFRST_EN_ALIGN                        0
#define RX66_1_CONTROL_RFIFO_AFRST_EN_BITS                         1
#define RX66_1_CONTROL_RFIFO_AFRST_EN_SHIFT                        0


/****************************************************************************
 * rx66_1 :: Status
 ***************************************************************************/
/* rx66_1 :: Status :: LOSS_OF_SYNC [15:15] */
#define RX66_1_STATUS_LOSS_OF_SYNC_MASK                            0x8000
#define RX66_1_STATUS_LOSS_OF_SYNC_ALIGN                           0
#define RX66_1_STATUS_LOSS_OF_SYNC_BITS                            1
#define RX66_1_STATUS_LOSS_OF_SYNC_SHIFT                           15

/* rx66_1 :: Status :: COMMA_DETECT [14:14] */
#define RX66_1_STATUS_COMMA_DETECT_MASK                            0x4000
#define RX66_1_STATUS_COMMA_DETECT_ALIGN                           0
#define RX66_1_STATUS_COMMA_DETECT_BITS                            1
#define RX66_1_STATUS_COMMA_DETECT_SHIFT                           14

/* rx66_1 :: Status :: SYNC_ACQD1 [13:13] */
#define RX66_1_STATUS_SYNC_ACQD1_MASK                              0x2000
#define RX66_1_STATUS_SYNC_ACQD1_ALIGN                             0
#define RX66_1_STATUS_SYNC_ACQD1_BITS                              1
#define RX66_1_STATUS_SYNC_ACQD1_SHIFT                             13

/* rx66_1 :: Status :: SYNC_ACQD2 [12:12] */
#define RX66_1_STATUS_SYNC_ACQD2_MASK                              0x1000
#define RX66_1_STATUS_SYNC_ACQD2_ALIGN                             0
#define RX66_1_STATUS_SYNC_ACQD2_BITS                              1
#define RX66_1_STATUS_SYNC_ACQD2_SHIFT                             12

/* rx66_1 :: Status :: reserved0 [11:04] */
#define RX66_1_STATUS_RESERVED0_MASK                               0x0ff0
#define RX66_1_STATUS_RESERVED0_ALIGN                              0
#define RX66_1_STATUS_RESERVED0_BITS                               8
#define RX66_1_STATUS_RESERVED0_SHIFT                              4

/* rx66_1 :: Status :: syncDone [03:03] */
#define RX66_1_STATUS_SYNCDONE_MASK                                0x0008
#define RX66_1_STATUS_SYNCDONE_ALIGN                               0
#define RX66_1_STATUS_SYNCDONE_BITS                                1
#define RX66_1_STATUS_SYNCDONE_SHIFT                               3

/* rx66_1 :: Status :: unflow [02:02] */
#define RX66_1_STATUS_UNFLOW_MASK                                  0x0004
#define RX66_1_STATUS_UNFLOW_ALIGN                                 0
#define RX66_1_STATUS_UNFLOW_BITS                                  1
#define RX66_1_STATUS_UNFLOW_SHIFT                                 2

/* rx66_1 :: Status :: ovflow [01:01] */
#define RX66_1_STATUS_OVFLOW_MASK                                  0x0002
#define RX66_1_STATUS_OVFLOW_ALIGN                                 0
#define RX66_1_STATUS_OVFLOW_BITS                                  1
#define RX66_1_STATUS_OVFLOW_SHIFT                                 1

/* rx66_1 :: Status :: ferr [00:00] */
#define RX66_1_STATUS_FERR_MASK                                    0x0001
#define RX66_1_STATUS_FERR_ALIGN                                   0
#define RX66_1_STATUS_FERR_BITS                                    1
#define RX66_1_STATUS_FERR_SHIFT                                   0


/****************************************************************************
 * rx66_1 :: scw0
 ***************************************************************************/
/* rx66_1 :: scw0 :: scw0 [15:00] */
#define RX66_1_SCW0_SCW0_MASK                                      0xffff
#define RX66_1_SCW0_SCW0_ALIGN                                     0
#define RX66_1_SCW0_SCW0_BITS                                      16
#define RX66_1_SCW0_SCW0_SHIFT                                     0


/****************************************************************************
 * rx66_1 :: scw1
 ***************************************************************************/
/* rx66_1 :: scw1 :: scw1 [15:00] */
#define RX66_1_SCW1_SCW1_MASK                                      0xffff
#define RX66_1_SCW1_SCW1_ALIGN                                     0
#define RX66_1_SCW1_SCW1_BITS                                      16
#define RX66_1_SCW1_SCW1_SHIFT                                     0


/****************************************************************************
 * rx66_1 :: scw2
 ***************************************************************************/
/* rx66_1 :: scw2 :: scw2 [15:00] */
#define RX66_1_SCW2_SCW2_MASK                                      0xffff
#define RX66_1_SCW2_SCW2_ALIGN                                     0
#define RX66_1_SCW2_SCW2_BITS                                      16
#define RX66_1_SCW2_SCW2_SHIFT                                     0


/****************************************************************************
 * rx66_1 :: scw3
 ***************************************************************************/
/* rx66_1 :: scw3 :: scw3 [15:00] */
#define RX66_1_SCW3_SCW3_MASK                                      0xffff
#define RX66_1_SCW3_SCW3_ALIGN                                     0
#define RX66_1_SCW3_SCW3_BITS                                      16
#define RX66_1_SCW3_SCW3_SHIFT                                     0


/****************************************************************************
 * rx66_1 :: scw0_mask
 ***************************************************************************/
/* rx66_1 :: scw0_mask :: scw0_mask [15:00] */
#define RX66_1_SCW0_MASK_SCW0_MASK_MASK                            0xffff
#define RX66_1_SCW0_MASK_SCW0_MASK_ALIGN                           0
#define RX66_1_SCW0_MASK_SCW0_MASK_BITS                            16
#define RX66_1_SCW0_MASK_SCW0_MASK_SHIFT                           0


/****************************************************************************
 * rx66_1 :: scw1_mask
 ***************************************************************************/
/* rx66_1 :: scw1_mask :: scw1_mask [15:00] */
#define RX66_1_SCW1_MASK_SCW1_MASK_MASK                            0xffff
#define RX66_1_SCW1_MASK_SCW1_MASK_ALIGN                           0
#define RX66_1_SCW1_MASK_SCW1_MASK_BITS                            16
#define RX66_1_SCW1_MASK_SCW1_MASK_SHIFT                           0


/****************************************************************************
 * rx66_1 :: scw2_mask
 ***************************************************************************/
/* rx66_1 :: scw2_mask :: scw2_mask [15:00] */
#define RX66_1_SCW2_MASK_SCW2_MASK_MASK                            0xffff
#define RX66_1_SCW2_MASK_SCW2_MASK_ALIGN                           0
#define RX66_1_SCW2_MASK_SCW2_MASK_BITS                            16
#define RX66_1_SCW2_MASK_SCW2_MASK_SHIFT                           0


/****************************************************************************
 * rx66_1 :: scw3_mask
 ***************************************************************************/
/* rx66_1 :: scw3_mask :: scw3_mask [15:00] */
#define RX66_1_SCW3_MASK_SCW3_MASK_MASK                            0xffff
#define RX66_1_SCW3_MASK_SCW3_MASK_ALIGN                           0
#define RX66_1_SCW3_MASK_SCW3_MASK_BITS                            16
#define RX66_1_SCW3_MASK_SCW3_MASK_SHIFT                           0


/****************************************************************************
 * rx66_1 :: syncbits
 ***************************************************************************/
/* rx66_1 :: syncbits :: reserved0 [15:04] */
#define RX66_1_SYNCBITS_RESERVED0_MASK                             0xfff0
#define RX66_1_SYNCBITS_RESERVED0_ALIGN                            0
#define RX66_1_SYNCBITS_RESERVED0_BITS                             12
#define RX66_1_SYNCBITS_RESERVED0_SHIFT                            4

/* rx66_1 :: syncbits :: syncbits [03:02] */
#define RX66_1_SYNCBITS_SYNCBITS_MASK                              0x000c
#define RX66_1_SYNCBITS_SYNCBITS_ALIGN                             0
#define RX66_1_SYNCBITS_SYNCBITS_BITS                              2
#define RX66_1_SYNCBITS_SYNCBITS_SHIFT                             2

/* rx66_1 :: syncbits :: syncbits_mask [01:00] */
#define RX66_1_SYNCBITS_SYNCBITS_MASK_MASK                         0x0003
#define RX66_1_SYNCBITS_SYNCBITS_MASK_ALIGN                        0
#define RX66_1_SYNCBITS_SYNCBITS_MASK_BITS                         2
#define RX66_1_SYNCBITS_SYNCBITS_MASK_SHIFT                        0


/****************************************************************************
 * rx66_1 :: scwControl
 ***************************************************************************/
/* rx66_1 :: scwControl :: reserved0 [15:15] */
#define RX66_1_SCWCONTROL_RESERVED0_MASK                           0x8000
#define RX66_1_SCWCONTROL_RESERVED0_ALIGN                          0
#define RX66_1_SCWCONTROL_RESERVED0_BITS                           1
#define RX66_1_SCWCONTROL_RESERVED0_SHIFT                          15

/* rx66_1 :: scwControl :: scwCount [14:10] */
#define RX66_1_SCWCONTROL_SCWCOUNT_MASK                            0x7c00
#define RX66_1_SCWCONTROL_SCWCOUNT_ALIGN                           0
#define RX66_1_SCWCONTROL_SCWCOUNT_BITS                            5
#define RX66_1_SCWCONTROL_SCWCOUNT_SHIFT                           10

/* rx66_1 :: scwControl :: gcwCount [09:05] */
#define RX66_1_SCWCONTROL_GCWCOUNT_MASK                            0x03e0
#define RX66_1_SCWCONTROL_GCWCOUNT_ALIGN                           0
#define RX66_1_SCWCONTROL_GCWCOUNT_BITS                            5
#define RX66_1_SCWCONTROL_GCWCOUNT_SHIFT                           5

/* rx66_1 :: scwControl :: hystCount [04:00] */
#define RX66_1_SCWCONTROL_HYSTCOUNT_MASK                           0x001f
#define RX66_1_SCWCONTROL_HYSTCOUNT_ALIGN                          0
#define RX66_1_SCWCONTROL_HYSTCOUNT_BITS                           5
#define RX66_1_SCWCONTROL_HYSTCOUNT_SHIFT                          0


/****************************************************************************
 * rx66_1 :: scwCount
 ***************************************************************************/
/* rx66_1 :: scwCount :: reserved0 [15:15] */
#define RX66_1_SCWCOUNT_RESERVED0_MASK                             0x8000
#define RX66_1_SCWCOUNT_RESERVED0_ALIGN                            0
#define RX66_1_SCWCOUNT_RESERVED0_BITS                             1
#define RX66_1_SCWCOUNT_RESERVED0_SHIFT                            15

/* rx66_1 :: scwCount :: scwShift [14:08] */
#define RX66_1_SCWCOUNT_SCWSHIFT_MASK                              0x7f00
#define RX66_1_SCWCOUNT_SCWSHIFT_ALIGN                             0
#define RX66_1_SCWCOUNT_SCWSHIFT_BITS                              7
#define RX66_1_SCWCOUNT_SCWSHIFT_SHIFT                             8

/* union - case COMMA_DETECT [07:00] */
/* rx66_1 :: scwCount :: cwCount [07:00] */
#define RX66_1_SCWCOUNT_COMMA_DETECT_CWCOUNT_MASK                  0x00ff
#define RX66_1_SCWCOUNT_COMMA_DETECT_CWCOUNT_ALIGN                 0
#define RX66_1_SCWCOUNT_COMMA_DETECT_CWCOUNT_BITS                  8
#define RX66_1_SCWCOUNT_COMMA_DETECT_CWCOUNT_SHIFT                 0


/* union - case SYNC_ACQD2 [07:00] */
/* rx66_1 :: scwCount :: cwCount [07:00] */
#define RX66_1_SCWCOUNT_SYNC_ACQD2_CWCOUNT_MASK                    0x00ff
#define RX66_1_SCWCOUNT_SYNC_ACQD2_CWCOUNT_ALIGN                   0
#define RX66_1_SCWCOUNT_SYNC_ACQD2_CWCOUNT_BITS                    8
#define RX66_1_SCWCOUNT_SYNC_ACQD2_CWCOUNT_SHIFT                   0



/****************************************************************************
 * rx66_1 :: errCount
 ***************************************************************************/
/* rx66_1 :: errCount :: sync66ErrCount [15:08] */
#define RX66_1_ERRCOUNT_SYNC66ERRCOUNT_MASK                        0xff00
#define RX66_1_ERRCOUNT_SYNC66ERRCOUNT_ALIGN                       0
#define RX66_1_ERRCOUNT_SYNC66ERRCOUNT_BITS                        8
#define RX66_1_ERRCOUNT_SYNC66ERRCOUNT_SHIFT                       8

/* rx66_1 :: errCount :: kcode66ErrCount [07:00] */
#define RX66_1_ERRCOUNT_KCODE66ERRCOUNT_MASK                       0x00ff
#define RX66_1_ERRCOUNT_KCODE66ERRCOUNT_ALIGN                      0
#define RX66_1_ERRCOUNT_KCODE66ERRCOUNT_BITS                       8
#define RX66_1_ERRCOUNT_KCODE66ERRCOUNT_SHIFT                      0


/****************************************************************************
 * Hypercore_USER_rx66_2
 ***************************************************************************/
/****************************************************************************
 * rx66_2 :: Control
 ***************************************************************************/
/* rx66_2 :: Control :: reserved0 [15:10] */
#define RX66_2_CONTROL_RESERVED0_MASK                              0xfc00
#define RX66_2_CONTROL_RESERVED0_ALIGN                             0
#define RX66_2_CONTROL_RESERVED0_BITS                              6
#define RX66_2_CONTROL_RESERVED0_SHIFT                             10

/* rx66_2 :: Control :: rxSeqDoneMask [09:09] */
#define RX66_2_CONTROL_RXSEQDONEMASK_MASK                          0x0200
#define RX66_2_CONTROL_RXSEQDONEMASK_ALIGN                         0
#define RX66_2_CONTROL_RXSEQDONEMASK_BITS                          1
#define RX66_2_CONTROL_RXSEQDONEMASK_SHIFT                         9

/* rx66_2 :: Control :: cwCount_sel [08:08] */
#define RX66_2_CONTROL_CWCOUNT_SEL_MASK                            0x0100
#define RX66_2_CONTROL_CWCOUNT_SEL_ALIGN                           0
#define RX66_2_CONTROL_CWCOUNT_SEL_BITS                            1
#define RX66_2_CONTROL_CWCOUNT_SEL_SHIFT                           8

/* rx66_2 :: Control :: cwCount_en [07:07] */
#define RX66_2_CONTROL_CWCOUNT_EN_MASK                             0x0080
#define RX66_2_CONTROL_CWCOUNT_EN_ALIGN                            0
#define RX66_2_CONTROL_CWCOUNT_EN_BITS                             1
#define RX66_2_CONTROL_CWCOUNT_EN_SHIFT                            7

/* rx66_2 :: Control :: sync66ErrCount_en [06:06] */
#define RX66_2_CONTROL_SYNC66ERRCOUNT_EN_MASK                      0x0040
#define RX66_2_CONTROL_SYNC66ERRCOUNT_EN_ALIGN                     0
#define RX66_2_CONTROL_SYNC66ERRCOUNT_EN_BITS                      1
#define RX66_2_CONTROL_SYNC66ERRCOUNT_EN_SHIFT                     6

/* rx66_2 :: Control :: kcode66ErrCount_en [05:05] */
#define RX66_2_CONTROL_KCODE66ERRCOUNT_EN_MASK                     0x0020
#define RX66_2_CONTROL_KCODE66ERRCOUNT_EN_ALIGN                    0
#define RX66_2_CONTROL_KCODE66ERRCOUNT_EN_BITS                     1
#define RX66_2_CONTROL_KCODE66ERRCOUNT_EN_SHIFT                    5

/* rx66_2 :: Control :: cgbad_kcode66Err_en [04:04] */
#define RX66_2_CONTROL_CGBAD_KCODE66ERR_EN_MASK                    0x0010
#define RX66_2_CONTROL_CGBAD_KCODE66ERR_EN_ALIGN                   0
#define RX66_2_CONTROL_CGBAD_KCODE66ERR_EN_BITS                    1
#define RX66_2_CONTROL_CGBAD_KCODE66ERR_EN_SHIFT                   4

/* rx66_2 :: Control :: descramblerControl [03:02] */
#define RX66_2_CONTROL_DESCRAMBLERCONTROL_MASK                     0x000c
#define RX66_2_CONTROL_DESCRAMBLERCONTROL_ALIGN                    0
#define RX66_2_CONTROL_DESCRAMBLERCONTROL_BITS                     2
#define RX66_2_CONTROL_DESCRAMBLERCONTROL_SHIFT                    2

/* rx66_2 :: Control :: rfifo_sbitclr [01:01] */
#define RX66_2_CONTROL_RFIFO_SBITCLR_MASK                          0x0002
#define RX66_2_CONTROL_RFIFO_SBITCLR_ALIGN                         0
#define RX66_2_CONTROL_RFIFO_SBITCLR_BITS                          1
#define RX66_2_CONTROL_RFIFO_SBITCLR_SHIFT                         1

/* rx66_2 :: Control :: rfifo_afrst_en [00:00] */
#define RX66_2_CONTROL_RFIFO_AFRST_EN_MASK                         0x0001
#define RX66_2_CONTROL_RFIFO_AFRST_EN_ALIGN                        0
#define RX66_2_CONTROL_RFIFO_AFRST_EN_BITS                         1
#define RX66_2_CONTROL_RFIFO_AFRST_EN_SHIFT                        0


/****************************************************************************
 * rx66_2 :: Status
 ***************************************************************************/
/* rx66_2 :: Status :: LOSS_OF_SYNC [15:15] */
#define RX66_2_STATUS_LOSS_OF_SYNC_MASK                            0x8000
#define RX66_2_STATUS_LOSS_OF_SYNC_ALIGN                           0
#define RX66_2_STATUS_LOSS_OF_SYNC_BITS                            1
#define RX66_2_STATUS_LOSS_OF_SYNC_SHIFT                           15

/* rx66_2 :: Status :: COMMA_DETECT [14:14] */
#define RX66_2_STATUS_COMMA_DETECT_MASK                            0x4000
#define RX66_2_STATUS_COMMA_DETECT_ALIGN                           0
#define RX66_2_STATUS_COMMA_DETECT_BITS                            1
#define RX66_2_STATUS_COMMA_DETECT_SHIFT                           14

/* rx66_2 :: Status :: SYNC_ACQD1 [13:13] */
#define RX66_2_STATUS_SYNC_ACQD1_MASK                              0x2000
#define RX66_2_STATUS_SYNC_ACQD1_ALIGN                             0
#define RX66_2_STATUS_SYNC_ACQD1_BITS                              1
#define RX66_2_STATUS_SYNC_ACQD1_SHIFT                             13

/* rx66_2 :: Status :: SYNC_ACQD2 [12:12] */
#define RX66_2_STATUS_SYNC_ACQD2_MASK                              0x1000
#define RX66_2_STATUS_SYNC_ACQD2_ALIGN                             0
#define RX66_2_STATUS_SYNC_ACQD2_BITS                              1
#define RX66_2_STATUS_SYNC_ACQD2_SHIFT                             12

/* rx66_2 :: Status :: reserved0 [11:04] */
#define RX66_2_STATUS_RESERVED0_MASK                               0x0ff0
#define RX66_2_STATUS_RESERVED0_ALIGN                              0
#define RX66_2_STATUS_RESERVED0_BITS                               8
#define RX66_2_STATUS_RESERVED0_SHIFT                              4

/* rx66_2 :: Status :: syncDone [03:03] */
#define RX66_2_STATUS_SYNCDONE_MASK                                0x0008
#define RX66_2_STATUS_SYNCDONE_ALIGN                               0
#define RX66_2_STATUS_SYNCDONE_BITS                                1
#define RX66_2_STATUS_SYNCDONE_SHIFT                               3

/* rx66_2 :: Status :: unflow [02:02] */
#define RX66_2_STATUS_UNFLOW_MASK                                  0x0004
#define RX66_2_STATUS_UNFLOW_ALIGN                                 0
#define RX66_2_STATUS_UNFLOW_BITS                                  1
#define RX66_2_STATUS_UNFLOW_SHIFT                                 2

/* rx66_2 :: Status :: ovflow [01:01] */
#define RX66_2_STATUS_OVFLOW_MASK                                  0x0002
#define RX66_2_STATUS_OVFLOW_ALIGN                                 0
#define RX66_2_STATUS_OVFLOW_BITS                                  1
#define RX66_2_STATUS_OVFLOW_SHIFT                                 1

/* rx66_2 :: Status :: ferr [00:00] */
#define RX66_2_STATUS_FERR_MASK                                    0x0001
#define RX66_2_STATUS_FERR_ALIGN                                   0
#define RX66_2_STATUS_FERR_BITS                                    1
#define RX66_2_STATUS_FERR_SHIFT                                   0


/****************************************************************************
 * rx66_2 :: scw0
 ***************************************************************************/
/* rx66_2 :: scw0 :: scw0 [15:00] */
#define RX66_2_SCW0_SCW0_MASK                                      0xffff
#define RX66_2_SCW0_SCW0_ALIGN                                     0
#define RX66_2_SCW0_SCW0_BITS                                      16
#define RX66_2_SCW0_SCW0_SHIFT                                     0


/****************************************************************************
 * rx66_2 :: scw1
 ***************************************************************************/
/* rx66_2 :: scw1 :: scw1 [15:00] */
#define RX66_2_SCW1_SCW1_MASK                                      0xffff
#define RX66_2_SCW1_SCW1_ALIGN                                     0
#define RX66_2_SCW1_SCW1_BITS                                      16
#define RX66_2_SCW1_SCW1_SHIFT                                     0


/****************************************************************************
 * rx66_2 :: scw2
 ***************************************************************************/
/* rx66_2 :: scw2 :: scw2 [15:00] */
#define RX66_2_SCW2_SCW2_MASK                                      0xffff
#define RX66_2_SCW2_SCW2_ALIGN                                     0
#define RX66_2_SCW2_SCW2_BITS                                      16
#define RX66_2_SCW2_SCW2_SHIFT                                     0


/****************************************************************************
 * rx66_2 :: scw3
 ***************************************************************************/
/* rx66_2 :: scw3 :: scw3 [15:00] */
#define RX66_2_SCW3_SCW3_MASK                                      0xffff
#define RX66_2_SCW3_SCW3_ALIGN                                     0
#define RX66_2_SCW3_SCW3_BITS                                      16
#define RX66_2_SCW3_SCW3_SHIFT                                     0


/****************************************************************************
 * rx66_2 :: scw0_mask
 ***************************************************************************/
/* rx66_2 :: scw0_mask :: scw0_mask [15:00] */
#define RX66_2_SCW0_MASK_SCW0_MASK_MASK                            0xffff
#define RX66_2_SCW0_MASK_SCW0_MASK_ALIGN                           0
#define RX66_2_SCW0_MASK_SCW0_MASK_BITS                            16
#define RX66_2_SCW0_MASK_SCW0_MASK_SHIFT                           0


/****************************************************************************
 * rx66_2 :: scw1_mask
 ***************************************************************************/
/* rx66_2 :: scw1_mask :: scw1_mask [15:00] */
#define RX66_2_SCW1_MASK_SCW1_MASK_MASK                            0xffff
#define RX66_2_SCW1_MASK_SCW1_MASK_ALIGN                           0
#define RX66_2_SCW1_MASK_SCW1_MASK_BITS                            16
#define RX66_2_SCW1_MASK_SCW1_MASK_SHIFT                           0


/****************************************************************************
 * rx66_2 :: scw2_mask
 ***************************************************************************/
/* rx66_2 :: scw2_mask :: scw2_mask [15:00] */
#define RX66_2_SCW2_MASK_SCW2_MASK_MASK                            0xffff
#define RX66_2_SCW2_MASK_SCW2_MASK_ALIGN                           0
#define RX66_2_SCW2_MASK_SCW2_MASK_BITS                            16
#define RX66_2_SCW2_MASK_SCW2_MASK_SHIFT                           0


/****************************************************************************
 * rx66_2 :: scw3_mask
 ***************************************************************************/
/* rx66_2 :: scw3_mask :: scw3_mask [15:00] */
#define RX66_2_SCW3_MASK_SCW3_MASK_MASK                            0xffff
#define RX66_2_SCW3_MASK_SCW3_MASK_ALIGN                           0
#define RX66_2_SCW3_MASK_SCW3_MASK_BITS                            16
#define RX66_2_SCW3_MASK_SCW3_MASK_SHIFT                           0


/****************************************************************************
 * rx66_2 :: syncbits
 ***************************************************************************/
/* rx66_2 :: syncbits :: reserved0 [15:04] */
#define RX66_2_SYNCBITS_RESERVED0_MASK                             0xfff0
#define RX66_2_SYNCBITS_RESERVED0_ALIGN                            0
#define RX66_2_SYNCBITS_RESERVED0_BITS                             12
#define RX66_2_SYNCBITS_RESERVED0_SHIFT                            4

/* rx66_2 :: syncbits :: syncbits [03:02] */
#define RX66_2_SYNCBITS_SYNCBITS_MASK                              0x000c
#define RX66_2_SYNCBITS_SYNCBITS_ALIGN                             0
#define RX66_2_SYNCBITS_SYNCBITS_BITS                              2
#define RX66_2_SYNCBITS_SYNCBITS_SHIFT                             2

/* rx66_2 :: syncbits :: syncbits_mask [01:00] */
#define RX66_2_SYNCBITS_SYNCBITS_MASK_MASK                         0x0003
#define RX66_2_SYNCBITS_SYNCBITS_MASK_ALIGN                        0
#define RX66_2_SYNCBITS_SYNCBITS_MASK_BITS                         2
#define RX66_2_SYNCBITS_SYNCBITS_MASK_SHIFT                        0


/****************************************************************************
 * rx66_2 :: scwControl
 ***************************************************************************/
/* rx66_2 :: scwControl :: reserved0 [15:15] */
#define RX66_2_SCWCONTROL_RESERVED0_MASK                           0x8000
#define RX66_2_SCWCONTROL_RESERVED0_ALIGN                          0
#define RX66_2_SCWCONTROL_RESERVED0_BITS                           1
#define RX66_2_SCWCONTROL_RESERVED0_SHIFT                          15

/* rx66_2 :: scwControl :: scwCount [14:10] */
#define RX66_2_SCWCONTROL_SCWCOUNT_MASK                            0x7c00
#define RX66_2_SCWCONTROL_SCWCOUNT_ALIGN                           0
#define RX66_2_SCWCONTROL_SCWCOUNT_BITS                            5
#define RX66_2_SCWCONTROL_SCWCOUNT_SHIFT                           10

/* rx66_2 :: scwControl :: gcwCount [09:05] */
#define RX66_2_SCWCONTROL_GCWCOUNT_MASK                            0x03e0
#define RX66_2_SCWCONTROL_GCWCOUNT_ALIGN                           0
#define RX66_2_SCWCONTROL_GCWCOUNT_BITS                            5
#define RX66_2_SCWCONTROL_GCWCOUNT_SHIFT                           5

/* rx66_2 :: scwControl :: hystCount [04:00] */
#define RX66_2_SCWCONTROL_HYSTCOUNT_MASK                           0x001f
#define RX66_2_SCWCONTROL_HYSTCOUNT_ALIGN                          0
#define RX66_2_SCWCONTROL_HYSTCOUNT_BITS                           5
#define RX66_2_SCWCONTROL_HYSTCOUNT_SHIFT                          0


/****************************************************************************
 * rx66_2 :: scwCount
 ***************************************************************************/
/* rx66_2 :: scwCount :: reserved0 [15:15] */
#define RX66_2_SCWCOUNT_RESERVED0_MASK                             0x8000
#define RX66_2_SCWCOUNT_RESERVED0_ALIGN                            0
#define RX66_2_SCWCOUNT_RESERVED0_BITS                             1
#define RX66_2_SCWCOUNT_RESERVED0_SHIFT                            15

/* rx66_2 :: scwCount :: scwShift [14:08] */
#define RX66_2_SCWCOUNT_SCWSHIFT_MASK                              0x7f00
#define RX66_2_SCWCOUNT_SCWSHIFT_ALIGN                             0
#define RX66_2_SCWCOUNT_SCWSHIFT_BITS                              7
#define RX66_2_SCWCOUNT_SCWSHIFT_SHIFT                             8

/* union - case COMMA_DETECT [07:00] */
/* rx66_2 :: scwCount :: cwCount [07:00] */
#define RX66_2_SCWCOUNT_COMMA_DETECT_CWCOUNT_MASK                  0x00ff
#define RX66_2_SCWCOUNT_COMMA_DETECT_CWCOUNT_ALIGN                 0
#define RX66_2_SCWCOUNT_COMMA_DETECT_CWCOUNT_BITS                  8
#define RX66_2_SCWCOUNT_COMMA_DETECT_CWCOUNT_SHIFT                 0


/* union - case SYNC_ACQD2 [07:00] */
/* rx66_2 :: scwCount :: cwCount [07:00] */
#define RX66_2_SCWCOUNT_SYNC_ACQD2_CWCOUNT_MASK                    0x00ff
#define RX66_2_SCWCOUNT_SYNC_ACQD2_CWCOUNT_ALIGN                   0
#define RX66_2_SCWCOUNT_SYNC_ACQD2_CWCOUNT_BITS                    8
#define RX66_2_SCWCOUNT_SYNC_ACQD2_CWCOUNT_SHIFT                   0



/****************************************************************************
 * rx66_2 :: errCount
 ***************************************************************************/
/* rx66_2 :: errCount :: sync66ErrCount [15:08] */
#define RX66_2_ERRCOUNT_SYNC66ERRCOUNT_MASK                        0xff00
#define RX66_2_ERRCOUNT_SYNC66ERRCOUNT_ALIGN                       0
#define RX66_2_ERRCOUNT_SYNC66ERRCOUNT_BITS                        8
#define RX66_2_ERRCOUNT_SYNC66ERRCOUNT_SHIFT                       8

/* rx66_2 :: errCount :: kcode66ErrCount [07:00] */
#define RX66_2_ERRCOUNT_KCODE66ERRCOUNT_MASK                       0x00ff
#define RX66_2_ERRCOUNT_KCODE66ERRCOUNT_ALIGN                      0
#define RX66_2_ERRCOUNT_KCODE66ERRCOUNT_BITS                       8
#define RX66_2_ERRCOUNT_KCODE66ERRCOUNT_SHIFT                      0


/****************************************************************************
 * Hypercore_USER_rx66_3
 ***************************************************************************/
/****************************************************************************
 * rx66_3 :: Control
 ***************************************************************************/
/* rx66_3 :: Control :: reserved0 [15:10] */
#define RX66_3_CONTROL_RESERVED0_MASK                              0xfc00
#define RX66_3_CONTROL_RESERVED0_ALIGN                             0
#define RX66_3_CONTROL_RESERVED0_BITS                              6
#define RX66_3_CONTROL_RESERVED0_SHIFT                             10

/* rx66_3 :: Control :: rxSeqDoneMask [09:09] */
#define RX66_3_CONTROL_RXSEQDONEMASK_MASK                          0x0200
#define RX66_3_CONTROL_RXSEQDONEMASK_ALIGN                         0
#define RX66_3_CONTROL_RXSEQDONEMASK_BITS                          1
#define RX66_3_CONTROL_RXSEQDONEMASK_SHIFT                         9

/* rx66_3 :: Control :: cwCount_sel [08:08] */
#define RX66_3_CONTROL_CWCOUNT_SEL_MASK                            0x0100
#define RX66_3_CONTROL_CWCOUNT_SEL_ALIGN                           0
#define RX66_3_CONTROL_CWCOUNT_SEL_BITS                            1
#define RX66_3_CONTROL_CWCOUNT_SEL_SHIFT                           8

/* rx66_3 :: Control :: cwCount_en [07:07] */
#define RX66_3_CONTROL_CWCOUNT_EN_MASK                             0x0080
#define RX66_3_CONTROL_CWCOUNT_EN_ALIGN                            0
#define RX66_3_CONTROL_CWCOUNT_EN_BITS                             1
#define RX66_3_CONTROL_CWCOUNT_EN_SHIFT                            7

/* rx66_3 :: Control :: sync66ErrCount_en [06:06] */
#define RX66_3_CONTROL_SYNC66ERRCOUNT_EN_MASK                      0x0040
#define RX66_3_CONTROL_SYNC66ERRCOUNT_EN_ALIGN                     0
#define RX66_3_CONTROL_SYNC66ERRCOUNT_EN_BITS                      1
#define RX66_3_CONTROL_SYNC66ERRCOUNT_EN_SHIFT                     6

/* rx66_3 :: Control :: kcode66ErrCount_en [05:05] */
#define RX66_3_CONTROL_KCODE66ERRCOUNT_EN_MASK                     0x0020
#define RX66_3_CONTROL_KCODE66ERRCOUNT_EN_ALIGN                    0
#define RX66_3_CONTROL_KCODE66ERRCOUNT_EN_BITS                     1
#define RX66_3_CONTROL_KCODE66ERRCOUNT_EN_SHIFT                    5

/* rx66_3 :: Control :: cgbad_kcode66Err_en [04:04] */
#define RX66_3_CONTROL_CGBAD_KCODE66ERR_EN_MASK                    0x0010
#define RX66_3_CONTROL_CGBAD_KCODE66ERR_EN_ALIGN                   0
#define RX66_3_CONTROL_CGBAD_KCODE66ERR_EN_BITS                    1
#define RX66_3_CONTROL_CGBAD_KCODE66ERR_EN_SHIFT                   4

/* rx66_3 :: Control :: descramblerControl [03:02] */
#define RX66_3_CONTROL_DESCRAMBLERCONTROL_MASK                     0x000c
#define RX66_3_CONTROL_DESCRAMBLERCONTROL_ALIGN                    0
#define RX66_3_CONTROL_DESCRAMBLERCONTROL_BITS                     2
#define RX66_3_CONTROL_DESCRAMBLERCONTROL_SHIFT                    2

/* rx66_3 :: Control :: rfifo_sbitclr [01:01] */
#define RX66_3_CONTROL_RFIFO_SBITCLR_MASK                          0x0002
#define RX66_3_CONTROL_RFIFO_SBITCLR_ALIGN                         0
#define RX66_3_CONTROL_RFIFO_SBITCLR_BITS                          1
#define RX66_3_CONTROL_RFIFO_SBITCLR_SHIFT                         1

/* rx66_3 :: Control :: rfifo_afrst_en [00:00] */
#define RX66_3_CONTROL_RFIFO_AFRST_EN_MASK                         0x0001
#define RX66_3_CONTROL_RFIFO_AFRST_EN_ALIGN                        0
#define RX66_3_CONTROL_RFIFO_AFRST_EN_BITS                         1
#define RX66_3_CONTROL_RFIFO_AFRST_EN_SHIFT                        0


/****************************************************************************
 * rx66_3 :: Status
 ***************************************************************************/
/* rx66_3 :: Status :: LOSS_OF_SYNC [15:15] */
#define RX66_3_STATUS_LOSS_OF_SYNC_MASK                            0x8000
#define RX66_3_STATUS_LOSS_OF_SYNC_ALIGN                           0
#define RX66_3_STATUS_LOSS_OF_SYNC_BITS                            1
#define RX66_3_STATUS_LOSS_OF_SYNC_SHIFT                           15

/* rx66_3 :: Status :: COMMA_DETECT [14:14] */
#define RX66_3_STATUS_COMMA_DETECT_MASK                            0x4000
#define RX66_3_STATUS_COMMA_DETECT_ALIGN                           0
#define RX66_3_STATUS_COMMA_DETECT_BITS                            1
#define RX66_3_STATUS_COMMA_DETECT_SHIFT                           14

/* rx66_3 :: Status :: SYNC_ACQD1 [13:13] */
#define RX66_3_STATUS_SYNC_ACQD1_MASK                              0x2000
#define RX66_3_STATUS_SYNC_ACQD1_ALIGN                             0
#define RX66_3_STATUS_SYNC_ACQD1_BITS                              1
#define RX66_3_STATUS_SYNC_ACQD1_SHIFT                             13

/* rx66_3 :: Status :: SYNC_ACQD2 [12:12] */
#define RX66_3_STATUS_SYNC_ACQD2_MASK                              0x1000
#define RX66_3_STATUS_SYNC_ACQD2_ALIGN                             0
#define RX66_3_STATUS_SYNC_ACQD2_BITS                              1
#define RX66_3_STATUS_SYNC_ACQD2_SHIFT                             12

/* rx66_3 :: Status :: reserved0 [11:04] */
#define RX66_3_STATUS_RESERVED0_MASK                               0x0ff0
#define RX66_3_STATUS_RESERVED0_ALIGN                              0
#define RX66_3_STATUS_RESERVED0_BITS                               8
#define RX66_3_STATUS_RESERVED0_SHIFT                              4

/* rx66_3 :: Status :: syncDone [03:03] */
#define RX66_3_STATUS_SYNCDONE_MASK                                0x0008
#define RX66_3_STATUS_SYNCDONE_ALIGN                               0
#define RX66_3_STATUS_SYNCDONE_BITS                                1
#define RX66_3_STATUS_SYNCDONE_SHIFT                               3

/* rx66_3 :: Status :: unflow [02:02] */
#define RX66_3_STATUS_UNFLOW_MASK                                  0x0004
#define RX66_3_STATUS_UNFLOW_ALIGN                                 0
#define RX66_3_STATUS_UNFLOW_BITS                                  1
#define RX66_3_STATUS_UNFLOW_SHIFT                                 2

/* rx66_3 :: Status :: ovflow [01:01] */
#define RX66_3_STATUS_OVFLOW_MASK                                  0x0002
#define RX66_3_STATUS_OVFLOW_ALIGN                                 0
#define RX66_3_STATUS_OVFLOW_BITS                                  1
#define RX66_3_STATUS_OVFLOW_SHIFT                                 1

/* rx66_3 :: Status :: ferr [00:00] */
#define RX66_3_STATUS_FERR_MASK                                    0x0001
#define RX66_3_STATUS_FERR_ALIGN                                   0
#define RX66_3_STATUS_FERR_BITS                                    1
#define RX66_3_STATUS_FERR_SHIFT                                   0


/****************************************************************************
 * rx66_3 :: scw0
 ***************************************************************************/
/* rx66_3 :: scw0 :: scw0 [15:00] */
#define RX66_3_SCW0_SCW0_MASK                                      0xffff
#define RX66_3_SCW0_SCW0_ALIGN                                     0
#define RX66_3_SCW0_SCW0_BITS                                      16
#define RX66_3_SCW0_SCW0_SHIFT                                     0


/****************************************************************************
 * rx66_3 :: scw1
 ***************************************************************************/
/* rx66_3 :: scw1 :: scw1 [15:00] */
#define RX66_3_SCW1_SCW1_MASK                                      0xffff
#define RX66_3_SCW1_SCW1_ALIGN                                     0
#define RX66_3_SCW1_SCW1_BITS                                      16
#define RX66_3_SCW1_SCW1_SHIFT                                     0


/****************************************************************************
 * rx66_3 :: scw2
 ***************************************************************************/
/* rx66_3 :: scw2 :: scw2 [15:00] */
#define RX66_3_SCW2_SCW2_MASK                                      0xffff
#define RX66_3_SCW2_SCW2_ALIGN                                     0
#define RX66_3_SCW2_SCW2_BITS                                      16
#define RX66_3_SCW2_SCW2_SHIFT                                     0


/****************************************************************************
 * rx66_3 :: scw3
 ***************************************************************************/
/* rx66_3 :: scw3 :: scw3 [15:00] */
#define RX66_3_SCW3_SCW3_MASK                                      0xffff
#define RX66_3_SCW3_SCW3_ALIGN                                     0
#define RX66_3_SCW3_SCW3_BITS                                      16
#define RX66_3_SCW3_SCW3_SHIFT                                     0


/****************************************************************************
 * rx66_3 :: scw0_mask
 ***************************************************************************/
/* rx66_3 :: scw0_mask :: scw0_mask [15:00] */
#define RX66_3_SCW0_MASK_SCW0_MASK_MASK                            0xffff
#define RX66_3_SCW0_MASK_SCW0_MASK_ALIGN                           0
#define RX66_3_SCW0_MASK_SCW0_MASK_BITS                            16
#define RX66_3_SCW0_MASK_SCW0_MASK_SHIFT                           0


/****************************************************************************
 * rx66_3 :: scw1_mask
 ***************************************************************************/
/* rx66_3 :: scw1_mask :: scw1_mask [15:00] */
#define RX66_3_SCW1_MASK_SCW1_MASK_MASK                            0xffff
#define RX66_3_SCW1_MASK_SCW1_MASK_ALIGN                           0
#define RX66_3_SCW1_MASK_SCW1_MASK_BITS                            16
#define RX66_3_SCW1_MASK_SCW1_MASK_SHIFT                           0


/****************************************************************************
 * rx66_3 :: scw2_mask
 ***************************************************************************/
/* rx66_3 :: scw2_mask :: scw2_mask [15:00] */
#define RX66_3_SCW2_MASK_SCW2_MASK_MASK                            0xffff
#define RX66_3_SCW2_MASK_SCW2_MASK_ALIGN                           0
#define RX66_3_SCW2_MASK_SCW2_MASK_BITS                            16
#define RX66_3_SCW2_MASK_SCW2_MASK_SHIFT                           0


/****************************************************************************
 * rx66_3 :: scw3_mask
 ***************************************************************************/
/* rx66_3 :: scw3_mask :: scw3_mask [15:00] */
#define RX66_3_SCW3_MASK_SCW3_MASK_MASK                            0xffff
#define RX66_3_SCW3_MASK_SCW3_MASK_ALIGN                           0
#define RX66_3_SCW3_MASK_SCW3_MASK_BITS                            16
#define RX66_3_SCW3_MASK_SCW3_MASK_SHIFT                           0


/****************************************************************************
 * rx66_3 :: syncbits
 ***************************************************************************/
/* rx66_3 :: syncbits :: reserved0 [15:04] */
#define RX66_3_SYNCBITS_RESERVED0_MASK                             0xfff0
#define RX66_3_SYNCBITS_RESERVED0_ALIGN                            0
#define RX66_3_SYNCBITS_RESERVED0_BITS                             12
#define RX66_3_SYNCBITS_RESERVED0_SHIFT                            4

/* rx66_3 :: syncbits :: syncbits [03:02] */
#define RX66_3_SYNCBITS_SYNCBITS_MASK                              0x000c
#define RX66_3_SYNCBITS_SYNCBITS_ALIGN                             0
#define RX66_3_SYNCBITS_SYNCBITS_BITS                              2
#define RX66_3_SYNCBITS_SYNCBITS_SHIFT                             2

/* rx66_3 :: syncbits :: syncbits_mask [01:00] */
#define RX66_3_SYNCBITS_SYNCBITS_MASK_MASK                         0x0003
#define RX66_3_SYNCBITS_SYNCBITS_MASK_ALIGN                        0
#define RX66_3_SYNCBITS_SYNCBITS_MASK_BITS                         2
#define RX66_3_SYNCBITS_SYNCBITS_MASK_SHIFT                        0


/****************************************************************************
 * rx66_3 :: scwControl
 ***************************************************************************/
/* rx66_3 :: scwControl :: reserved0 [15:15] */
#define RX66_3_SCWCONTROL_RESERVED0_MASK                           0x8000
#define RX66_3_SCWCONTROL_RESERVED0_ALIGN                          0
#define RX66_3_SCWCONTROL_RESERVED0_BITS                           1
#define RX66_3_SCWCONTROL_RESERVED0_SHIFT                          15

/* rx66_3 :: scwControl :: scwCount [14:10] */
#define RX66_3_SCWCONTROL_SCWCOUNT_MASK                            0x7c00
#define RX66_3_SCWCONTROL_SCWCOUNT_ALIGN                           0
#define RX66_3_SCWCONTROL_SCWCOUNT_BITS                            5
#define RX66_3_SCWCONTROL_SCWCOUNT_SHIFT                           10

/* rx66_3 :: scwControl :: gcwCount [09:05] */
#define RX66_3_SCWCONTROL_GCWCOUNT_MASK                            0x03e0
#define RX66_3_SCWCONTROL_GCWCOUNT_ALIGN                           0
#define RX66_3_SCWCONTROL_GCWCOUNT_BITS                            5
#define RX66_3_SCWCONTROL_GCWCOUNT_SHIFT                           5

/* rx66_3 :: scwControl :: hystCount [04:00] */
#define RX66_3_SCWCONTROL_HYSTCOUNT_MASK                           0x001f
#define RX66_3_SCWCONTROL_HYSTCOUNT_ALIGN                          0
#define RX66_3_SCWCONTROL_HYSTCOUNT_BITS                           5
#define RX66_3_SCWCONTROL_HYSTCOUNT_SHIFT                          0


/****************************************************************************
 * rx66_3 :: scwCount
 ***************************************************************************/
/* rx66_3 :: scwCount :: reserved0 [15:15] */
#define RX66_3_SCWCOUNT_RESERVED0_MASK                             0x8000
#define RX66_3_SCWCOUNT_RESERVED0_ALIGN                            0
#define RX66_3_SCWCOUNT_RESERVED0_BITS                             1
#define RX66_3_SCWCOUNT_RESERVED0_SHIFT                            15

/* rx66_3 :: scwCount :: scwShift [14:08] */
#define RX66_3_SCWCOUNT_SCWSHIFT_MASK                              0x7f00
#define RX66_3_SCWCOUNT_SCWSHIFT_ALIGN                             0
#define RX66_3_SCWCOUNT_SCWSHIFT_BITS                              7
#define RX66_3_SCWCOUNT_SCWSHIFT_SHIFT                             8

/* union - case COMMA_DETECT [07:00] */
/* rx66_3 :: scwCount :: cwCount [07:00] */
#define RX66_3_SCWCOUNT_COMMA_DETECT_CWCOUNT_MASK                  0x00ff
#define RX66_3_SCWCOUNT_COMMA_DETECT_CWCOUNT_ALIGN                 0
#define RX66_3_SCWCOUNT_COMMA_DETECT_CWCOUNT_BITS                  8
#define RX66_3_SCWCOUNT_COMMA_DETECT_CWCOUNT_SHIFT                 0


/* union - case SYNC_ACQD2 [07:00] */
/* rx66_3 :: scwCount :: cwCount [07:00] */
#define RX66_3_SCWCOUNT_SYNC_ACQD2_CWCOUNT_MASK                    0x00ff
#define RX66_3_SCWCOUNT_SYNC_ACQD2_CWCOUNT_ALIGN                   0
#define RX66_3_SCWCOUNT_SYNC_ACQD2_CWCOUNT_BITS                    8
#define RX66_3_SCWCOUNT_SYNC_ACQD2_CWCOUNT_SHIFT                   0



/****************************************************************************
 * rx66_3 :: errCount
 ***************************************************************************/
/* rx66_3 :: errCount :: sync66ErrCount [15:08] */
#define RX66_3_ERRCOUNT_SYNC66ERRCOUNT_MASK                        0xff00
#define RX66_3_ERRCOUNT_SYNC66ERRCOUNT_ALIGN                       0
#define RX66_3_ERRCOUNT_SYNC66ERRCOUNT_BITS                        8
#define RX66_3_ERRCOUNT_SYNC66ERRCOUNT_SHIFT                       8

/* rx66_3 :: errCount :: kcode66ErrCount [07:00] */
#define RX66_3_ERRCOUNT_KCODE66ERRCOUNT_MASK                       0x00ff
#define RX66_3_ERRCOUNT_KCODE66ERRCOUNT_ALIGN                      0
#define RX66_3_ERRCOUNT_KCODE66ERRCOUNT_BITS                       8
#define RX66_3_ERRCOUNT_KCODE66ERRCOUNT_SHIFT                      0


/****************************************************************************
 * Hypercore_USER_rx66_A
 ***************************************************************************/
/****************************************************************************
 * rx66_A :: Control
 ***************************************************************************/
/* rx66_A :: Control :: reserved0 [15:10] */
#define RX66_A_CONTROL_RESERVED0_MASK                              0xfc00
#define RX66_A_CONTROL_RESERVED0_ALIGN                             0
#define RX66_A_CONTROL_RESERVED0_BITS                              6
#define RX66_A_CONTROL_RESERVED0_SHIFT                             10

/* rx66_A :: Control :: rxSeqDoneMask [09:09] */
#define RX66_A_CONTROL_RXSEQDONEMASK_MASK                          0x0200
#define RX66_A_CONTROL_RXSEQDONEMASK_ALIGN                         0
#define RX66_A_CONTROL_RXSEQDONEMASK_BITS                          1
#define RX66_A_CONTROL_RXSEQDONEMASK_SHIFT                         9

/* rx66_A :: Control :: cwCount_sel [08:08] */
#define RX66_A_CONTROL_CWCOUNT_SEL_MASK                            0x0100
#define RX66_A_CONTROL_CWCOUNT_SEL_ALIGN                           0
#define RX66_A_CONTROL_CWCOUNT_SEL_BITS                            1
#define RX66_A_CONTROL_CWCOUNT_SEL_SHIFT                           8

/* rx66_A :: Control :: cwCount_en [07:07] */
#define RX66_A_CONTROL_CWCOUNT_EN_MASK                             0x0080
#define RX66_A_CONTROL_CWCOUNT_EN_ALIGN                            0
#define RX66_A_CONTROL_CWCOUNT_EN_BITS                             1
#define RX66_A_CONTROL_CWCOUNT_EN_SHIFT                            7

/* rx66_A :: Control :: sync66ErrCount_en [06:06] */
#define RX66_A_CONTROL_SYNC66ERRCOUNT_EN_MASK                      0x0040
#define RX66_A_CONTROL_SYNC66ERRCOUNT_EN_ALIGN                     0
#define RX66_A_CONTROL_SYNC66ERRCOUNT_EN_BITS                      1
#define RX66_A_CONTROL_SYNC66ERRCOUNT_EN_SHIFT                     6

/* rx66_A :: Control :: kcode66ErrCount_en [05:05] */
#define RX66_A_CONTROL_KCODE66ERRCOUNT_EN_MASK                     0x0020
#define RX66_A_CONTROL_KCODE66ERRCOUNT_EN_ALIGN                    0
#define RX66_A_CONTROL_KCODE66ERRCOUNT_EN_BITS                     1
#define RX66_A_CONTROL_KCODE66ERRCOUNT_EN_SHIFT                    5

/* rx66_A :: Control :: cgbad_kcode66Err_en [04:04] */
#define RX66_A_CONTROL_CGBAD_KCODE66ERR_EN_MASK                    0x0010
#define RX66_A_CONTROL_CGBAD_KCODE66ERR_EN_ALIGN                   0
#define RX66_A_CONTROL_CGBAD_KCODE66ERR_EN_BITS                    1
#define RX66_A_CONTROL_CGBAD_KCODE66ERR_EN_SHIFT                   4

/* rx66_A :: Control :: descramblerControl [03:02] */
#define RX66_A_CONTROL_DESCRAMBLERCONTROL_MASK                     0x000c
#define RX66_A_CONTROL_DESCRAMBLERCONTROL_ALIGN                    0
#define RX66_A_CONTROL_DESCRAMBLERCONTROL_BITS                     2
#define RX66_A_CONTROL_DESCRAMBLERCONTROL_SHIFT                    2

/* rx66_A :: Control :: rfifo_sbitclr [01:01] */
#define RX66_A_CONTROL_RFIFO_SBITCLR_MASK                          0x0002
#define RX66_A_CONTROL_RFIFO_SBITCLR_ALIGN                         0
#define RX66_A_CONTROL_RFIFO_SBITCLR_BITS                          1
#define RX66_A_CONTROL_RFIFO_SBITCLR_SHIFT                         1

/* rx66_A :: Control :: rfifo_afrst_en [00:00] */
#define RX66_A_CONTROL_RFIFO_AFRST_EN_MASK                         0x0001
#define RX66_A_CONTROL_RFIFO_AFRST_EN_ALIGN                        0
#define RX66_A_CONTROL_RFIFO_AFRST_EN_BITS                         1
#define RX66_A_CONTROL_RFIFO_AFRST_EN_SHIFT                        0


/****************************************************************************
 * rx66_A :: Status
 ***************************************************************************/
/* rx66_A :: Status :: LOSS_OF_SYNC [15:15] */
#define RX66_A_STATUS_LOSS_OF_SYNC_MASK                            0x8000
#define RX66_A_STATUS_LOSS_OF_SYNC_ALIGN                           0
#define RX66_A_STATUS_LOSS_OF_SYNC_BITS                            1
#define RX66_A_STATUS_LOSS_OF_SYNC_SHIFT                           15

/* rx66_A :: Status :: COMMA_DETECT [14:14] */
#define RX66_A_STATUS_COMMA_DETECT_MASK                            0x4000
#define RX66_A_STATUS_COMMA_DETECT_ALIGN                           0
#define RX66_A_STATUS_COMMA_DETECT_BITS                            1
#define RX66_A_STATUS_COMMA_DETECT_SHIFT                           14

/* rx66_A :: Status :: SYNC_ACQD1 [13:13] */
#define RX66_A_STATUS_SYNC_ACQD1_MASK                              0x2000
#define RX66_A_STATUS_SYNC_ACQD1_ALIGN                             0
#define RX66_A_STATUS_SYNC_ACQD1_BITS                              1
#define RX66_A_STATUS_SYNC_ACQD1_SHIFT                             13

/* rx66_A :: Status :: SYNC_ACQD2 [12:12] */
#define RX66_A_STATUS_SYNC_ACQD2_MASK                              0x1000
#define RX66_A_STATUS_SYNC_ACQD2_ALIGN                             0
#define RX66_A_STATUS_SYNC_ACQD2_BITS                              1
#define RX66_A_STATUS_SYNC_ACQD2_SHIFT                             12

/* rx66_A :: Status :: reserved0 [11:04] */
#define RX66_A_STATUS_RESERVED0_MASK                               0x0ff0
#define RX66_A_STATUS_RESERVED0_ALIGN                              0
#define RX66_A_STATUS_RESERVED0_BITS                               8
#define RX66_A_STATUS_RESERVED0_SHIFT                              4

/* rx66_A :: Status :: syncDone [03:03] */
#define RX66_A_STATUS_SYNCDONE_MASK                                0x0008
#define RX66_A_STATUS_SYNCDONE_ALIGN                               0
#define RX66_A_STATUS_SYNCDONE_BITS                                1
#define RX66_A_STATUS_SYNCDONE_SHIFT                               3

/* rx66_A :: Status :: unflow [02:02] */
#define RX66_A_STATUS_UNFLOW_MASK                                  0x0004
#define RX66_A_STATUS_UNFLOW_ALIGN                                 0
#define RX66_A_STATUS_UNFLOW_BITS                                  1
#define RX66_A_STATUS_UNFLOW_SHIFT                                 2

/* rx66_A :: Status :: ovflow [01:01] */
#define RX66_A_STATUS_OVFLOW_MASK                                  0x0002
#define RX66_A_STATUS_OVFLOW_ALIGN                                 0
#define RX66_A_STATUS_OVFLOW_BITS                                  1
#define RX66_A_STATUS_OVFLOW_SHIFT                                 1

/* rx66_A :: Status :: ferr [00:00] */
#define RX66_A_STATUS_FERR_MASK                                    0x0001
#define RX66_A_STATUS_FERR_ALIGN                                   0
#define RX66_A_STATUS_FERR_BITS                                    1
#define RX66_A_STATUS_FERR_SHIFT                                   0


/****************************************************************************
 * rx66_A :: scw0
 ***************************************************************************/
/* rx66_A :: scw0 :: scw0 [15:00] */
#define RX66_A_SCW0_SCW0_MASK                                      0xffff
#define RX66_A_SCW0_SCW0_ALIGN                                     0
#define RX66_A_SCW0_SCW0_BITS                                      16
#define RX66_A_SCW0_SCW0_SHIFT                                     0


/****************************************************************************
 * rx66_A :: scw1
 ***************************************************************************/
/* rx66_A :: scw1 :: scw1 [15:00] */
#define RX66_A_SCW1_SCW1_MASK                                      0xffff
#define RX66_A_SCW1_SCW1_ALIGN                                     0
#define RX66_A_SCW1_SCW1_BITS                                      16
#define RX66_A_SCW1_SCW1_SHIFT                                     0


/****************************************************************************
 * rx66_A :: scw2
 ***************************************************************************/
/* rx66_A :: scw2 :: scw2 [15:00] */
#define RX66_A_SCW2_SCW2_MASK                                      0xffff
#define RX66_A_SCW2_SCW2_ALIGN                                     0
#define RX66_A_SCW2_SCW2_BITS                                      16
#define RX66_A_SCW2_SCW2_SHIFT                                     0


/****************************************************************************
 * rx66_A :: scw3
 ***************************************************************************/
/* rx66_A :: scw3 :: scw3 [15:00] */
#define RX66_A_SCW3_SCW3_MASK                                      0xffff
#define RX66_A_SCW3_SCW3_ALIGN                                     0
#define RX66_A_SCW3_SCW3_BITS                                      16
#define RX66_A_SCW3_SCW3_SHIFT                                     0


/****************************************************************************
 * rx66_A :: scw0_mask
 ***************************************************************************/
/* rx66_A :: scw0_mask :: scw0_mask [15:00] */
#define RX66_A_SCW0_MASK_SCW0_MASK_MASK                            0xffff
#define RX66_A_SCW0_MASK_SCW0_MASK_ALIGN                           0
#define RX66_A_SCW0_MASK_SCW0_MASK_BITS                            16
#define RX66_A_SCW0_MASK_SCW0_MASK_SHIFT                           0


/****************************************************************************
 * rx66_A :: scw1_mask
 ***************************************************************************/
/* rx66_A :: scw1_mask :: scw1_mask [15:00] */
#define RX66_A_SCW1_MASK_SCW1_MASK_MASK                            0xffff
#define RX66_A_SCW1_MASK_SCW1_MASK_ALIGN                           0
#define RX66_A_SCW1_MASK_SCW1_MASK_BITS                            16
#define RX66_A_SCW1_MASK_SCW1_MASK_SHIFT                           0


/****************************************************************************
 * rx66_A :: scw2_mask
 ***************************************************************************/
/* rx66_A :: scw2_mask :: scw2_mask [15:00] */
#define RX66_A_SCW2_MASK_SCW2_MASK_MASK                            0xffff
#define RX66_A_SCW2_MASK_SCW2_MASK_ALIGN                           0
#define RX66_A_SCW2_MASK_SCW2_MASK_BITS                            16
#define RX66_A_SCW2_MASK_SCW2_MASK_SHIFT                           0


/****************************************************************************
 * rx66_A :: scw3_mask
 ***************************************************************************/
/* rx66_A :: scw3_mask :: scw3_mask [15:00] */
#define RX66_A_SCW3_MASK_SCW3_MASK_MASK                            0xffff
#define RX66_A_SCW3_MASK_SCW3_MASK_ALIGN                           0
#define RX66_A_SCW3_MASK_SCW3_MASK_BITS                            16
#define RX66_A_SCW3_MASK_SCW3_MASK_SHIFT                           0


/****************************************************************************
 * rx66_A :: syncbits
 ***************************************************************************/
/* rx66_A :: syncbits :: reserved0 [15:04] */
#define RX66_A_SYNCBITS_RESERVED0_MASK                             0xfff0
#define RX66_A_SYNCBITS_RESERVED0_ALIGN                            0
#define RX66_A_SYNCBITS_RESERVED0_BITS                             12
#define RX66_A_SYNCBITS_RESERVED0_SHIFT                            4

/* rx66_A :: syncbits :: syncbits [03:02] */
#define RX66_A_SYNCBITS_SYNCBITS_MASK                              0x000c
#define RX66_A_SYNCBITS_SYNCBITS_ALIGN                             0
#define RX66_A_SYNCBITS_SYNCBITS_BITS                              2
#define RX66_A_SYNCBITS_SYNCBITS_SHIFT                             2

/* rx66_A :: syncbits :: syncbits_mask [01:00] */
#define RX66_A_SYNCBITS_SYNCBITS_MASK_MASK                         0x0003
#define RX66_A_SYNCBITS_SYNCBITS_MASK_ALIGN                        0
#define RX66_A_SYNCBITS_SYNCBITS_MASK_BITS                         2
#define RX66_A_SYNCBITS_SYNCBITS_MASK_SHIFT                        0


/****************************************************************************
 * rx66_A :: scwControl
 ***************************************************************************/
/* rx66_A :: scwControl :: reserved0 [15:15] */
#define RX66_A_SCWCONTROL_RESERVED0_MASK                           0x8000
#define RX66_A_SCWCONTROL_RESERVED0_ALIGN                          0
#define RX66_A_SCWCONTROL_RESERVED0_BITS                           1
#define RX66_A_SCWCONTROL_RESERVED0_SHIFT                          15

/* rx66_A :: scwControl :: scwCount [14:10] */
#define RX66_A_SCWCONTROL_SCWCOUNT_MASK                            0x7c00
#define RX66_A_SCWCONTROL_SCWCOUNT_ALIGN                           0
#define RX66_A_SCWCONTROL_SCWCOUNT_BITS                            5
#define RX66_A_SCWCONTROL_SCWCOUNT_SHIFT                           10

/* rx66_A :: scwControl :: gcwCount [09:05] */
#define RX66_A_SCWCONTROL_GCWCOUNT_MASK                            0x03e0
#define RX66_A_SCWCONTROL_GCWCOUNT_ALIGN                           0
#define RX66_A_SCWCONTROL_GCWCOUNT_BITS                            5
#define RX66_A_SCWCONTROL_GCWCOUNT_SHIFT                           5

/* rx66_A :: scwControl :: hystCount [04:00] */
#define RX66_A_SCWCONTROL_HYSTCOUNT_MASK                           0x001f
#define RX66_A_SCWCONTROL_HYSTCOUNT_ALIGN                          0
#define RX66_A_SCWCONTROL_HYSTCOUNT_BITS                           5
#define RX66_A_SCWCONTROL_HYSTCOUNT_SHIFT                          0


/****************************************************************************
 * rx66_A :: scwCount
 ***************************************************************************/
/* rx66_A :: scwCount :: reserved0 [15:15] */
#define RX66_A_SCWCOUNT_RESERVED0_MASK                             0x8000
#define RX66_A_SCWCOUNT_RESERVED0_ALIGN                            0
#define RX66_A_SCWCOUNT_RESERVED0_BITS                             1
#define RX66_A_SCWCOUNT_RESERVED0_SHIFT                            15

/* rx66_A :: scwCount :: scwShift [14:08] */
#define RX66_A_SCWCOUNT_SCWSHIFT_MASK                              0x7f00
#define RX66_A_SCWCOUNT_SCWSHIFT_ALIGN                             0
#define RX66_A_SCWCOUNT_SCWSHIFT_BITS                              7
#define RX66_A_SCWCOUNT_SCWSHIFT_SHIFT                             8

/* union - case COMMA_DETECT [07:00] */
/* rx66_A :: scwCount :: cwCount [07:00] */
#define RX66_A_SCWCOUNT_COMMA_DETECT_CWCOUNT_MASK                  0x00ff
#define RX66_A_SCWCOUNT_COMMA_DETECT_CWCOUNT_ALIGN                 0
#define RX66_A_SCWCOUNT_COMMA_DETECT_CWCOUNT_BITS                  8
#define RX66_A_SCWCOUNT_COMMA_DETECT_CWCOUNT_SHIFT                 0


/* union - case SYNC_ACQD2 [07:00] */
/* rx66_A :: scwCount :: cwCount [07:00] */
#define RX66_A_SCWCOUNT_SYNC_ACQD2_CWCOUNT_MASK                    0x00ff
#define RX66_A_SCWCOUNT_SYNC_ACQD2_CWCOUNT_ALIGN                   0
#define RX66_A_SCWCOUNT_SYNC_ACQD2_CWCOUNT_BITS                    8
#define RX66_A_SCWCOUNT_SYNC_ACQD2_CWCOUNT_SHIFT                   0



/****************************************************************************
 * rx66_A :: errCount
 ***************************************************************************/
/* rx66_A :: errCount :: sync66ErrCount [15:08] */
#define RX66_A_ERRCOUNT_SYNC66ERRCOUNT_MASK                        0xff00
#define RX66_A_ERRCOUNT_SYNC66ERRCOUNT_ALIGN                       0
#define RX66_A_ERRCOUNT_SYNC66ERRCOUNT_BITS                        8
#define RX66_A_ERRCOUNT_SYNC66ERRCOUNT_SHIFT                       8

/* rx66_A :: errCount :: kcode66ErrCount [07:00] */
#define RX66_A_ERRCOUNT_KCODE66ERRCOUNT_MASK                       0x00ff
#define RX66_A_ERRCOUNT_KCODE66ERRCOUNT_ALIGN                      0
#define RX66_A_ERRCOUNT_KCODE66ERRCOUNT_BITS                       8
#define RX66_A_ERRCOUNT_KCODE66ERRCOUNT_SHIFT                      0


/****************************************************************************
 * Hypercore_USER_Dsc1b0
 ***************************************************************************/
/****************************************************************************
 * Dsc1b0 :: cdr_ctrl0
 ***************************************************************************/
/* Dsc1b0 :: cdr_ctrl0 :: reserved_for_eco0 [15:13] */
#define DSC1B0_CDR_CTRL0_RESERVED_FOR_ECO0_MASK                    0xe000
#define DSC1B0_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC1B0_CDR_CTRL0_RESERVED_FOR_ECO0_BITS                    3
#define DSC1B0_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT                   13

/* Dsc1b0 :: cdr_ctrl0 :: cdrbr_polarity [12:12] */
#define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_MASK                       0x1000
#define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_ALIGN                      0
#define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_BITS                       1
#define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_SHIFT                      12

/* Dsc1b0 :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */
#define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK                   0x0800
#define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN                  0
#define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS                   1
#define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT                  11

/* Dsc1b0 :: cdr_ctrl0 :: cdros_rising_edge [10:10] */
#define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_MASK                    0x0400
#define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN                   0
#define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_BITS                    1
#define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT                   10

/* Dsc1b0 :: cdr_ctrl0 :: cdros_falling_edge [09:09] */
#define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_MASK                   0x0200
#define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN                  0
#define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_BITS                   1
#define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT                  9

/* Dsc1b0 :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */
#define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK                 0x0180
#define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN                0
#define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS                 2
#define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT                7

/* Dsc1b0 :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */
#define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK                  0x0040
#define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN                 0
#define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS                  1
#define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT                 6

/* Dsc1b0 :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */
#define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK                  0x0020
#define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN                 0
#define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS                  1
#define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT                 5

/* Dsc1b0 :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */
#define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK                    0x0010
#define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN                   0
#define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS                    1
#define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT                   4

/* Dsc1b0 :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */
#define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK                    0x0008
#define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN                   0
#define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS                    1
#define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT                   3

/* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */
#define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK                      0x0004
#define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN                     0
#define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS                      1
#define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT                     2

/* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_en [01:01] */
#define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_MASK                          0x0002
#define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_ALIGN                         0
#define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_BITS                          1
#define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_SHIFT                         1

/* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */
#define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK                 0x0001
#define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN                0
#define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS                 1
#define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT                0


/****************************************************************************
 * Dsc1b0 :: cdr_ctrl1
 ***************************************************************************/
/* Dsc1b0 :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */
#define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK                0xffff
#define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN               0
#define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS                16
#define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT               0


/****************************************************************************
 * Dsc1b0 :: cdr_ctrl2
 ***************************************************************************/
/* Dsc1b0 :: cdr_ctrl2 :: reserved_for_eco0 [15:06] */
#define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_MASK                    0xffc0
#define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_BITS                    10
#define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT                   6

/* Dsc1b0 :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */
#define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK               0x003f
#define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN              0
#define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS               6
#define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT              0


/****************************************************************************
 * Dsc1b0 :: pi_ctrl0
 ***************************************************************************/
/* Dsc1b0 :: pi_ctrl0 :: pi_cw_rst [15:15] */
#define DSC1B0_PI_CTRL0_PI_CW_RST_MASK                             0x8000
#define DSC1B0_PI_CTRL0_PI_CW_RST_ALIGN                            0
#define DSC1B0_PI_CTRL0_PI_CW_RST_BITS                             1
#define DSC1B0_PI_CTRL0_PI_CW_RST_SHIFT                            15

/* Dsc1b0 :: pi_ctrl0 :: intrp_tmuxSelect [14:12] */
#define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_MASK                      0x7000
#define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_ALIGN                     0
#define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_BITS                      3
#define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_SHIFT                     12
#define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_lsb             0
#define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_msb             1
#define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_lsb           2
#define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_msb           3
#define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_lsb            4
#define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_msb            5
#define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_lsb          6
#define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_msb          7

/* Dsc1b0 :: pi_ctrl0 :: reserved_for_eco0 [11:11] */
#define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_MASK                     0x0800
#define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_BITS                     1
#define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT                    11

/* Dsc1b0 :: pi_ctrl0 :: pi_phase_invert [10:10] */
#define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_MASK                       0x0400
#define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_ALIGN                      0
#define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_BITS                       1
#define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_SHIFT                      10

/* Dsc1b0 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */
#define DSC1B0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK                0x0200
#define DSC1B0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN               0
#define DSC1B0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS                1
#define DSC1B0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT               9

/* Dsc1b0 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */
#define DSC1B0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK              0x0100
#define DSC1B0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN             0
#define DSC1B0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS              1
#define DSC1B0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT             8

/* Dsc1b0 :: pi_ctrl0 :: pi_phase_dec [07:07] */
#define DSC1B0_PI_CTRL0_PI_PHASE_DEC_MASK                          0x0080
#define DSC1B0_PI_CTRL0_PI_PHASE_DEC_ALIGN                         0
#define DSC1B0_PI_CTRL0_PI_PHASE_DEC_BITS                          1
#define DSC1B0_PI_CTRL0_PI_PHASE_DEC_SHIFT                         7

/* Dsc1b0 :: pi_ctrl0 :: pi_phase_inc [06:06] */
#define DSC1B0_PI_CTRL0_PI_PHASE_INC_MASK                          0x0040
#define DSC1B0_PI_CTRL0_PI_PHASE_INC_ALIGN                         0
#define DSC1B0_PI_CTRL0_PI_PHASE_INC_BITS                          1
#define DSC1B0_PI_CTRL0_PI_PHASE_INC_SHIFT                         6

/* Dsc1b0 :: pi_ctrl0 :: pi_phase_strobe [05:05] */
#define DSC1B0_PI_CTRL0_PI_PHASE_STROBE_MASK                       0x0020
#define DSC1B0_PI_CTRL0_PI_PHASE_STROBE_ALIGN                      0
#define DSC1B0_PI_CTRL0_PI_PHASE_STROBE_BITS                       1
#define DSC1B0_PI_CTRL0_PI_PHASE_STROBE_SHIFT                      5

/* Dsc1b0 :: pi_ctrl0 :: pi_phase_delta [04:01] */
#define DSC1B0_PI_CTRL0_PI_PHASE_DELTA_MASK                        0x001e
#define DSC1B0_PI_CTRL0_PI_PHASE_DELTA_ALIGN                       0
#define DSC1B0_PI_CTRL0_PI_PHASE_DELTA_BITS                        4
#define DSC1B0_PI_CTRL0_PI_PHASE_DELTA_SHIFT                       1

/* Dsc1b0 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */
#define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_MASK                    0x0001
#define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN                   0
#define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_BITS                    1
#define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT                   0


/****************************************************************************
 * Dsc1b0 :: dfe_vga_ctrl0
 ***************************************************************************/
/* Dsc1b0 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:08] */
#define DSC1B0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK                0xff00
#define DSC1B0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS                8
#define DSC1B0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT               8

/* Dsc1b0 :: dfe_vga_ctrl0 :: vga_timer_ctrl [07:06] */
#define DSC1B0_DFE_VGA_CTRL0_VGA_TIMER_CTRL_MASK                   0x00c0
#define DSC1B0_DFE_VGA_CTRL0_VGA_TIMER_CTRL_ALIGN                  0
#define DSC1B0_DFE_VGA_CTRL0_VGA_TIMER_CTRL_BITS                   2
#define DSC1B0_DFE_VGA_CTRL0_VGA_TIMER_CTRL_SHIFT                  6

/* Dsc1b0 :: dfe_vga_ctrl0 :: vga_polarity [05:05] */
#define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_MASK                     0x0020
#define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN                    0
#define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_BITS                     1
#define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT                    5

/* Dsc1b0 :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */
#define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_MASK                     0x0010
#define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN                    0
#define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_BITS                     1
#define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT                    4

/* Dsc1b0 :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */
#define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK                 0x0008
#define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN                0
#define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS                 1
#define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT                3

/* Dsc1b0 :: dfe_vga_ctrl0 :: sum_m1err [02:02] */
#define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_MASK                        0x0004
#define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN                       0
#define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_BITS                        1
#define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT                       2

/* Dsc1b0 :: dfe_vga_ctrl0 :: trnsum_en [01:01] */
#define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_MASK                        0x0002
#define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN                       0
#define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_BITS                        1
#define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT                       1

/* Dsc1b0 :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */
#define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK                    0x0001
#define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN                   0
#define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS                    1
#define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT                   0


/****************************************************************************
 * Dsc1b0 :: dfe_vga_ctrl1
 ***************************************************************************/
/* Dsc1b0 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:13] */
#define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK                0xe000
#define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS                3
#define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT               13

/* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_write_val [12:07] */
#define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_VAL_MASK                    0x1f80
#define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_VAL_ALIGN                   0
#define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_VAL_BITS                    6
#define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_VAL_SHIFT                   7

/* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_write_en [06:06] */
#define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_EN_MASK                     0x0040
#define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_EN_ALIGN                    0
#define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_EN_BITS                     1
#define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_EN_SHIFT                    6

/* Dsc1b0 :: dfe_vga_ctrl1 :: vga_write_val [05:01] */
#define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_VAL_MASK                    0x003e
#define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_VAL_ALIGN                   0
#define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_VAL_BITS                    5
#define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_VAL_SHIFT                   1

/* Dsc1b0 :: dfe_vga_ctrl1 :: vga_write_en [00:00] */
#define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_EN_MASK                     0x0001
#define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_EN_ALIGN                    0
#define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_EN_BITS                     1
#define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_EN_SHIFT                    0


/****************************************************************************
 * Dsc1b0 :: dfe_vga_ctrl2
 ***************************************************************************/
/* Dsc1b0 :: dfe_vga_ctrl2 :: reserved_for_eco0 [15:14] */
#define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_MASK                0xc000
#define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_BITS                2
#define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_SHIFT               14

/* Dsc1b0 :: dfe_vga_ctrl2 :: trnsum_otap_en [13:07] */
#define DSC1B0_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_MASK                   0x3f80
#define DSC1B0_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_ALIGN                  0
#define DSC1B0_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_BITS                   7
#define DSC1B0_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_SHIFT                  7

/* Dsc1b0 :: dfe_vga_ctrl2 :: trnsum_etap_en [06:00] */
#define DSC1B0_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_MASK                   0x007f
#define DSC1B0_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_ALIGN                  0
#define DSC1B0_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_BITS                   7
#define DSC1B0_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_SHIFT                  0


/****************************************************************************
 * Dsc1b0 :: dfe_vga_ctrl3
 ***************************************************************************/
/* Dsc1b0 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:14] */
#define DSC1B0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK                0xc000
#define DSC1B0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS                2
#define DSC1B0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT               14

/* Dsc1b0 :: dfe_vga_ctrl3 :: trnsum_otap_sign [13:07] */
#define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_MASK                 0x3f80
#define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_ALIGN                0
#define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_BITS                 7
#define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_SHIFT                7

/* Dsc1b0 :: dfe_vga_ctrl3 :: trnsum_etap_sign [06:00] */
#define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_MASK                 0x007f
#define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_ALIGN                0
#define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_BITS                 7
#define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_SHIFT                0


/****************************************************************************
 * Dsc1b0 :: dfe_vga_ctrl4
 ***************************************************************************/
/* Dsc1b0 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */
#define DSC1B0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK                0xfc00
#define DSC1B0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS                6
#define DSC1B0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT               10

/* Dsc1b0 :: dfe_vga_ctrl4 :: vga_cor_sel_e [09:05] */
#define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_E_MASK                    0x03e0
#define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_E_ALIGN                   0
#define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_E_BITS                    5
#define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_E_SHIFT                   5

/* Dsc1b0 :: dfe_vga_ctrl4 :: vga_cor_sel_o [04:00] */
#define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_O_MASK                    0x001f
#define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_O_ALIGN                   0
#define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_O_BITS                    5
#define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_O_SHIFT                   0


/****************************************************************************
 * Dsc1b0 :: dfe_vga_ctrl5
 ***************************************************************************/
/* Dsc1b0 :: dfe_vga_ctrl5 :: reserved_for_eco0 [15:10] */
#define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_MASK                0xfc00
#define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_BITS                6
#define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_SHIFT               10

/* Dsc1b0 :: dfe_vga_ctrl5 :: dfe_cor_sel_e [09:05] */
#define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_E_MASK                    0x03e0
#define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_E_ALIGN                   0
#define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_E_BITS                    5
#define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_E_SHIFT                   5

/* Dsc1b0 :: dfe_vga_ctrl5 :: dfe_cor_sel_o [04:00] */
#define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_O_MASK                    0x001f
#define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_O_ALIGN                   0
#define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_O_BITS                    5
#define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_O_SHIFT                   0


/****************************************************************************
 * Dsc1b0 :: dsc_ana_ctrl0
 ***************************************************************************/
/* Dsc1b0 :: dsc_ana_ctrl0 :: force_odd_ctrl [15:15] */
#define DSC1B0_DSC_ANA_CTRL0_FORCE_ODD_CTRL_MASK                   0x8000
#define DSC1B0_DSC_ANA_CTRL0_FORCE_ODD_CTRL_ALIGN                  0
#define DSC1B0_DSC_ANA_CTRL0_FORCE_ODD_CTRL_BITS                   1
#define DSC1B0_DSC_ANA_CTRL0_FORCE_ODD_CTRL_SHIFT                  15

/* Dsc1b0 :: dsc_ana_ctrl0 :: p1_odd_ctrl [14:10] */
#define DSC1B0_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK                      0x7c00
#define DSC1B0_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN                     0
#define DSC1B0_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS                      5
#define DSC1B0_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT                     10

/* Dsc1b0 :: dsc_ana_ctrl0 :: d_odd_ctrl [09:05] */
#define DSC1B0_DSC_ANA_CTRL0_D_ODD_CTRL_MASK                       0x03e0
#define DSC1B0_DSC_ANA_CTRL0_D_ODD_CTRL_ALIGN                      0
#define DSC1B0_DSC_ANA_CTRL0_D_ODD_CTRL_BITS                       5
#define DSC1B0_DSC_ANA_CTRL0_D_ODD_CTRL_SHIFT                      5

/* Dsc1b0 :: dsc_ana_ctrl0 :: m1_odd_ctrl [04:00] */
#define DSC1B0_DSC_ANA_CTRL0_M1_ODD_CTRL_MASK                      0x001f
#define DSC1B0_DSC_ANA_CTRL0_M1_ODD_CTRL_ALIGN                     0
#define DSC1B0_DSC_ANA_CTRL0_M1_ODD_CTRL_BITS                      5
#define DSC1B0_DSC_ANA_CTRL0_M1_ODD_CTRL_SHIFT                     0


/****************************************************************************
 * Dsc1b0 :: dsc_ana_ctrl1
 ***************************************************************************/
/* Dsc1b0 :: dsc_ana_ctrl1 :: force_evn_ctrl [15:15] */
#define DSC1B0_DSC_ANA_CTRL1_FORCE_EVN_CTRL_MASK                   0x8000
#define DSC1B0_DSC_ANA_CTRL1_FORCE_EVN_CTRL_ALIGN                  0
#define DSC1B0_DSC_ANA_CTRL1_FORCE_EVN_CTRL_BITS                   1
#define DSC1B0_DSC_ANA_CTRL1_FORCE_EVN_CTRL_SHIFT                  15

/* Dsc1b0 :: dsc_ana_ctrl1 :: p1_evn_ctrl [14:10] */
#define DSC1B0_DSC_ANA_CTRL1_P1_EVN_CTRL_MASK                      0x7c00
#define DSC1B0_DSC_ANA_CTRL1_P1_EVN_CTRL_ALIGN                     0
#define DSC1B0_DSC_ANA_CTRL1_P1_EVN_CTRL_BITS                      5
#define DSC1B0_DSC_ANA_CTRL1_P1_EVN_CTRL_SHIFT                     10

/* Dsc1b0 :: dsc_ana_ctrl1 :: d_evn_ctrl [09:05] */
#define DSC1B0_DSC_ANA_CTRL1_D_EVN_CTRL_MASK                       0x03e0
#define DSC1B0_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN                      0
#define DSC1B0_DSC_ANA_CTRL1_D_EVN_CTRL_BITS                       5
#define DSC1B0_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT                      5

/* Dsc1b0 :: dsc_ana_ctrl1 :: m1_evn_ctrl [04:00] */
#define DSC1B0_DSC_ANA_CTRL1_M1_EVN_CTRL_MASK                      0x001f
#define DSC1B0_DSC_ANA_CTRL1_M1_EVN_CTRL_ALIGN                     0
#define DSC1B0_DSC_ANA_CTRL1_M1_EVN_CTRL_BITS                      5
#define DSC1B0_DSC_ANA_CTRL1_M1_EVN_CTRL_SHIFT                     0


/****************************************************************************
 * Dsc1b0 :: dsc_ana_ctrl2
 ***************************************************************************/
/* Dsc1b0 :: dsc_ana_ctrl2 :: br_offset_pd [15:15] */
#define DSC1B0_DSC_ANA_CTRL2_BR_OFFSET_PD_MASK                     0x8000
#define DSC1B0_DSC_ANA_CTRL2_BR_OFFSET_PD_ALIGN                    0
#define DSC1B0_DSC_ANA_CTRL2_BR_OFFSET_PD_BITS                     1
#define DSC1B0_DSC_ANA_CTRL2_BR_OFFSET_PD_SHIFT                    15

/* Dsc1b0 :: dsc_ana_ctrl2 :: br_en_hgain [14:14] */
#define DSC1B0_DSC_ANA_CTRL2_BR_EN_HGAIN_MASK                      0x4000
#define DSC1B0_DSC_ANA_CTRL2_BR_EN_HGAIN_ALIGN                     0
#define DSC1B0_DSC_ANA_CTRL2_BR_EN_HGAIN_BITS                      1
#define DSC1B0_DSC_ANA_CTRL2_BR_EN_HGAIN_SHIFT                     14

/* Dsc1b0 :: dsc_ana_ctrl2 :: br_en_dfe_clk [13:13] */
#define DSC1B0_DSC_ANA_CTRL2_BR_EN_DFE_CLK_MASK                    0x2000
#define DSC1B0_DSC_ANA_CTRL2_BR_EN_DFE_CLK_ALIGN                   0
#define DSC1B0_DSC_ANA_CTRL2_BR_EN_DFE_CLK_BITS                    1
#define DSC1B0_DSC_ANA_CTRL2_BR_EN_DFE_CLK_SHIFT                   13

/* Dsc1b0 :: dsc_ana_ctrl2 :: br_pd_ch_p1 [12:12] */
#define DSC1B0_DSC_ANA_CTRL2_BR_PD_CH_P1_MASK                      0x1000
#define DSC1B0_DSC_ANA_CTRL2_BR_PD_CH_P1_ALIGN                     0
#define DSC1B0_DSC_ANA_CTRL2_BR_PD_CH_P1_BITS                      1
#define DSC1B0_DSC_ANA_CTRL2_BR_PD_CH_P1_SHIFT                     12

/* Dsc1b0 :: dsc_ana_ctrl2 :: osr_offset_pd [11:11] */
#define DSC1B0_DSC_ANA_CTRL2_OSR_OFFSET_PD_MASK                    0x0800
#define DSC1B0_DSC_ANA_CTRL2_OSR_OFFSET_PD_ALIGN                   0
#define DSC1B0_DSC_ANA_CTRL2_OSR_OFFSET_PD_BITS                    1
#define DSC1B0_DSC_ANA_CTRL2_OSR_OFFSET_PD_SHIFT                   11

/* Dsc1b0 :: dsc_ana_ctrl2 :: osr_en_hgain [10:10] */
#define DSC1B0_DSC_ANA_CTRL2_OSR_EN_HGAIN_MASK                     0x0400
#define DSC1B0_DSC_ANA_CTRL2_OSR_EN_HGAIN_ALIGN                    0
#define DSC1B0_DSC_ANA_CTRL2_OSR_EN_HGAIN_BITS                     1
#define DSC1B0_DSC_ANA_CTRL2_OSR_EN_HGAIN_SHIFT                    10

/* Dsc1b0 :: dsc_ana_ctrl2 :: osr_en_dfe_clk [09:09] */
#define DSC1B0_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_MASK                   0x0200
#define DSC1B0_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_ALIGN                  0
#define DSC1B0_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_BITS                   1
#define DSC1B0_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_SHIFT                  9

/* Dsc1b0 :: dsc_ana_ctrl2 :: osr_pd_ch_p1 [08:08] */
#define DSC1B0_DSC_ANA_CTRL2_OSR_PD_CH_P1_MASK                     0x0100
#define DSC1B0_DSC_ANA_CTRL2_OSR_PD_CH_P1_ALIGN                    0
#define DSC1B0_DSC_ANA_CTRL2_OSR_PD_CH_P1_BITS                     1
#define DSC1B0_DSC_ANA_CTRL2_OSR_PD_CH_P1_SHIFT                    8

/* Dsc1b0 :: dsc_ana_ctrl2 :: force_rx_m1_thresh_zero [07:07] */
#define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_MASK          0x0080
#define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_ALIGN         0
#define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_BITS          1
#define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_SHIFT         7

/* Dsc1b0 :: dsc_ana_ctrl2 :: rx_m1_thresh_zero [06:06] */
#define DSC1B0_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_MASK                0x0040
#define DSC1B0_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_ALIGN               0
#define DSC1B0_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_BITS                1
#define DSC1B0_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_SHIFT               6

/* Dsc1b0 :: dsc_ana_ctrl2 :: rx_thresh_sel [05:04] */
#define DSC1B0_DSC_ANA_CTRL2_RX_THRESH_SEL_MASK                    0x0030
#define DSC1B0_DSC_ANA_CTRL2_RX_THRESH_SEL_ALIGN                   0
#define DSC1B0_DSC_ANA_CTRL2_RX_THRESH_SEL_BITS                    2
#define DSC1B0_DSC_ANA_CTRL2_RX_THRESH_SEL_SHIFT                   4

/* Dsc1b0 :: dsc_ana_ctrl2 :: force_rx_pf_ctrl [03:03] */
#define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_MASK                 0x0008
#define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_ALIGN                0
#define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_BITS                 1
#define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_SHIFT                3

/* Dsc1b0 :: dsc_ana_ctrl2 :: rx_pf_ctrl [02:00] */
#define DSC1B0_DSC_ANA_CTRL2_RX_PF_CTRL_MASK                       0x0007
#define DSC1B0_DSC_ANA_CTRL2_RX_PF_CTRL_ALIGN                      0
#define DSC1B0_DSC_ANA_CTRL2_RX_PF_CTRL_BITS                       3
#define DSC1B0_DSC_ANA_CTRL2_RX_PF_CTRL_SHIFT                      0


/****************************************************************************
 * Dsc1b0 :: dsc_100fx_ctrl
 ***************************************************************************/
/* Dsc1b0 :: dsc_100fx_ctrl :: reserved_for_eco0 [15:11] */
#define DSC1B0_DSC_100FX_CTRL_RESERVED_FOR_ECO0_MASK               0xf800
#define DSC1B0_DSC_100FX_CTRL_RESERVED_FOR_ECO0_ALIGN              0
#define DSC1B0_DSC_100FX_CTRL_RESERVED_FOR_ECO0_BITS               5
#define DSC1B0_DSC_100FX_CTRL_RESERVED_FOR_ECO0_SHIFT              11

/* Dsc1b0 :: dsc_100fx_ctrl :: phase_sat_ctrl_100fx [10:09] */
#define DSC1B0_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_MASK            0x0600
#define DSC1B0_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_ALIGN           0
#define DSC1B0_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_BITS            2
#define DSC1B0_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_SHIFT           9

/* Dsc1b0 :: dsc_100fx_ctrl :: pi_phase_step_mult_100fx [08:08] */
#define DSC1B0_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_MASK        0x0100
#define DSC1B0_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_ALIGN       0
#define DSC1B0_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_BITS        1
#define DSC1B0_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_SHIFT       8

/* Dsc1b0 :: dsc_100fx_ctrl :: cdros_bwsel_integ_100fx [07:04] */
#define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_MASK         0x00f0
#define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_ALIGN        0
#define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_BITS         4
#define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_SHIFT        4

/* Dsc1b0 :: dsc_100fx_ctrl :: cdros_bwsel_prop_100fx [03:00] */
#define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_MASK          0x000f
#define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_ALIGN         0
#define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_BITS          4
#define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_SHIFT         0


/****************************************************************************
 * Dsc1b0 :: dsc_ana_ctrl3
 ***************************************************************************/
/* Dsc1b0 :: dsc_ana_ctrl3 :: reserved_for_eco0 [15:06] */
#define DSC1B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_MASK                0xffc0
#define DSC1B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_BITS                10
#define DSC1B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_SHIFT               6

/* Dsc1b0 :: dsc_ana_ctrl3 :: force_p1_evn_ctrl [05:05] */
#define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_MASK                0x0020
#define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_ALIGN               0
#define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_BITS                1
#define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_SHIFT               5

/* Dsc1b0 :: dsc_ana_ctrl3 :: force_d_evn_ctrl [04:04] */
#define DSC1B0_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_MASK                 0x0010
#define DSC1B0_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_ALIGN                0
#define DSC1B0_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_BITS                 1
#define DSC1B0_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_SHIFT                4

/* Dsc1b0 :: dsc_ana_ctrl3 :: force_m1_evn_ctrl [03:03] */
#define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_MASK                0x0008
#define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_ALIGN               0
#define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_BITS                1
#define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_SHIFT               3

/* Dsc1b0 :: dsc_ana_ctrl3 :: force_p1_odd_ctrl [02:02] */
#define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_MASK                0x0004
#define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_ALIGN               0
#define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_BITS                1
#define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_SHIFT               2

/* Dsc1b0 :: dsc_ana_ctrl3 :: force_d_odd_ctrl [01:01] */
#define DSC1B0_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_MASK                 0x0002
#define DSC1B0_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_ALIGN                0
#define DSC1B0_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_BITS                 1
#define DSC1B0_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_SHIFT                1

/* Dsc1b0 :: dsc_ana_ctrl3 :: force_m1_odd_ctrl [00:00] */
#define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_MASK                0x0001
#define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_ALIGN               0
#define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_BITS                1
#define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_SHIFT               0


/****************************************************************************
 * Hypercore_USER_Dsc1b1
 ***************************************************************************/
/****************************************************************************
 * Dsc1b1 :: cdr_ctrl0
 ***************************************************************************/
/* Dsc1b1 :: cdr_ctrl0 :: reserved_for_eco0 [15:13] */
#define DSC1B1_CDR_CTRL0_RESERVED_FOR_ECO0_MASK                    0xe000
#define DSC1B1_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC1B1_CDR_CTRL0_RESERVED_FOR_ECO0_BITS                    3
#define DSC1B1_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT                   13

/* Dsc1b1 :: cdr_ctrl0 :: cdrbr_polarity [12:12] */
#define DSC1B1_CDR_CTRL0_CDRBR_POLARITY_MASK                       0x1000
#define DSC1B1_CDR_CTRL0_CDRBR_POLARITY_ALIGN                      0
#define DSC1B1_CDR_CTRL0_CDRBR_POLARITY_BITS                       1
#define DSC1B1_CDR_CTRL0_CDRBR_POLARITY_SHIFT                      12

/* Dsc1b1 :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */
#define DSC1B1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK                   0x0800
#define DSC1B1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN                  0
#define DSC1B1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS                   1
#define DSC1B1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT                  11

/* Dsc1b1 :: cdr_ctrl0 :: cdros_rising_edge [10:10] */
#define DSC1B1_CDR_CTRL0_CDROS_RISING_EDGE_MASK                    0x0400
#define DSC1B1_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN                   0
#define DSC1B1_CDR_CTRL0_CDROS_RISING_EDGE_BITS                    1
#define DSC1B1_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT                   10

/* Dsc1b1 :: cdr_ctrl0 :: cdros_falling_edge [09:09] */
#define DSC1B1_CDR_CTRL0_CDROS_FALLING_EDGE_MASK                   0x0200
#define DSC1B1_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN                  0
#define DSC1B1_CDR_CTRL0_CDROS_FALLING_EDGE_BITS                   1
#define DSC1B1_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT                  9

/* Dsc1b1 :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */
#define DSC1B1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK                 0x0180
#define DSC1B1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN                0
#define DSC1B1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS                 2
#define DSC1B1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT                7

/* Dsc1b1 :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */
#define DSC1B1_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK                  0x0040
#define DSC1B1_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN                 0
#define DSC1B1_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS                  1
#define DSC1B1_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT                 6

/* Dsc1b1 :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */
#define DSC1B1_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK                  0x0020
#define DSC1B1_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN                 0
#define DSC1B1_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS                  1
#define DSC1B1_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT                 5

/* Dsc1b1 :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */
#define DSC1B1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK                    0x0010
#define DSC1B1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN                   0
#define DSC1B1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS                    1
#define DSC1B1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT                   4

/* Dsc1b1 :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */
#define DSC1B1_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK                    0x0008
#define DSC1B1_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN                   0
#define DSC1B1_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS                    1
#define DSC1B1_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT                   3

/* Dsc1b1 :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */
#define DSC1B1_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK                      0x0004
#define DSC1B1_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN                     0
#define DSC1B1_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS                      1
#define DSC1B1_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT                     2

/* Dsc1b1 :: cdr_ctrl0 :: cdr_freq_en [01:01] */
#define DSC1B1_CDR_CTRL0_CDR_FREQ_EN_MASK                          0x0002
#define DSC1B1_CDR_CTRL0_CDR_FREQ_EN_ALIGN                         0
#define DSC1B1_CDR_CTRL0_CDR_FREQ_EN_BITS                          1
#define DSC1B1_CDR_CTRL0_CDR_FREQ_EN_SHIFT                         1

/* Dsc1b1 :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */
#define DSC1B1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK                 0x0001
#define DSC1B1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN                0
#define DSC1B1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS                 1
#define DSC1B1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT                0


/****************************************************************************
 * Dsc1b1 :: cdr_ctrl1
 ***************************************************************************/
/* Dsc1b1 :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */
#define DSC1B1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK                0xffff
#define DSC1B1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN               0
#define DSC1B1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS                16
#define DSC1B1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT               0


/****************************************************************************
 * Dsc1b1 :: cdr_ctrl2
 ***************************************************************************/
/* Dsc1b1 :: cdr_ctrl2 :: reserved_for_eco0 [15:06] */
#define DSC1B1_CDR_CTRL2_RESERVED_FOR_ECO0_MASK                    0xffc0
#define DSC1B1_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC1B1_CDR_CTRL2_RESERVED_FOR_ECO0_BITS                    10
#define DSC1B1_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT                   6

/* Dsc1b1 :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */
#define DSC1B1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK               0x003f
#define DSC1B1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN              0
#define DSC1B1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS               6
#define DSC1B1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT              0


/****************************************************************************
 * Dsc1b1 :: pi_ctrl0
 ***************************************************************************/
/* Dsc1b1 :: pi_ctrl0 :: pi_cw_rst [15:15] */
#define DSC1B1_PI_CTRL0_PI_CW_RST_MASK                             0x8000
#define DSC1B1_PI_CTRL0_PI_CW_RST_ALIGN                            0
#define DSC1B1_PI_CTRL0_PI_CW_RST_BITS                             1
#define DSC1B1_PI_CTRL0_PI_CW_RST_SHIFT                            15

/* Dsc1b1 :: pi_ctrl0 :: intrp_tmuxSelect [14:12] */
#define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_MASK                      0x7000
#define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_ALIGN                     0
#define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_BITS                      3
#define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_SHIFT                     12
#define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_lsb             0
#define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_msb             1
#define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_lsb           2
#define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_msb           3
#define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_lsb            4
#define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_msb            5
#define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_lsb          6
#define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_msb          7

/* Dsc1b1 :: pi_ctrl0 :: reserved_for_eco0 [11:11] */
#define DSC1B1_PI_CTRL0_RESERVED_FOR_ECO0_MASK                     0x0800
#define DSC1B1_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC1B1_PI_CTRL0_RESERVED_FOR_ECO0_BITS                     1
#define DSC1B1_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT                    11

/* Dsc1b1 :: pi_ctrl0 :: pi_phase_invert [10:10] */
#define DSC1B1_PI_CTRL0_PI_PHASE_INVERT_MASK                       0x0400
#define DSC1B1_PI_CTRL0_PI_PHASE_INVERT_ALIGN                      0
#define DSC1B1_PI_CTRL0_PI_PHASE_INVERT_BITS                       1
#define DSC1B1_PI_CTRL0_PI_PHASE_INVERT_SHIFT                      10

/* Dsc1b1 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */
#define DSC1B1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK                0x0200
#define DSC1B1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN               0
#define DSC1B1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS                1
#define DSC1B1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT               9

/* Dsc1b1 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */
#define DSC1B1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK              0x0100
#define DSC1B1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN             0
#define DSC1B1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS              1
#define DSC1B1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT             8

/* Dsc1b1 :: pi_ctrl0 :: pi_phase_dec [07:07] */
#define DSC1B1_PI_CTRL0_PI_PHASE_DEC_MASK                          0x0080
#define DSC1B1_PI_CTRL0_PI_PHASE_DEC_ALIGN                         0
#define DSC1B1_PI_CTRL0_PI_PHASE_DEC_BITS                          1
#define DSC1B1_PI_CTRL0_PI_PHASE_DEC_SHIFT                         7

/* Dsc1b1 :: pi_ctrl0 :: pi_phase_inc [06:06] */
#define DSC1B1_PI_CTRL0_PI_PHASE_INC_MASK                          0x0040
#define DSC1B1_PI_CTRL0_PI_PHASE_INC_ALIGN                         0
#define DSC1B1_PI_CTRL0_PI_PHASE_INC_BITS                          1
#define DSC1B1_PI_CTRL0_PI_PHASE_INC_SHIFT                         6

/* Dsc1b1 :: pi_ctrl0 :: pi_phase_strobe [05:05] */
#define DSC1B1_PI_CTRL0_PI_PHASE_STROBE_MASK                       0x0020
#define DSC1B1_PI_CTRL0_PI_PHASE_STROBE_ALIGN                      0
#define DSC1B1_PI_CTRL0_PI_PHASE_STROBE_BITS                       1
#define DSC1B1_PI_CTRL0_PI_PHASE_STROBE_SHIFT                      5

/* Dsc1b1 :: pi_ctrl0 :: pi_phase_delta [04:01] */
#define DSC1B1_PI_CTRL0_PI_PHASE_DELTA_MASK                        0x001e
#define DSC1B1_PI_CTRL0_PI_PHASE_DELTA_ALIGN                       0
#define DSC1B1_PI_CTRL0_PI_PHASE_DELTA_BITS                        4
#define DSC1B1_PI_CTRL0_PI_PHASE_DELTA_SHIFT                       1

/* Dsc1b1 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */
#define DSC1B1_PI_CTRL0_PI_PHASE_STEP_MULT_MASK                    0x0001
#define DSC1B1_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN                   0
#define DSC1B1_PI_CTRL0_PI_PHASE_STEP_MULT_BITS                    1
#define DSC1B1_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT                   0


/****************************************************************************
 * Dsc1b1 :: dfe_vga_ctrl0
 ***************************************************************************/
/* Dsc1b1 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:08] */
#define DSC1B1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK                0xff00
#define DSC1B1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS                8
#define DSC1B1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT               8

/* Dsc1b1 :: dfe_vga_ctrl0 :: vga_timer_ctrl [07:06] */
#define DSC1B1_DFE_VGA_CTRL0_VGA_TIMER_CTRL_MASK                   0x00c0
#define DSC1B1_DFE_VGA_CTRL0_VGA_TIMER_CTRL_ALIGN                  0
#define DSC1B1_DFE_VGA_CTRL0_VGA_TIMER_CTRL_BITS                   2
#define DSC1B1_DFE_VGA_CTRL0_VGA_TIMER_CTRL_SHIFT                  6

/* Dsc1b1 :: dfe_vga_ctrl0 :: vga_polarity [05:05] */
#define DSC1B1_DFE_VGA_CTRL0_VGA_POLARITY_MASK                     0x0020
#define DSC1B1_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN                    0
#define DSC1B1_DFE_VGA_CTRL0_VGA_POLARITY_BITS                     1
#define DSC1B1_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT                    5

/* Dsc1b1 :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */
#define DSC1B1_DFE_VGA_CTRL0_DFE_POLARITY_MASK                     0x0010
#define DSC1B1_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN                    0
#define DSC1B1_DFE_VGA_CTRL0_DFE_POLARITY_BITS                     1
#define DSC1B1_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT                    4

/* Dsc1b1 :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */
#define DSC1B1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK                 0x0008
#define DSC1B1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN                0
#define DSC1B1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS                 1
#define DSC1B1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT                3

/* Dsc1b1 :: dfe_vga_ctrl0 :: sum_m1err [02:02] */
#define DSC1B1_DFE_VGA_CTRL0_SUM_M1ERR_MASK                        0x0004
#define DSC1B1_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN                       0
#define DSC1B1_DFE_VGA_CTRL0_SUM_M1ERR_BITS                        1
#define DSC1B1_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT                       2

/* Dsc1b1 :: dfe_vga_ctrl0 :: trnsum_en [01:01] */
#define DSC1B1_DFE_VGA_CTRL0_TRNSUM_EN_MASK                        0x0002
#define DSC1B1_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN                       0
#define DSC1B1_DFE_VGA_CTRL0_TRNSUM_EN_BITS                        1
#define DSC1B1_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT                       1

/* Dsc1b1 :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */
#define DSC1B1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK                    0x0001
#define DSC1B1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN                   0
#define DSC1B1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS                    1
#define DSC1B1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT                   0


/****************************************************************************
 * Dsc1b1 :: dfe_vga_ctrl1
 ***************************************************************************/
/* Dsc1b1 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:13] */
#define DSC1B1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK                0xe000
#define DSC1B1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS                3
#define DSC1B1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT               13

/* Dsc1b1 :: dfe_vga_ctrl1 :: dfe_write_val [12:07] */
#define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_VAL_MASK                    0x1f80
#define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_VAL_ALIGN                   0
#define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_VAL_BITS                    6
#define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_VAL_SHIFT                   7

/* Dsc1b1 :: dfe_vga_ctrl1 :: dfe_write_en [06:06] */
#define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_EN_MASK                     0x0040
#define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_EN_ALIGN                    0
#define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_EN_BITS                     1
#define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_EN_SHIFT                    6

/* Dsc1b1 :: dfe_vga_ctrl1 :: vga_write_val [05:01] */
#define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_VAL_MASK                    0x003e
#define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_VAL_ALIGN                   0
#define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_VAL_BITS                    5
#define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_VAL_SHIFT                   1

/* Dsc1b1 :: dfe_vga_ctrl1 :: vga_write_en [00:00] */
#define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_EN_MASK                     0x0001
#define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_EN_ALIGN                    0
#define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_EN_BITS                     1
#define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_EN_SHIFT                    0


/****************************************************************************
 * Dsc1b1 :: dfe_vga_ctrl2
 ***************************************************************************/
/* Dsc1b1 :: dfe_vga_ctrl2 :: reserved_for_eco0 [15:14] */
#define DSC1B1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_MASK                0xc000
#define DSC1B1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_BITS                2
#define DSC1B1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_SHIFT               14

/* Dsc1b1 :: dfe_vga_ctrl2 :: trnsum_otap_en [13:07] */
#define DSC1B1_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_MASK                   0x3f80
#define DSC1B1_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_ALIGN                  0
#define DSC1B1_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_BITS                   7
#define DSC1B1_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_SHIFT                  7

/* Dsc1b1 :: dfe_vga_ctrl2 :: trnsum_etap_en [06:00] */
#define DSC1B1_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_MASK                   0x007f
#define DSC1B1_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_ALIGN                  0
#define DSC1B1_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_BITS                   7
#define DSC1B1_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_SHIFT                  0


/****************************************************************************
 * Dsc1b1 :: dfe_vga_ctrl3
 ***************************************************************************/
/* Dsc1b1 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:14] */
#define DSC1B1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK                0xc000
#define DSC1B1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS                2
#define DSC1B1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT               14

/* Dsc1b1 :: dfe_vga_ctrl3 :: trnsum_otap_sign [13:07] */
#define DSC1B1_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_MASK                 0x3f80
#define DSC1B1_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_ALIGN                0
#define DSC1B1_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_BITS                 7
#define DSC1B1_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_SHIFT                7

/* Dsc1b1 :: dfe_vga_ctrl3 :: trnsum_etap_sign [06:00] */
#define DSC1B1_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_MASK                 0x007f
#define DSC1B1_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_ALIGN                0
#define DSC1B1_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_BITS                 7
#define DSC1B1_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_SHIFT                0


/****************************************************************************
 * Dsc1b1 :: dfe_vga_ctrl4
 ***************************************************************************/
/* Dsc1b1 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */
#define DSC1B1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK                0xfc00
#define DSC1B1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS                6
#define DSC1B1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT               10

/* Dsc1b1 :: dfe_vga_ctrl4 :: vga_cor_sel_e [09:05] */
#define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_E_MASK                    0x03e0
#define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_E_ALIGN                   0
#define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_E_BITS                    5
#define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_E_SHIFT                   5

/* Dsc1b1 :: dfe_vga_ctrl4 :: vga_cor_sel_o [04:00] */
#define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_O_MASK                    0x001f
#define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_O_ALIGN                   0
#define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_O_BITS                    5
#define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_O_SHIFT                   0


/****************************************************************************
 * Dsc1b1 :: dfe_vga_ctrl5
 ***************************************************************************/
/* Dsc1b1 :: dfe_vga_ctrl5 :: reserved_for_eco0 [15:10] */
#define DSC1B1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_MASK                0xfc00
#define DSC1B1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_BITS                6
#define DSC1B1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_SHIFT               10

/* Dsc1b1 :: dfe_vga_ctrl5 :: dfe_cor_sel_e [09:05] */
#define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_E_MASK                    0x03e0
#define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_E_ALIGN                   0
#define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_E_BITS                    5
#define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_E_SHIFT                   5

/* Dsc1b1 :: dfe_vga_ctrl5 :: dfe_cor_sel_o [04:00] */
#define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_O_MASK                    0x001f
#define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_O_ALIGN                   0
#define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_O_BITS                    5
#define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_O_SHIFT                   0


/****************************************************************************
 * Dsc1b1 :: dsc_ana_ctrl0
 ***************************************************************************/
/* Dsc1b1 :: dsc_ana_ctrl0 :: force_odd_ctrl [15:15] */
#define DSC1B1_DSC_ANA_CTRL0_FORCE_ODD_CTRL_MASK                   0x8000
#define DSC1B1_DSC_ANA_CTRL0_FORCE_ODD_CTRL_ALIGN                  0
#define DSC1B1_DSC_ANA_CTRL0_FORCE_ODD_CTRL_BITS                   1
#define DSC1B1_DSC_ANA_CTRL0_FORCE_ODD_CTRL_SHIFT                  15

/* Dsc1b1 :: dsc_ana_ctrl0 :: p1_odd_ctrl [14:10] */
#define DSC1B1_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK                      0x7c00
#define DSC1B1_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN                     0
#define DSC1B1_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS                      5
#define DSC1B1_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT                     10

/* Dsc1b1 :: dsc_ana_ctrl0 :: d_odd_ctrl [09:05] */
#define DSC1B1_DSC_ANA_CTRL0_D_ODD_CTRL_MASK                       0x03e0
#define DSC1B1_DSC_ANA_CTRL0_D_ODD_CTRL_ALIGN                      0
#define DSC1B1_DSC_ANA_CTRL0_D_ODD_CTRL_BITS                       5
#define DSC1B1_DSC_ANA_CTRL0_D_ODD_CTRL_SHIFT                      5

/* Dsc1b1 :: dsc_ana_ctrl0 :: m1_odd_ctrl [04:00] */
#define DSC1B1_DSC_ANA_CTRL0_M1_ODD_CTRL_MASK                      0x001f
#define DSC1B1_DSC_ANA_CTRL0_M1_ODD_CTRL_ALIGN                     0
#define DSC1B1_DSC_ANA_CTRL0_M1_ODD_CTRL_BITS                      5
#define DSC1B1_DSC_ANA_CTRL0_M1_ODD_CTRL_SHIFT                     0


/****************************************************************************
 * Dsc1b1 :: dsc_ana_ctrl1
 ***************************************************************************/
/* Dsc1b1 :: dsc_ana_ctrl1 :: force_evn_ctrl [15:15] */
#define DSC1B1_DSC_ANA_CTRL1_FORCE_EVN_CTRL_MASK                   0x8000
#define DSC1B1_DSC_ANA_CTRL1_FORCE_EVN_CTRL_ALIGN                  0
#define DSC1B1_DSC_ANA_CTRL1_FORCE_EVN_CTRL_BITS                   1
#define DSC1B1_DSC_ANA_CTRL1_FORCE_EVN_CTRL_SHIFT                  15

/* Dsc1b1 :: dsc_ana_ctrl1 :: p1_evn_ctrl [14:10] */
#define DSC1B1_DSC_ANA_CTRL1_P1_EVN_CTRL_MASK                      0x7c00
#define DSC1B1_DSC_ANA_CTRL1_P1_EVN_CTRL_ALIGN                     0
#define DSC1B1_DSC_ANA_CTRL1_P1_EVN_CTRL_BITS                      5
#define DSC1B1_DSC_ANA_CTRL1_P1_EVN_CTRL_SHIFT                     10

/* Dsc1b1 :: dsc_ana_ctrl1 :: d_evn_ctrl [09:05] */
#define DSC1B1_DSC_ANA_CTRL1_D_EVN_CTRL_MASK                       0x03e0
#define DSC1B1_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN                      0
#define DSC1B1_DSC_ANA_CTRL1_D_EVN_CTRL_BITS                       5
#define DSC1B1_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT                      5

/* Dsc1b1 :: dsc_ana_ctrl1 :: m1_evn_ctrl [04:00] */
#define DSC1B1_DSC_ANA_CTRL1_M1_EVN_CTRL_MASK                      0x001f
#define DSC1B1_DSC_ANA_CTRL1_M1_EVN_CTRL_ALIGN                     0
#define DSC1B1_DSC_ANA_CTRL1_M1_EVN_CTRL_BITS                      5
#define DSC1B1_DSC_ANA_CTRL1_M1_EVN_CTRL_SHIFT                     0


/****************************************************************************
 * Dsc1b1 :: dsc_ana_ctrl2
 ***************************************************************************/
/* Dsc1b1 :: dsc_ana_ctrl2 :: br_offset_pd [15:15] */
#define DSC1B1_DSC_ANA_CTRL2_BR_OFFSET_PD_MASK                     0x8000
#define DSC1B1_DSC_ANA_CTRL2_BR_OFFSET_PD_ALIGN                    0
#define DSC1B1_DSC_ANA_CTRL2_BR_OFFSET_PD_BITS                     1
#define DSC1B1_DSC_ANA_CTRL2_BR_OFFSET_PD_SHIFT                    15

/* Dsc1b1 :: dsc_ana_ctrl2 :: br_en_hgain [14:14] */
#define DSC1B1_DSC_ANA_CTRL2_BR_EN_HGAIN_MASK                      0x4000
#define DSC1B1_DSC_ANA_CTRL2_BR_EN_HGAIN_ALIGN                     0
#define DSC1B1_DSC_ANA_CTRL2_BR_EN_HGAIN_BITS                      1
#define DSC1B1_DSC_ANA_CTRL2_BR_EN_HGAIN_SHIFT                     14

/* Dsc1b1 :: dsc_ana_ctrl2 :: br_en_dfe_clk [13:13] */
#define DSC1B1_DSC_ANA_CTRL2_BR_EN_DFE_CLK_MASK                    0x2000
#define DSC1B1_DSC_ANA_CTRL2_BR_EN_DFE_CLK_ALIGN                   0
#define DSC1B1_DSC_ANA_CTRL2_BR_EN_DFE_CLK_BITS                    1
#define DSC1B1_DSC_ANA_CTRL2_BR_EN_DFE_CLK_SHIFT                   13

/* Dsc1b1 :: dsc_ana_ctrl2 :: br_pd_ch_p1 [12:12] */
#define DSC1B1_DSC_ANA_CTRL2_BR_PD_CH_P1_MASK                      0x1000
#define DSC1B1_DSC_ANA_CTRL2_BR_PD_CH_P1_ALIGN                     0
#define DSC1B1_DSC_ANA_CTRL2_BR_PD_CH_P1_BITS                      1
#define DSC1B1_DSC_ANA_CTRL2_BR_PD_CH_P1_SHIFT                     12

/* Dsc1b1 :: dsc_ana_ctrl2 :: osr_offset_pd [11:11] */
#define DSC1B1_DSC_ANA_CTRL2_OSR_OFFSET_PD_MASK                    0x0800
#define DSC1B1_DSC_ANA_CTRL2_OSR_OFFSET_PD_ALIGN                   0
#define DSC1B1_DSC_ANA_CTRL2_OSR_OFFSET_PD_BITS                    1
#define DSC1B1_DSC_ANA_CTRL2_OSR_OFFSET_PD_SHIFT                   11

/* Dsc1b1 :: dsc_ana_ctrl2 :: osr_en_hgain [10:10] */
#define DSC1B1_DSC_ANA_CTRL2_OSR_EN_HGAIN_MASK                     0x0400
#define DSC1B1_DSC_ANA_CTRL2_OSR_EN_HGAIN_ALIGN                    0
#define DSC1B1_DSC_ANA_CTRL2_OSR_EN_HGAIN_BITS                     1
#define DSC1B1_DSC_ANA_CTRL2_OSR_EN_HGAIN_SHIFT                    10

/* Dsc1b1 :: dsc_ana_ctrl2 :: osr_en_dfe_clk [09:09] */
#define DSC1B1_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_MASK                   0x0200
#define DSC1B1_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_ALIGN                  0
#define DSC1B1_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_BITS                   1
#define DSC1B1_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_SHIFT                  9

/* Dsc1b1 :: dsc_ana_ctrl2 :: osr_pd_ch_p1 [08:08] */
#define DSC1B1_DSC_ANA_CTRL2_OSR_PD_CH_P1_MASK                     0x0100
#define DSC1B1_DSC_ANA_CTRL2_OSR_PD_CH_P1_ALIGN                    0
#define DSC1B1_DSC_ANA_CTRL2_OSR_PD_CH_P1_BITS                     1
#define DSC1B1_DSC_ANA_CTRL2_OSR_PD_CH_P1_SHIFT                    8

/* Dsc1b1 :: dsc_ana_ctrl2 :: force_rx_m1_thresh_zero [07:07] */
#define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_MASK          0x0080
#define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_ALIGN         0
#define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_BITS          1
#define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_SHIFT         7

/* Dsc1b1 :: dsc_ana_ctrl2 :: rx_m1_thresh_zero [06:06] */
#define DSC1B1_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_MASK                0x0040
#define DSC1B1_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_ALIGN               0
#define DSC1B1_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_BITS                1
#define DSC1B1_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_SHIFT               6

/* Dsc1b1 :: dsc_ana_ctrl2 :: rx_thresh_sel [05:04] */
#define DSC1B1_DSC_ANA_CTRL2_RX_THRESH_SEL_MASK                    0x0030
#define DSC1B1_DSC_ANA_CTRL2_RX_THRESH_SEL_ALIGN                   0
#define DSC1B1_DSC_ANA_CTRL2_RX_THRESH_SEL_BITS                    2
#define DSC1B1_DSC_ANA_CTRL2_RX_THRESH_SEL_SHIFT                   4

/* Dsc1b1 :: dsc_ana_ctrl2 :: force_rx_pf_ctrl [03:03] */
#define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_MASK                 0x0008
#define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_ALIGN                0
#define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_BITS                 1
#define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_SHIFT                3

/* Dsc1b1 :: dsc_ana_ctrl2 :: rx_pf_ctrl [02:00] */
#define DSC1B1_DSC_ANA_CTRL2_RX_PF_CTRL_MASK                       0x0007
#define DSC1B1_DSC_ANA_CTRL2_RX_PF_CTRL_ALIGN                      0
#define DSC1B1_DSC_ANA_CTRL2_RX_PF_CTRL_BITS                       3
#define DSC1B1_DSC_ANA_CTRL2_RX_PF_CTRL_SHIFT                      0


/****************************************************************************
 * Dsc1b1 :: dsc_100fx_ctrl
 ***************************************************************************/
/* Dsc1b1 :: dsc_100fx_ctrl :: reserved_for_eco0 [15:11] */
#define DSC1B1_DSC_100FX_CTRL_RESERVED_FOR_ECO0_MASK               0xf800
#define DSC1B1_DSC_100FX_CTRL_RESERVED_FOR_ECO0_ALIGN              0
#define DSC1B1_DSC_100FX_CTRL_RESERVED_FOR_ECO0_BITS               5
#define DSC1B1_DSC_100FX_CTRL_RESERVED_FOR_ECO0_SHIFT              11

/* Dsc1b1 :: dsc_100fx_ctrl :: phase_sat_ctrl_100fx [10:09] */
#define DSC1B1_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_MASK            0x0600
#define DSC1B1_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_ALIGN           0
#define DSC1B1_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_BITS            2
#define DSC1B1_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_SHIFT           9

/* Dsc1b1 :: dsc_100fx_ctrl :: pi_phase_step_mult_100fx [08:08] */
#define DSC1B1_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_MASK        0x0100
#define DSC1B1_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_ALIGN       0
#define DSC1B1_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_BITS        1
#define DSC1B1_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_SHIFT       8

/* Dsc1b1 :: dsc_100fx_ctrl :: cdros_bwsel_integ_100fx [07:04] */
#define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_MASK         0x00f0
#define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_ALIGN        0
#define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_BITS         4
#define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_SHIFT        4

/* Dsc1b1 :: dsc_100fx_ctrl :: cdros_bwsel_prop_100fx [03:00] */
#define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_MASK          0x000f
#define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_ALIGN         0
#define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_BITS          4
#define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_SHIFT         0


/****************************************************************************
 * Dsc1b1 :: dsc_ana_ctrl3
 ***************************************************************************/
/* Dsc1b1 :: dsc_ana_ctrl3 :: reserved_for_eco0 [15:06] */
#define DSC1B1_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_MASK                0xffc0
#define DSC1B1_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B1_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_BITS                10
#define DSC1B1_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_SHIFT               6

/* Dsc1b1 :: dsc_ana_ctrl3 :: force_p1_evn_ctrl [05:05] */
#define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_MASK                0x0020
#define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_ALIGN               0
#define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_BITS                1
#define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_SHIFT               5

/* Dsc1b1 :: dsc_ana_ctrl3 :: force_d_evn_ctrl [04:04] */
#define DSC1B1_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_MASK                 0x0010
#define DSC1B1_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_ALIGN                0
#define DSC1B1_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_BITS                 1
#define DSC1B1_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_SHIFT                4

/* Dsc1b1 :: dsc_ana_ctrl3 :: force_m1_evn_ctrl [03:03] */
#define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_MASK                0x0008
#define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_ALIGN               0
#define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_BITS                1
#define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_SHIFT               3

/* Dsc1b1 :: dsc_ana_ctrl3 :: force_p1_odd_ctrl [02:02] */
#define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_MASK                0x0004
#define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_ALIGN               0
#define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_BITS                1
#define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_SHIFT               2

/* Dsc1b1 :: dsc_ana_ctrl3 :: force_d_odd_ctrl [01:01] */
#define DSC1B1_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_MASK                 0x0002
#define DSC1B1_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_ALIGN                0
#define DSC1B1_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_BITS                 1
#define DSC1B1_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_SHIFT                1

/* Dsc1b1 :: dsc_ana_ctrl3 :: force_m1_odd_ctrl [00:00] */
#define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_MASK                0x0001
#define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_ALIGN               0
#define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_BITS                1
#define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_SHIFT               0


/****************************************************************************
 * Hypercore_USER_Dsc1b2
 ***************************************************************************/
/****************************************************************************
 * Dsc1b2 :: cdr_ctrl0
 ***************************************************************************/
/* Dsc1b2 :: cdr_ctrl0 :: reserved_for_eco0 [15:13] */
#define DSC1B2_CDR_CTRL0_RESERVED_FOR_ECO0_MASK                    0xe000
#define DSC1B2_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC1B2_CDR_CTRL0_RESERVED_FOR_ECO0_BITS                    3
#define DSC1B2_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT                   13

/* Dsc1b2 :: cdr_ctrl0 :: cdrbr_polarity [12:12] */
#define DSC1B2_CDR_CTRL0_CDRBR_POLARITY_MASK                       0x1000
#define DSC1B2_CDR_CTRL0_CDRBR_POLARITY_ALIGN                      0
#define DSC1B2_CDR_CTRL0_CDRBR_POLARITY_BITS                       1
#define DSC1B2_CDR_CTRL0_CDRBR_POLARITY_SHIFT                      12

/* Dsc1b2 :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */
#define DSC1B2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK                   0x0800
#define DSC1B2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN                  0
#define DSC1B2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS                   1
#define DSC1B2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT                  11

/* Dsc1b2 :: cdr_ctrl0 :: cdros_rising_edge [10:10] */
#define DSC1B2_CDR_CTRL0_CDROS_RISING_EDGE_MASK                    0x0400
#define DSC1B2_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN                   0
#define DSC1B2_CDR_CTRL0_CDROS_RISING_EDGE_BITS                    1
#define DSC1B2_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT                   10

/* Dsc1b2 :: cdr_ctrl0 :: cdros_falling_edge [09:09] */
#define DSC1B2_CDR_CTRL0_CDROS_FALLING_EDGE_MASK                   0x0200
#define DSC1B2_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN                  0
#define DSC1B2_CDR_CTRL0_CDROS_FALLING_EDGE_BITS                   1
#define DSC1B2_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT                  9

/* Dsc1b2 :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */
#define DSC1B2_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK                 0x0180
#define DSC1B2_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN                0
#define DSC1B2_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS                 2
#define DSC1B2_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT                7

/* Dsc1b2 :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */
#define DSC1B2_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK                  0x0040
#define DSC1B2_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN                 0
#define DSC1B2_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS                  1
#define DSC1B2_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT                 6

/* Dsc1b2 :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */
#define DSC1B2_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK                  0x0020
#define DSC1B2_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN                 0
#define DSC1B2_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS                  1
#define DSC1B2_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT                 5

/* Dsc1b2 :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */
#define DSC1B2_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK                    0x0010
#define DSC1B2_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN                   0
#define DSC1B2_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS                    1
#define DSC1B2_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT                   4

/* Dsc1b2 :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */
#define DSC1B2_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK                    0x0008
#define DSC1B2_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN                   0
#define DSC1B2_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS                    1
#define DSC1B2_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT                   3

/* Dsc1b2 :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */
#define DSC1B2_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK                      0x0004
#define DSC1B2_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN                     0
#define DSC1B2_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS                      1
#define DSC1B2_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT                     2

/* Dsc1b2 :: cdr_ctrl0 :: cdr_freq_en [01:01] */
#define DSC1B2_CDR_CTRL0_CDR_FREQ_EN_MASK                          0x0002
#define DSC1B2_CDR_CTRL0_CDR_FREQ_EN_ALIGN                         0
#define DSC1B2_CDR_CTRL0_CDR_FREQ_EN_BITS                          1
#define DSC1B2_CDR_CTRL0_CDR_FREQ_EN_SHIFT                         1

/* Dsc1b2 :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */
#define DSC1B2_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK                 0x0001
#define DSC1B2_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN                0
#define DSC1B2_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS                 1
#define DSC1B2_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT                0


/****************************************************************************
 * Dsc1b2 :: cdr_ctrl1
 ***************************************************************************/
/* Dsc1b2 :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */
#define DSC1B2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK                0xffff
#define DSC1B2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN               0
#define DSC1B2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS                16
#define DSC1B2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT               0


/****************************************************************************
 * Dsc1b2 :: cdr_ctrl2
 ***************************************************************************/
/* Dsc1b2 :: cdr_ctrl2 :: reserved_for_eco0 [15:06] */
#define DSC1B2_CDR_CTRL2_RESERVED_FOR_ECO0_MASK                    0xffc0
#define DSC1B2_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC1B2_CDR_CTRL2_RESERVED_FOR_ECO0_BITS                    10
#define DSC1B2_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT                   6

/* Dsc1b2 :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */
#define DSC1B2_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK               0x003f
#define DSC1B2_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN              0
#define DSC1B2_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS               6
#define DSC1B2_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT              0


/****************************************************************************
 * Dsc1b2 :: pi_ctrl0
 ***************************************************************************/
/* Dsc1b2 :: pi_ctrl0 :: pi_cw_rst [15:15] */
#define DSC1B2_PI_CTRL0_PI_CW_RST_MASK                             0x8000
#define DSC1B2_PI_CTRL0_PI_CW_RST_ALIGN                            0
#define DSC1B2_PI_CTRL0_PI_CW_RST_BITS                             1
#define DSC1B2_PI_CTRL0_PI_CW_RST_SHIFT                            15

/* Dsc1b2 :: pi_ctrl0 :: intrp_tmuxSelect [14:12] */
#define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_MASK                      0x7000
#define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_ALIGN                     0
#define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_BITS                      3
#define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_SHIFT                     12
#define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_lsb             0
#define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_msb             1
#define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_lsb           2
#define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_msb           3
#define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_lsb            4
#define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_msb            5
#define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_lsb          6
#define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_msb          7

/* Dsc1b2 :: pi_ctrl0 :: reserved_for_eco0 [11:11] */
#define DSC1B2_PI_CTRL0_RESERVED_FOR_ECO0_MASK                     0x0800
#define DSC1B2_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC1B2_PI_CTRL0_RESERVED_FOR_ECO0_BITS                     1
#define DSC1B2_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT                    11

/* Dsc1b2 :: pi_ctrl0 :: pi_phase_invert [10:10] */
#define DSC1B2_PI_CTRL0_PI_PHASE_INVERT_MASK                       0x0400
#define DSC1B2_PI_CTRL0_PI_PHASE_INVERT_ALIGN                      0
#define DSC1B2_PI_CTRL0_PI_PHASE_INVERT_BITS                       1
#define DSC1B2_PI_CTRL0_PI_PHASE_INVERT_SHIFT                      10

/* Dsc1b2 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */
#define DSC1B2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK                0x0200
#define DSC1B2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN               0
#define DSC1B2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS                1
#define DSC1B2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT               9

/* Dsc1b2 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */
#define DSC1B2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK              0x0100
#define DSC1B2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN             0
#define DSC1B2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS              1
#define DSC1B2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT             8

/* Dsc1b2 :: pi_ctrl0 :: pi_phase_dec [07:07] */
#define DSC1B2_PI_CTRL0_PI_PHASE_DEC_MASK                          0x0080
#define DSC1B2_PI_CTRL0_PI_PHASE_DEC_ALIGN                         0
#define DSC1B2_PI_CTRL0_PI_PHASE_DEC_BITS                          1
#define DSC1B2_PI_CTRL0_PI_PHASE_DEC_SHIFT                         7

/* Dsc1b2 :: pi_ctrl0 :: pi_phase_inc [06:06] */
#define DSC1B2_PI_CTRL0_PI_PHASE_INC_MASK                          0x0040
#define DSC1B2_PI_CTRL0_PI_PHASE_INC_ALIGN                         0
#define DSC1B2_PI_CTRL0_PI_PHASE_INC_BITS                          1
#define DSC1B2_PI_CTRL0_PI_PHASE_INC_SHIFT                         6

/* Dsc1b2 :: pi_ctrl0 :: pi_phase_strobe [05:05] */
#define DSC1B2_PI_CTRL0_PI_PHASE_STROBE_MASK                       0x0020
#define DSC1B2_PI_CTRL0_PI_PHASE_STROBE_ALIGN                      0
#define DSC1B2_PI_CTRL0_PI_PHASE_STROBE_BITS                       1
#define DSC1B2_PI_CTRL0_PI_PHASE_STROBE_SHIFT                      5

/* Dsc1b2 :: pi_ctrl0 :: pi_phase_delta [04:01] */
#define DSC1B2_PI_CTRL0_PI_PHASE_DELTA_MASK                        0x001e
#define DSC1B2_PI_CTRL0_PI_PHASE_DELTA_ALIGN                       0
#define DSC1B2_PI_CTRL0_PI_PHASE_DELTA_BITS                        4
#define DSC1B2_PI_CTRL0_PI_PHASE_DELTA_SHIFT                       1

/* Dsc1b2 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */
#define DSC1B2_PI_CTRL0_PI_PHASE_STEP_MULT_MASK                    0x0001
#define DSC1B2_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN                   0
#define DSC1B2_PI_CTRL0_PI_PHASE_STEP_MULT_BITS                    1
#define DSC1B2_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT                   0


/****************************************************************************
 * Dsc1b2 :: dfe_vga_ctrl0
 ***************************************************************************/
/* Dsc1b2 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:08] */
#define DSC1B2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK                0xff00
#define DSC1B2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS                8
#define DSC1B2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT               8

/* Dsc1b2 :: dfe_vga_ctrl0 :: vga_timer_ctrl [07:06] */
#define DSC1B2_DFE_VGA_CTRL0_VGA_TIMER_CTRL_MASK                   0x00c0
#define DSC1B2_DFE_VGA_CTRL0_VGA_TIMER_CTRL_ALIGN                  0
#define DSC1B2_DFE_VGA_CTRL0_VGA_TIMER_CTRL_BITS                   2
#define DSC1B2_DFE_VGA_CTRL0_VGA_TIMER_CTRL_SHIFT                  6

/* Dsc1b2 :: dfe_vga_ctrl0 :: vga_polarity [05:05] */
#define DSC1B2_DFE_VGA_CTRL0_VGA_POLARITY_MASK                     0x0020
#define DSC1B2_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN                    0
#define DSC1B2_DFE_VGA_CTRL0_VGA_POLARITY_BITS                     1
#define DSC1B2_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT                    5

/* Dsc1b2 :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */
#define DSC1B2_DFE_VGA_CTRL0_DFE_POLARITY_MASK                     0x0010
#define DSC1B2_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN                    0
#define DSC1B2_DFE_VGA_CTRL0_DFE_POLARITY_BITS                     1
#define DSC1B2_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT                    4

/* Dsc1b2 :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */
#define DSC1B2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK                 0x0008
#define DSC1B2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN                0
#define DSC1B2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS                 1
#define DSC1B2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT                3

/* Dsc1b2 :: dfe_vga_ctrl0 :: sum_m1err [02:02] */
#define DSC1B2_DFE_VGA_CTRL0_SUM_M1ERR_MASK                        0x0004
#define DSC1B2_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN                       0
#define DSC1B2_DFE_VGA_CTRL0_SUM_M1ERR_BITS                        1
#define DSC1B2_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT                       2

/* Dsc1b2 :: dfe_vga_ctrl0 :: trnsum_en [01:01] */
#define DSC1B2_DFE_VGA_CTRL0_TRNSUM_EN_MASK                        0x0002
#define DSC1B2_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN                       0
#define DSC1B2_DFE_VGA_CTRL0_TRNSUM_EN_BITS                        1
#define DSC1B2_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT                       1

/* Dsc1b2 :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */
#define DSC1B2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK                    0x0001
#define DSC1B2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN                   0
#define DSC1B2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS                    1
#define DSC1B2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT                   0


/****************************************************************************
 * Dsc1b2 :: dfe_vga_ctrl1
 ***************************************************************************/
/* Dsc1b2 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:13] */
#define DSC1B2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK                0xe000
#define DSC1B2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS                3
#define DSC1B2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT               13

/* Dsc1b2 :: dfe_vga_ctrl1 :: dfe_write_val [12:07] */
#define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_VAL_MASK                    0x1f80
#define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_VAL_ALIGN                   0
#define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_VAL_BITS                    6
#define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_VAL_SHIFT                   7

/* Dsc1b2 :: dfe_vga_ctrl1 :: dfe_write_en [06:06] */
#define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_EN_MASK                     0x0040
#define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_EN_ALIGN                    0
#define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_EN_BITS                     1
#define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_EN_SHIFT                    6

/* Dsc1b2 :: dfe_vga_ctrl1 :: vga_write_val [05:01] */
#define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_VAL_MASK                    0x003e
#define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_VAL_ALIGN                   0
#define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_VAL_BITS                    5
#define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_VAL_SHIFT                   1

/* Dsc1b2 :: dfe_vga_ctrl1 :: vga_write_en [00:00] */
#define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_EN_MASK                     0x0001
#define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_EN_ALIGN                    0
#define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_EN_BITS                     1
#define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_EN_SHIFT                    0


/****************************************************************************
 * Dsc1b2 :: dfe_vga_ctrl2
 ***************************************************************************/
/* Dsc1b2 :: dfe_vga_ctrl2 :: reserved_for_eco0 [15:14] */
#define DSC1B2_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_MASK                0xc000
#define DSC1B2_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B2_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_BITS                2
#define DSC1B2_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_SHIFT               14

/* Dsc1b2 :: dfe_vga_ctrl2 :: trnsum_otap_en [13:07] */
#define DSC1B2_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_MASK                   0x3f80
#define DSC1B2_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_ALIGN                  0
#define DSC1B2_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_BITS                   7
#define DSC1B2_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_SHIFT                  7

/* Dsc1b2 :: dfe_vga_ctrl2 :: trnsum_etap_en [06:00] */
#define DSC1B2_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_MASK                   0x007f
#define DSC1B2_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_ALIGN                  0
#define DSC1B2_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_BITS                   7
#define DSC1B2_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_SHIFT                  0


/****************************************************************************
 * Dsc1b2 :: dfe_vga_ctrl3
 ***************************************************************************/
/* Dsc1b2 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:14] */
#define DSC1B2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK                0xc000
#define DSC1B2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS                2
#define DSC1B2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT               14

/* Dsc1b2 :: dfe_vga_ctrl3 :: trnsum_otap_sign [13:07] */
#define DSC1B2_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_MASK                 0x3f80
#define DSC1B2_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_ALIGN                0
#define DSC1B2_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_BITS                 7
#define DSC1B2_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_SHIFT                7

/* Dsc1b2 :: dfe_vga_ctrl3 :: trnsum_etap_sign [06:00] */
#define DSC1B2_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_MASK                 0x007f
#define DSC1B2_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_ALIGN                0
#define DSC1B2_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_BITS                 7
#define DSC1B2_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_SHIFT                0


/****************************************************************************
 * Dsc1b2 :: dfe_vga_ctrl4
 ***************************************************************************/
/* Dsc1b2 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */
#define DSC1B2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK                0xfc00
#define DSC1B2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS                6
#define DSC1B2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT               10

/* Dsc1b2 :: dfe_vga_ctrl4 :: vga_cor_sel_e [09:05] */
#define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_E_MASK                    0x03e0
#define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_E_ALIGN                   0
#define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_E_BITS                    5
#define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_E_SHIFT                   5

/* Dsc1b2 :: dfe_vga_ctrl4 :: vga_cor_sel_o [04:00] */
#define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_O_MASK                    0x001f
#define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_O_ALIGN                   0
#define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_O_BITS                    5
#define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_O_SHIFT                   0


/****************************************************************************
 * Dsc1b2 :: dfe_vga_ctrl5
 ***************************************************************************/
/* Dsc1b2 :: dfe_vga_ctrl5 :: reserved_for_eco0 [15:10] */
#define DSC1B2_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_MASK                0xfc00
#define DSC1B2_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B2_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_BITS                6
#define DSC1B2_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_SHIFT               10

/* Dsc1b2 :: dfe_vga_ctrl5 :: dfe_cor_sel_e [09:05] */
#define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_E_MASK                    0x03e0
#define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_E_ALIGN                   0
#define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_E_BITS                    5
#define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_E_SHIFT                   5

/* Dsc1b2 :: dfe_vga_ctrl5 :: dfe_cor_sel_o [04:00] */
#define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_O_MASK                    0x001f
#define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_O_ALIGN                   0
#define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_O_BITS                    5
#define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_O_SHIFT                   0


/****************************************************************************
 * Dsc1b2 :: dsc_ana_ctrl0
 ***************************************************************************/
/* Dsc1b2 :: dsc_ana_ctrl0 :: force_odd_ctrl [15:15] */
#define DSC1B2_DSC_ANA_CTRL0_FORCE_ODD_CTRL_MASK                   0x8000
#define DSC1B2_DSC_ANA_CTRL0_FORCE_ODD_CTRL_ALIGN                  0
#define DSC1B2_DSC_ANA_CTRL0_FORCE_ODD_CTRL_BITS                   1
#define DSC1B2_DSC_ANA_CTRL0_FORCE_ODD_CTRL_SHIFT                  15

/* Dsc1b2 :: dsc_ana_ctrl0 :: p1_odd_ctrl [14:10] */
#define DSC1B2_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK                      0x7c00
#define DSC1B2_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN                     0
#define DSC1B2_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS                      5
#define DSC1B2_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT                     10

/* Dsc1b2 :: dsc_ana_ctrl0 :: d_odd_ctrl [09:05] */
#define DSC1B2_DSC_ANA_CTRL0_D_ODD_CTRL_MASK                       0x03e0
#define DSC1B2_DSC_ANA_CTRL0_D_ODD_CTRL_ALIGN                      0
#define DSC1B2_DSC_ANA_CTRL0_D_ODD_CTRL_BITS                       5
#define DSC1B2_DSC_ANA_CTRL0_D_ODD_CTRL_SHIFT                      5

/* Dsc1b2 :: dsc_ana_ctrl0 :: m1_odd_ctrl [04:00] */
#define DSC1B2_DSC_ANA_CTRL0_M1_ODD_CTRL_MASK                      0x001f
#define DSC1B2_DSC_ANA_CTRL0_M1_ODD_CTRL_ALIGN                     0
#define DSC1B2_DSC_ANA_CTRL0_M1_ODD_CTRL_BITS                      5
#define DSC1B2_DSC_ANA_CTRL0_M1_ODD_CTRL_SHIFT                     0


/****************************************************************************
 * Dsc1b2 :: dsc_ana_ctrl1
 ***************************************************************************/
/* Dsc1b2 :: dsc_ana_ctrl1 :: force_evn_ctrl [15:15] */
#define DSC1B2_DSC_ANA_CTRL1_FORCE_EVN_CTRL_MASK                   0x8000
#define DSC1B2_DSC_ANA_CTRL1_FORCE_EVN_CTRL_ALIGN                  0
#define DSC1B2_DSC_ANA_CTRL1_FORCE_EVN_CTRL_BITS                   1
#define DSC1B2_DSC_ANA_CTRL1_FORCE_EVN_CTRL_SHIFT                  15

/* Dsc1b2 :: dsc_ana_ctrl1 :: p1_evn_ctrl [14:10] */
#define DSC1B2_DSC_ANA_CTRL1_P1_EVN_CTRL_MASK                      0x7c00
#define DSC1B2_DSC_ANA_CTRL1_P1_EVN_CTRL_ALIGN                     0
#define DSC1B2_DSC_ANA_CTRL1_P1_EVN_CTRL_BITS                      5
#define DSC1B2_DSC_ANA_CTRL1_P1_EVN_CTRL_SHIFT                     10

/* Dsc1b2 :: dsc_ana_ctrl1 :: d_evn_ctrl [09:05] */
#define DSC1B2_DSC_ANA_CTRL1_D_EVN_CTRL_MASK                       0x03e0
#define DSC1B2_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN                      0
#define DSC1B2_DSC_ANA_CTRL1_D_EVN_CTRL_BITS                       5
#define DSC1B2_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT                      5

/* Dsc1b2 :: dsc_ana_ctrl1 :: m1_evn_ctrl [04:00] */
#define DSC1B2_DSC_ANA_CTRL1_M1_EVN_CTRL_MASK                      0x001f
#define DSC1B2_DSC_ANA_CTRL1_M1_EVN_CTRL_ALIGN                     0
#define DSC1B2_DSC_ANA_CTRL1_M1_EVN_CTRL_BITS                      5
#define DSC1B2_DSC_ANA_CTRL1_M1_EVN_CTRL_SHIFT                     0


/****************************************************************************
 * Dsc1b2 :: dsc_ana_ctrl2
 ***************************************************************************/
/* Dsc1b2 :: dsc_ana_ctrl2 :: br_offset_pd [15:15] */
#define DSC1B2_DSC_ANA_CTRL2_BR_OFFSET_PD_MASK                     0x8000
#define DSC1B2_DSC_ANA_CTRL2_BR_OFFSET_PD_ALIGN                    0
#define DSC1B2_DSC_ANA_CTRL2_BR_OFFSET_PD_BITS                     1
#define DSC1B2_DSC_ANA_CTRL2_BR_OFFSET_PD_SHIFT                    15

/* Dsc1b2 :: dsc_ana_ctrl2 :: br_en_hgain [14:14] */
#define DSC1B2_DSC_ANA_CTRL2_BR_EN_HGAIN_MASK                      0x4000
#define DSC1B2_DSC_ANA_CTRL2_BR_EN_HGAIN_ALIGN                     0
#define DSC1B2_DSC_ANA_CTRL2_BR_EN_HGAIN_BITS                      1
#define DSC1B2_DSC_ANA_CTRL2_BR_EN_HGAIN_SHIFT                     14

/* Dsc1b2 :: dsc_ana_ctrl2 :: br_en_dfe_clk [13:13] */
#define DSC1B2_DSC_ANA_CTRL2_BR_EN_DFE_CLK_MASK                    0x2000
#define DSC1B2_DSC_ANA_CTRL2_BR_EN_DFE_CLK_ALIGN                   0
#define DSC1B2_DSC_ANA_CTRL2_BR_EN_DFE_CLK_BITS                    1
#define DSC1B2_DSC_ANA_CTRL2_BR_EN_DFE_CLK_SHIFT                   13

/* Dsc1b2 :: dsc_ana_ctrl2 :: br_pd_ch_p1 [12:12] */
#define DSC1B2_DSC_ANA_CTRL2_BR_PD_CH_P1_MASK                      0x1000
#define DSC1B2_DSC_ANA_CTRL2_BR_PD_CH_P1_ALIGN                     0
#define DSC1B2_DSC_ANA_CTRL2_BR_PD_CH_P1_BITS                      1
#define DSC1B2_DSC_ANA_CTRL2_BR_PD_CH_P1_SHIFT                     12

/* Dsc1b2 :: dsc_ana_ctrl2 :: osr_offset_pd [11:11] */
#define DSC1B2_DSC_ANA_CTRL2_OSR_OFFSET_PD_MASK                    0x0800
#define DSC1B2_DSC_ANA_CTRL2_OSR_OFFSET_PD_ALIGN                   0
#define DSC1B2_DSC_ANA_CTRL2_OSR_OFFSET_PD_BITS                    1
#define DSC1B2_DSC_ANA_CTRL2_OSR_OFFSET_PD_SHIFT                   11

/* Dsc1b2 :: dsc_ana_ctrl2 :: osr_en_hgain [10:10] */
#define DSC1B2_DSC_ANA_CTRL2_OSR_EN_HGAIN_MASK                     0x0400
#define DSC1B2_DSC_ANA_CTRL2_OSR_EN_HGAIN_ALIGN                    0
#define DSC1B2_DSC_ANA_CTRL2_OSR_EN_HGAIN_BITS                     1
#define DSC1B2_DSC_ANA_CTRL2_OSR_EN_HGAIN_SHIFT                    10

/* Dsc1b2 :: dsc_ana_ctrl2 :: osr_en_dfe_clk [09:09] */
#define DSC1B2_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_MASK                   0x0200
#define DSC1B2_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_ALIGN                  0
#define DSC1B2_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_BITS                   1
#define DSC1B2_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_SHIFT                  9

/* Dsc1b2 :: dsc_ana_ctrl2 :: osr_pd_ch_p1 [08:08] */
#define DSC1B2_DSC_ANA_CTRL2_OSR_PD_CH_P1_MASK                     0x0100
#define DSC1B2_DSC_ANA_CTRL2_OSR_PD_CH_P1_ALIGN                    0
#define DSC1B2_DSC_ANA_CTRL2_OSR_PD_CH_P1_BITS                     1
#define DSC1B2_DSC_ANA_CTRL2_OSR_PD_CH_P1_SHIFT                    8

/* Dsc1b2 :: dsc_ana_ctrl2 :: force_rx_m1_thresh_zero [07:07] */
#define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_MASK          0x0080
#define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_ALIGN         0
#define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_BITS          1
#define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_SHIFT         7

/* Dsc1b2 :: dsc_ana_ctrl2 :: rx_m1_thresh_zero [06:06] */
#define DSC1B2_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_MASK                0x0040
#define DSC1B2_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_ALIGN               0
#define DSC1B2_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_BITS                1
#define DSC1B2_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_SHIFT               6

/* Dsc1b2 :: dsc_ana_ctrl2 :: rx_thresh_sel [05:04] */
#define DSC1B2_DSC_ANA_CTRL2_RX_THRESH_SEL_MASK                    0x0030
#define DSC1B2_DSC_ANA_CTRL2_RX_THRESH_SEL_ALIGN                   0
#define DSC1B2_DSC_ANA_CTRL2_RX_THRESH_SEL_BITS                    2
#define DSC1B2_DSC_ANA_CTRL2_RX_THRESH_SEL_SHIFT                   4

/* Dsc1b2 :: dsc_ana_ctrl2 :: force_rx_pf_ctrl [03:03] */
#define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_MASK                 0x0008
#define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_ALIGN                0
#define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_BITS                 1
#define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_SHIFT                3

/* Dsc1b2 :: dsc_ana_ctrl2 :: rx_pf_ctrl [02:00] */
#define DSC1B2_DSC_ANA_CTRL2_RX_PF_CTRL_MASK                       0x0007
#define DSC1B2_DSC_ANA_CTRL2_RX_PF_CTRL_ALIGN                      0
#define DSC1B2_DSC_ANA_CTRL2_RX_PF_CTRL_BITS                       3
#define DSC1B2_DSC_ANA_CTRL2_RX_PF_CTRL_SHIFT                      0


/****************************************************************************
 * Dsc1b2 :: dsc_100fx_ctrl
 ***************************************************************************/
/* Dsc1b2 :: dsc_100fx_ctrl :: reserved_for_eco0 [15:11] */
#define DSC1B2_DSC_100FX_CTRL_RESERVED_FOR_ECO0_MASK               0xf800
#define DSC1B2_DSC_100FX_CTRL_RESERVED_FOR_ECO0_ALIGN              0
#define DSC1B2_DSC_100FX_CTRL_RESERVED_FOR_ECO0_BITS               5
#define DSC1B2_DSC_100FX_CTRL_RESERVED_FOR_ECO0_SHIFT              11

/* Dsc1b2 :: dsc_100fx_ctrl :: phase_sat_ctrl_100fx [10:09] */
#define DSC1B2_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_MASK            0x0600
#define DSC1B2_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_ALIGN           0
#define DSC1B2_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_BITS            2
#define DSC1B2_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_SHIFT           9

/* Dsc1b2 :: dsc_100fx_ctrl :: pi_phase_step_mult_100fx [08:08] */
#define DSC1B2_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_MASK        0x0100
#define DSC1B2_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_ALIGN       0
#define DSC1B2_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_BITS        1
#define DSC1B2_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_SHIFT       8

/* Dsc1b2 :: dsc_100fx_ctrl :: cdros_bwsel_integ_100fx [07:04] */
#define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_MASK         0x00f0
#define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_ALIGN        0
#define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_BITS         4
#define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_SHIFT        4

/* Dsc1b2 :: dsc_100fx_ctrl :: cdros_bwsel_prop_100fx [03:00] */
#define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_MASK          0x000f
#define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_ALIGN         0
#define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_BITS          4
#define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_SHIFT         0


/****************************************************************************
 * Dsc1b2 :: dsc_ana_ctrl3
 ***************************************************************************/
/* Dsc1b2 :: dsc_ana_ctrl3 :: reserved_for_eco0 [15:06] */
#define DSC1B2_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_MASK                0xffc0
#define DSC1B2_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B2_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_BITS                10
#define DSC1B2_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_SHIFT               6

/* Dsc1b2 :: dsc_ana_ctrl3 :: force_p1_evn_ctrl [05:05] */
#define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_MASK                0x0020
#define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_ALIGN               0
#define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_BITS                1
#define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_SHIFT               5

/* Dsc1b2 :: dsc_ana_ctrl3 :: force_d_evn_ctrl [04:04] */
#define DSC1B2_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_MASK                 0x0010
#define DSC1B2_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_ALIGN                0
#define DSC1B2_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_BITS                 1
#define DSC1B2_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_SHIFT                4

/* Dsc1b2 :: dsc_ana_ctrl3 :: force_m1_evn_ctrl [03:03] */
#define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_MASK                0x0008
#define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_ALIGN               0
#define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_BITS                1
#define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_SHIFT               3

/* Dsc1b2 :: dsc_ana_ctrl3 :: force_p1_odd_ctrl [02:02] */
#define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_MASK                0x0004
#define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_ALIGN               0
#define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_BITS                1
#define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_SHIFT               2

/* Dsc1b2 :: dsc_ana_ctrl3 :: force_d_odd_ctrl [01:01] */
#define DSC1B2_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_MASK                 0x0002
#define DSC1B2_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_ALIGN                0
#define DSC1B2_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_BITS                 1
#define DSC1B2_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_SHIFT                1

/* Dsc1b2 :: dsc_ana_ctrl3 :: force_m1_odd_ctrl [00:00] */
#define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_MASK                0x0001
#define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_ALIGN               0
#define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_BITS                1
#define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_SHIFT               0


/****************************************************************************
 * Hypercore_USER_Dsc1b3
 ***************************************************************************/
/****************************************************************************
 * Dsc1b3 :: cdr_ctrl0
 ***************************************************************************/
/* Dsc1b3 :: cdr_ctrl0 :: reserved_for_eco0 [15:13] */
#define DSC1B3_CDR_CTRL0_RESERVED_FOR_ECO0_MASK                    0xe000
#define DSC1B3_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC1B3_CDR_CTRL0_RESERVED_FOR_ECO0_BITS                    3
#define DSC1B3_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT                   13

/* Dsc1b3 :: cdr_ctrl0 :: cdrbr_polarity [12:12] */
#define DSC1B3_CDR_CTRL0_CDRBR_POLARITY_MASK                       0x1000
#define DSC1B3_CDR_CTRL0_CDRBR_POLARITY_ALIGN                      0
#define DSC1B3_CDR_CTRL0_CDRBR_POLARITY_BITS                       1
#define DSC1B3_CDR_CTRL0_CDRBR_POLARITY_SHIFT                      12

/* Dsc1b3 :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */
#define DSC1B3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK                   0x0800
#define DSC1B3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN                  0
#define DSC1B3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS                   1
#define DSC1B3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT                  11

/* Dsc1b3 :: cdr_ctrl0 :: cdros_rising_edge [10:10] */
#define DSC1B3_CDR_CTRL0_CDROS_RISING_EDGE_MASK                    0x0400
#define DSC1B3_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN                   0
#define DSC1B3_CDR_CTRL0_CDROS_RISING_EDGE_BITS                    1
#define DSC1B3_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT                   10

/* Dsc1b3 :: cdr_ctrl0 :: cdros_falling_edge [09:09] */
#define DSC1B3_CDR_CTRL0_CDROS_FALLING_EDGE_MASK                   0x0200
#define DSC1B3_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN                  0
#define DSC1B3_CDR_CTRL0_CDROS_FALLING_EDGE_BITS                   1
#define DSC1B3_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT                  9

/* Dsc1b3 :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */
#define DSC1B3_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK                 0x0180
#define DSC1B3_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN                0
#define DSC1B3_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS                 2
#define DSC1B3_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT                7

/* Dsc1b3 :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */
#define DSC1B3_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK                  0x0040
#define DSC1B3_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN                 0
#define DSC1B3_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS                  1
#define DSC1B3_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT                 6

/* Dsc1b3 :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */
#define DSC1B3_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK                  0x0020
#define DSC1B3_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN                 0
#define DSC1B3_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS                  1
#define DSC1B3_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT                 5

/* Dsc1b3 :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */
#define DSC1B3_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK                    0x0010
#define DSC1B3_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN                   0
#define DSC1B3_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS                    1
#define DSC1B3_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT                   4

/* Dsc1b3 :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */
#define DSC1B3_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK                    0x0008
#define DSC1B3_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN                   0
#define DSC1B3_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS                    1
#define DSC1B3_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT                   3

/* Dsc1b3 :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */
#define DSC1B3_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK                      0x0004
#define DSC1B3_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN                     0
#define DSC1B3_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS                      1
#define DSC1B3_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT                     2

/* Dsc1b3 :: cdr_ctrl0 :: cdr_freq_en [01:01] */
#define DSC1B3_CDR_CTRL0_CDR_FREQ_EN_MASK                          0x0002
#define DSC1B3_CDR_CTRL0_CDR_FREQ_EN_ALIGN                         0
#define DSC1B3_CDR_CTRL0_CDR_FREQ_EN_BITS                          1
#define DSC1B3_CDR_CTRL0_CDR_FREQ_EN_SHIFT                         1

/* Dsc1b3 :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */
#define DSC1B3_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK                 0x0001
#define DSC1B3_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN                0
#define DSC1B3_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS                 1
#define DSC1B3_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT                0


/****************************************************************************
 * Dsc1b3 :: cdr_ctrl1
 ***************************************************************************/
/* Dsc1b3 :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */
#define DSC1B3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK                0xffff
#define DSC1B3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN               0
#define DSC1B3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS                16
#define DSC1B3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT               0


/****************************************************************************
 * Dsc1b3 :: cdr_ctrl2
 ***************************************************************************/
/* Dsc1b3 :: cdr_ctrl2 :: reserved_for_eco0 [15:06] */
#define DSC1B3_CDR_CTRL2_RESERVED_FOR_ECO0_MASK                    0xffc0
#define DSC1B3_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC1B3_CDR_CTRL2_RESERVED_FOR_ECO0_BITS                    10
#define DSC1B3_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT                   6

/* Dsc1b3 :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */
#define DSC1B3_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK               0x003f
#define DSC1B3_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN              0
#define DSC1B3_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS               6
#define DSC1B3_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT              0


/****************************************************************************
 * Dsc1b3 :: pi_ctrl0
 ***************************************************************************/
/* Dsc1b3 :: pi_ctrl0 :: pi_cw_rst [15:15] */
#define DSC1B3_PI_CTRL0_PI_CW_RST_MASK                             0x8000
#define DSC1B3_PI_CTRL0_PI_CW_RST_ALIGN                            0
#define DSC1B3_PI_CTRL0_PI_CW_RST_BITS                             1
#define DSC1B3_PI_CTRL0_PI_CW_RST_SHIFT                            15

/* Dsc1b3 :: pi_ctrl0 :: intrp_tmuxSelect [14:12] */
#define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_MASK                      0x7000
#define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_ALIGN                     0
#define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_BITS                      3
#define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_SHIFT                     12
#define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_lsb             0
#define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_msb             1
#define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_lsb           2
#define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_msb           3
#define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_lsb            4
#define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_msb            5
#define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_lsb          6
#define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_msb          7

/* Dsc1b3 :: pi_ctrl0 :: reserved_for_eco0 [11:11] */
#define DSC1B3_PI_CTRL0_RESERVED_FOR_ECO0_MASK                     0x0800
#define DSC1B3_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC1B3_PI_CTRL0_RESERVED_FOR_ECO0_BITS                     1
#define DSC1B3_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT                    11

/* Dsc1b3 :: pi_ctrl0 :: pi_phase_invert [10:10] */
#define DSC1B3_PI_CTRL0_PI_PHASE_INVERT_MASK                       0x0400
#define DSC1B3_PI_CTRL0_PI_PHASE_INVERT_ALIGN                      0
#define DSC1B3_PI_CTRL0_PI_PHASE_INVERT_BITS                       1
#define DSC1B3_PI_CTRL0_PI_PHASE_INVERT_SHIFT                      10

/* Dsc1b3 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */
#define DSC1B3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK                0x0200
#define DSC1B3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN               0
#define DSC1B3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS                1
#define DSC1B3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT               9

/* Dsc1b3 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */
#define DSC1B3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK              0x0100
#define DSC1B3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN             0
#define DSC1B3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS              1
#define DSC1B3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT             8

/* Dsc1b3 :: pi_ctrl0 :: pi_phase_dec [07:07] */
#define DSC1B3_PI_CTRL0_PI_PHASE_DEC_MASK                          0x0080
#define DSC1B3_PI_CTRL0_PI_PHASE_DEC_ALIGN                         0
#define DSC1B3_PI_CTRL0_PI_PHASE_DEC_BITS                          1
#define DSC1B3_PI_CTRL0_PI_PHASE_DEC_SHIFT                         7

/* Dsc1b3 :: pi_ctrl0 :: pi_phase_inc [06:06] */
#define DSC1B3_PI_CTRL0_PI_PHASE_INC_MASK                          0x0040
#define DSC1B3_PI_CTRL0_PI_PHASE_INC_ALIGN                         0
#define DSC1B3_PI_CTRL0_PI_PHASE_INC_BITS                          1
#define DSC1B3_PI_CTRL0_PI_PHASE_INC_SHIFT                         6

/* Dsc1b3 :: pi_ctrl0 :: pi_phase_strobe [05:05] */
#define DSC1B3_PI_CTRL0_PI_PHASE_STROBE_MASK                       0x0020
#define DSC1B3_PI_CTRL0_PI_PHASE_STROBE_ALIGN                      0
#define DSC1B3_PI_CTRL0_PI_PHASE_STROBE_BITS                       1
#define DSC1B3_PI_CTRL0_PI_PHASE_STROBE_SHIFT                      5

/* Dsc1b3 :: pi_ctrl0 :: pi_phase_delta [04:01] */
#define DSC1B3_PI_CTRL0_PI_PHASE_DELTA_MASK                        0x001e
#define DSC1B3_PI_CTRL0_PI_PHASE_DELTA_ALIGN                       0
#define DSC1B3_PI_CTRL0_PI_PHASE_DELTA_BITS                        4
#define DSC1B3_PI_CTRL0_PI_PHASE_DELTA_SHIFT                       1

/* Dsc1b3 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */
#define DSC1B3_PI_CTRL0_PI_PHASE_STEP_MULT_MASK                    0x0001
#define DSC1B3_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN                   0
#define DSC1B3_PI_CTRL0_PI_PHASE_STEP_MULT_BITS                    1
#define DSC1B3_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT                   0


/****************************************************************************
 * Dsc1b3 :: dfe_vga_ctrl0
 ***************************************************************************/
/* Dsc1b3 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:08] */
#define DSC1B3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK                0xff00
#define DSC1B3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS                8
#define DSC1B3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT               8

/* Dsc1b3 :: dfe_vga_ctrl0 :: vga_timer_ctrl [07:06] */
#define DSC1B3_DFE_VGA_CTRL0_VGA_TIMER_CTRL_MASK                   0x00c0
#define DSC1B3_DFE_VGA_CTRL0_VGA_TIMER_CTRL_ALIGN                  0
#define DSC1B3_DFE_VGA_CTRL0_VGA_TIMER_CTRL_BITS                   2
#define DSC1B3_DFE_VGA_CTRL0_VGA_TIMER_CTRL_SHIFT                  6

/* Dsc1b3 :: dfe_vga_ctrl0 :: vga_polarity [05:05] */
#define DSC1B3_DFE_VGA_CTRL0_VGA_POLARITY_MASK                     0x0020
#define DSC1B3_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN                    0
#define DSC1B3_DFE_VGA_CTRL0_VGA_POLARITY_BITS                     1
#define DSC1B3_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT                    5

/* Dsc1b3 :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */
#define DSC1B3_DFE_VGA_CTRL0_DFE_POLARITY_MASK                     0x0010
#define DSC1B3_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN                    0
#define DSC1B3_DFE_VGA_CTRL0_DFE_POLARITY_BITS                     1
#define DSC1B3_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT                    4

/* Dsc1b3 :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */
#define DSC1B3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK                 0x0008
#define DSC1B3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN                0
#define DSC1B3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS                 1
#define DSC1B3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT                3

/* Dsc1b3 :: dfe_vga_ctrl0 :: sum_m1err [02:02] */
#define DSC1B3_DFE_VGA_CTRL0_SUM_M1ERR_MASK                        0x0004
#define DSC1B3_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN                       0
#define DSC1B3_DFE_VGA_CTRL0_SUM_M1ERR_BITS                        1
#define DSC1B3_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT                       2

/* Dsc1b3 :: dfe_vga_ctrl0 :: trnsum_en [01:01] */
#define DSC1B3_DFE_VGA_CTRL0_TRNSUM_EN_MASK                        0x0002
#define DSC1B3_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN                       0
#define DSC1B3_DFE_VGA_CTRL0_TRNSUM_EN_BITS                        1
#define DSC1B3_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT                       1

/* Dsc1b3 :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */
#define DSC1B3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK                    0x0001
#define DSC1B3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN                   0
#define DSC1B3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS                    1
#define DSC1B3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT                   0


/****************************************************************************
 * Dsc1b3 :: dfe_vga_ctrl1
 ***************************************************************************/
/* Dsc1b3 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:13] */
#define DSC1B3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK                0xe000
#define DSC1B3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS                3
#define DSC1B3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT               13

/* Dsc1b3 :: dfe_vga_ctrl1 :: dfe_write_val [12:07] */
#define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_VAL_MASK                    0x1f80
#define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_VAL_ALIGN                   0
#define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_VAL_BITS                    6
#define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_VAL_SHIFT                   7

/* Dsc1b3 :: dfe_vga_ctrl1 :: dfe_write_en [06:06] */
#define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_EN_MASK                     0x0040
#define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_EN_ALIGN                    0
#define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_EN_BITS                     1
#define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_EN_SHIFT                    6

/* Dsc1b3 :: dfe_vga_ctrl1 :: vga_write_val [05:01] */
#define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_VAL_MASK                    0x003e
#define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_VAL_ALIGN                   0
#define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_VAL_BITS                    5
#define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_VAL_SHIFT                   1

/* Dsc1b3 :: dfe_vga_ctrl1 :: vga_write_en [00:00] */
#define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_EN_MASK                     0x0001
#define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_EN_ALIGN                    0
#define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_EN_BITS                     1
#define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_EN_SHIFT                    0


/****************************************************************************
 * Dsc1b3 :: dfe_vga_ctrl2
 ***************************************************************************/
/* Dsc1b3 :: dfe_vga_ctrl2 :: reserved_for_eco0 [15:14] */
#define DSC1B3_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_MASK                0xc000
#define DSC1B3_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B3_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_BITS                2
#define DSC1B3_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_SHIFT               14

/* Dsc1b3 :: dfe_vga_ctrl2 :: trnsum_otap_en [13:07] */
#define DSC1B3_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_MASK                   0x3f80
#define DSC1B3_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_ALIGN                  0
#define DSC1B3_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_BITS                   7
#define DSC1B3_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_SHIFT                  7

/* Dsc1b3 :: dfe_vga_ctrl2 :: trnsum_etap_en [06:00] */
#define DSC1B3_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_MASK                   0x007f
#define DSC1B3_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_ALIGN                  0
#define DSC1B3_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_BITS                   7
#define DSC1B3_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_SHIFT                  0


/****************************************************************************
 * Dsc1b3 :: dfe_vga_ctrl3
 ***************************************************************************/
/* Dsc1b3 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:14] */
#define DSC1B3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK                0xc000
#define DSC1B3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS                2
#define DSC1B3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT               14

/* Dsc1b3 :: dfe_vga_ctrl3 :: trnsum_otap_sign [13:07] */
#define DSC1B3_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_MASK                 0x3f80
#define DSC1B3_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_ALIGN                0
#define DSC1B3_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_BITS                 7
#define DSC1B3_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_SHIFT                7

/* Dsc1b3 :: dfe_vga_ctrl3 :: trnsum_etap_sign [06:00] */
#define DSC1B3_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_MASK                 0x007f
#define DSC1B3_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_ALIGN                0
#define DSC1B3_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_BITS                 7
#define DSC1B3_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_SHIFT                0


/****************************************************************************
 * Dsc1b3 :: dfe_vga_ctrl4
 ***************************************************************************/
/* Dsc1b3 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */
#define DSC1B3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK                0xfc00
#define DSC1B3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS                6
#define DSC1B3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT               10

/* Dsc1b3 :: dfe_vga_ctrl4 :: vga_cor_sel_e [09:05] */
#define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_E_MASK                    0x03e0
#define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_E_ALIGN                   0
#define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_E_BITS                    5
#define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_E_SHIFT                   5

/* Dsc1b3 :: dfe_vga_ctrl4 :: vga_cor_sel_o [04:00] */
#define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_O_MASK                    0x001f
#define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_O_ALIGN                   0
#define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_O_BITS                    5
#define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_O_SHIFT                   0


/****************************************************************************
 * Dsc1b3 :: dfe_vga_ctrl5
 ***************************************************************************/
/* Dsc1b3 :: dfe_vga_ctrl5 :: reserved_for_eco0 [15:10] */
#define DSC1B3_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_MASK                0xfc00
#define DSC1B3_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B3_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_BITS                6
#define DSC1B3_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_SHIFT               10

/* Dsc1b3 :: dfe_vga_ctrl5 :: dfe_cor_sel_e [09:05] */
#define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_E_MASK                    0x03e0
#define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_E_ALIGN                   0
#define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_E_BITS                    5
#define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_E_SHIFT                   5

/* Dsc1b3 :: dfe_vga_ctrl5 :: dfe_cor_sel_o [04:00] */
#define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_O_MASK                    0x001f
#define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_O_ALIGN                   0
#define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_O_BITS                    5
#define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_O_SHIFT                   0


/****************************************************************************
 * Dsc1b3 :: dsc_ana_ctrl0
 ***************************************************************************/
/* Dsc1b3 :: dsc_ana_ctrl0 :: force_odd_ctrl [15:15] */
#define DSC1B3_DSC_ANA_CTRL0_FORCE_ODD_CTRL_MASK                   0x8000
#define DSC1B3_DSC_ANA_CTRL0_FORCE_ODD_CTRL_ALIGN                  0
#define DSC1B3_DSC_ANA_CTRL0_FORCE_ODD_CTRL_BITS                   1
#define DSC1B3_DSC_ANA_CTRL0_FORCE_ODD_CTRL_SHIFT                  15

/* Dsc1b3 :: dsc_ana_ctrl0 :: p1_odd_ctrl [14:10] */
#define DSC1B3_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK                      0x7c00
#define DSC1B3_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN                     0
#define DSC1B3_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS                      5
#define DSC1B3_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT                     10

/* Dsc1b3 :: dsc_ana_ctrl0 :: d_odd_ctrl [09:05] */
#define DSC1B3_DSC_ANA_CTRL0_D_ODD_CTRL_MASK                       0x03e0
#define DSC1B3_DSC_ANA_CTRL0_D_ODD_CTRL_ALIGN                      0
#define DSC1B3_DSC_ANA_CTRL0_D_ODD_CTRL_BITS                       5
#define DSC1B3_DSC_ANA_CTRL0_D_ODD_CTRL_SHIFT                      5

/* Dsc1b3 :: dsc_ana_ctrl0 :: m1_odd_ctrl [04:00] */
#define DSC1B3_DSC_ANA_CTRL0_M1_ODD_CTRL_MASK                      0x001f
#define DSC1B3_DSC_ANA_CTRL0_M1_ODD_CTRL_ALIGN                     0
#define DSC1B3_DSC_ANA_CTRL0_M1_ODD_CTRL_BITS                      5
#define DSC1B3_DSC_ANA_CTRL0_M1_ODD_CTRL_SHIFT                     0


/****************************************************************************
 * Dsc1b3 :: dsc_ana_ctrl1
 ***************************************************************************/
/* Dsc1b3 :: dsc_ana_ctrl1 :: force_evn_ctrl [15:15] */
#define DSC1B3_DSC_ANA_CTRL1_FORCE_EVN_CTRL_MASK                   0x8000
#define DSC1B3_DSC_ANA_CTRL1_FORCE_EVN_CTRL_ALIGN                  0
#define DSC1B3_DSC_ANA_CTRL1_FORCE_EVN_CTRL_BITS                   1
#define DSC1B3_DSC_ANA_CTRL1_FORCE_EVN_CTRL_SHIFT                  15

/* Dsc1b3 :: dsc_ana_ctrl1 :: p1_evn_ctrl [14:10] */
#define DSC1B3_DSC_ANA_CTRL1_P1_EVN_CTRL_MASK                      0x7c00
#define DSC1B3_DSC_ANA_CTRL1_P1_EVN_CTRL_ALIGN                     0
#define DSC1B3_DSC_ANA_CTRL1_P1_EVN_CTRL_BITS                      5
#define DSC1B3_DSC_ANA_CTRL1_P1_EVN_CTRL_SHIFT                     10

/* Dsc1b3 :: dsc_ana_ctrl1 :: d_evn_ctrl [09:05] */
#define DSC1B3_DSC_ANA_CTRL1_D_EVN_CTRL_MASK                       0x03e0
#define DSC1B3_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN                      0
#define DSC1B3_DSC_ANA_CTRL1_D_EVN_CTRL_BITS                       5
#define DSC1B3_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT                      5

/* Dsc1b3 :: dsc_ana_ctrl1 :: m1_evn_ctrl [04:00] */
#define DSC1B3_DSC_ANA_CTRL1_M1_EVN_CTRL_MASK                      0x001f
#define DSC1B3_DSC_ANA_CTRL1_M1_EVN_CTRL_ALIGN                     0
#define DSC1B3_DSC_ANA_CTRL1_M1_EVN_CTRL_BITS                      5
#define DSC1B3_DSC_ANA_CTRL1_M1_EVN_CTRL_SHIFT                     0


/****************************************************************************
 * Dsc1b3 :: dsc_ana_ctrl2
 ***************************************************************************/
/* Dsc1b3 :: dsc_ana_ctrl2 :: br_offset_pd [15:15] */
#define DSC1B3_DSC_ANA_CTRL2_BR_OFFSET_PD_MASK                     0x8000
#define DSC1B3_DSC_ANA_CTRL2_BR_OFFSET_PD_ALIGN                    0
#define DSC1B3_DSC_ANA_CTRL2_BR_OFFSET_PD_BITS                     1
#define DSC1B3_DSC_ANA_CTRL2_BR_OFFSET_PD_SHIFT                    15

/* Dsc1b3 :: dsc_ana_ctrl2 :: br_en_hgain [14:14] */
#define DSC1B3_DSC_ANA_CTRL2_BR_EN_HGAIN_MASK                      0x4000
#define DSC1B3_DSC_ANA_CTRL2_BR_EN_HGAIN_ALIGN                     0
#define DSC1B3_DSC_ANA_CTRL2_BR_EN_HGAIN_BITS                      1
#define DSC1B3_DSC_ANA_CTRL2_BR_EN_HGAIN_SHIFT                     14

/* Dsc1b3 :: dsc_ana_ctrl2 :: br_en_dfe_clk [13:13] */
#define DSC1B3_DSC_ANA_CTRL2_BR_EN_DFE_CLK_MASK                    0x2000
#define DSC1B3_DSC_ANA_CTRL2_BR_EN_DFE_CLK_ALIGN                   0
#define DSC1B3_DSC_ANA_CTRL2_BR_EN_DFE_CLK_BITS                    1
#define DSC1B3_DSC_ANA_CTRL2_BR_EN_DFE_CLK_SHIFT                   13

/* Dsc1b3 :: dsc_ana_ctrl2 :: br_pd_ch_p1 [12:12] */
#define DSC1B3_DSC_ANA_CTRL2_BR_PD_CH_P1_MASK                      0x1000
#define DSC1B3_DSC_ANA_CTRL2_BR_PD_CH_P1_ALIGN                     0
#define DSC1B3_DSC_ANA_CTRL2_BR_PD_CH_P1_BITS                      1
#define DSC1B3_DSC_ANA_CTRL2_BR_PD_CH_P1_SHIFT                     12

/* Dsc1b3 :: dsc_ana_ctrl2 :: osr_offset_pd [11:11] */
#define DSC1B3_DSC_ANA_CTRL2_OSR_OFFSET_PD_MASK                    0x0800
#define DSC1B3_DSC_ANA_CTRL2_OSR_OFFSET_PD_ALIGN                   0
#define DSC1B3_DSC_ANA_CTRL2_OSR_OFFSET_PD_BITS                    1
#define DSC1B3_DSC_ANA_CTRL2_OSR_OFFSET_PD_SHIFT                   11

/* Dsc1b3 :: dsc_ana_ctrl2 :: osr_en_hgain [10:10] */
#define DSC1B3_DSC_ANA_CTRL2_OSR_EN_HGAIN_MASK                     0x0400
#define DSC1B3_DSC_ANA_CTRL2_OSR_EN_HGAIN_ALIGN                    0
#define DSC1B3_DSC_ANA_CTRL2_OSR_EN_HGAIN_BITS                     1
#define DSC1B3_DSC_ANA_CTRL2_OSR_EN_HGAIN_SHIFT                    10

/* Dsc1b3 :: dsc_ana_ctrl2 :: osr_en_dfe_clk [09:09] */
#define DSC1B3_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_MASK                   0x0200
#define DSC1B3_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_ALIGN                  0
#define DSC1B3_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_BITS                   1
#define DSC1B3_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_SHIFT                  9

/* Dsc1b3 :: dsc_ana_ctrl2 :: osr_pd_ch_p1 [08:08] */
#define DSC1B3_DSC_ANA_CTRL2_OSR_PD_CH_P1_MASK                     0x0100
#define DSC1B3_DSC_ANA_CTRL2_OSR_PD_CH_P1_ALIGN                    0
#define DSC1B3_DSC_ANA_CTRL2_OSR_PD_CH_P1_BITS                     1
#define DSC1B3_DSC_ANA_CTRL2_OSR_PD_CH_P1_SHIFT                    8

/* Dsc1b3 :: dsc_ana_ctrl2 :: force_rx_m1_thresh_zero [07:07] */
#define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_MASK          0x0080
#define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_ALIGN         0
#define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_BITS          1
#define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_SHIFT         7

/* Dsc1b3 :: dsc_ana_ctrl2 :: rx_m1_thresh_zero [06:06] */
#define DSC1B3_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_MASK                0x0040
#define DSC1B3_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_ALIGN               0
#define DSC1B3_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_BITS                1
#define DSC1B3_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_SHIFT               6

/* Dsc1b3 :: dsc_ana_ctrl2 :: rx_thresh_sel [05:04] */
#define DSC1B3_DSC_ANA_CTRL2_RX_THRESH_SEL_MASK                    0x0030
#define DSC1B3_DSC_ANA_CTRL2_RX_THRESH_SEL_ALIGN                   0
#define DSC1B3_DSC_ANA_CTRL2_RX_THRESH_SEL_BITS                    2
#define DSC1B3_DSC_ANA_CTRL2_RX_THRESH_SEL_SHIFT                   4

/* Dsc1b3 :: dsc_ana_ctrl2 :: force_rx_pf_ctrl [03:03] */
#define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_MASK                 0x0008
#define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_ALIGN                0
#define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_BITS                 1
#define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_SHIFT                3

/* Dsc1b3 :: dsc_ana_ctrl2 :: rx_pf_ctrl [02:00] */
#define DSC1B3_DSC_ANA_CTRL2_RX_PF_CTRL_MASK                       0x0007
#define DSC1B3_DSC_ANA_CTRL2_RX_PF_CTRL_ALIGN                      0
#define DSC1B3_DSC_ANA_CTRL2_RX_PF_CTRL_BITS                       3
#define DSC1B3_DSC_ANA_CTRL2_RX_PF_CTRL_SHIFT                      0


/****************************************************************************
 * Dsc1b3 :: dsc_100fx_ctrl
 ***************************************************************************/
/* Dsc1b3 :: dsc_100fx_ctrl :: reserved_for_eco0 [15:11] */
#define DSC1B3_DSC_100FX_CTRL_RESERVED_FOR_ECO0_MASK               0xf800
#define DSC1B3_DSC_100FX_CTRL_RESERVED_FOR_ECO0_ALIGN              0
#define DSC1B3_DSC_100FX_CTRL_RESERVED_FOR_ECO0_BITS               5
#define DSC1B3_DSC_100FX_CTRL_RESERVED_FOR_ECO0_SHIFT              11

/* Dsc1b3 :: dsc_100fx_ctrl :: phase_sat_ctrl_100fx [10:09] */
#define DSC1B3_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_MASK            0x0600
#define DSC1B3_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_ALIGN           0
#define DSC1B3_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_BITS            2
#define DSC1B3_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_SHIFT           9

/* Dsc1b3 :: dsc_100fx_ctrl :: pi_phase_step_mult_100fx [08:08] */
#define DSC1B3_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_MASK        0x0100
#define DSC1B3_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_ALIGN       0
#define DSC1B3_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_BITS        1
#define DSC1B3_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_SHIFT       8

/* Dsc1b3 :: dsc_100fx_ctrl :: cdros_bwsel_integ_100fx [07:04] */
#define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_MASK         0x00f0
#define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_ALIGN        0
#define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_BITS         4
#define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_SHIFT        4

/* Dsc1b3 :: dsc_100fx_ctrl :: cdros_bwsel_prop_100fx [03:00] */
#define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_MASK          0x000f
#define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_ALIGN         0
#define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_BITS          4
#define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_SHIFT         0


/****************************************************************************
 * Dsc1b3 :: dsc_ana_ctrl3
 ***************************************************************************/
/* Dsc1b3 :: dsc_ana_ctrl3 :: reserved_for_eco0 [15:06] */
#define DSC1B3_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_MASK                0xffc0
#define DSC1B3_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1B3_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_BITS                10
#define DSC1B3_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_SHIFT               6

/* Dsc1b3 :: dsc_ana_ctrl3 :: force_p1_evn_ctrl [05:05] */
#define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_MASK                0x0020
#define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_ALIGN               0
#define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_BITS                1
#define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_SHIFT               5

/* Dsc1b3 :: dsc_ana_ctrl3 :: force_d_evn_ctrl [04:04] */
#define DSC1B3_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_MASK                 0x0010
#define DSC1B3_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_ALIGN                0
#define DSC1B3_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_BITS                 1
#define DSC1B3_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_SHIFT                4

/* Dsc1b3 :: dsc_ana_ctrl3 :: force_m1_evn_ctrl [03:03] */
#define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_MASK                0x0008
#define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_ALIGN               0
#define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_BITS                1
#define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_SHIFT               3

/* Dsc1b3 :: dsc_ana_ctrl3 :: force_p1_odd_ctrl [02:02] */
#define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_MASK                0x0004
#define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_ALIGN               0
#define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_BITS                1
#define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_SHIFT               2

/* Dsc1b3 :: dsc_ana_ctrl3 :: force_d_odd_ctrl [01:01] */
#define DSC1B3_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_MASK                 0x0002
#define DSC1B3_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_ALIGN                0
#define DSC1B3_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_BITS                 1
#define DSC1B3_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_SHIFT                1

/* Dsc1b3 :: dsc_ana_ctrl3 :: force_m1_odd_ctrl [00:00] */
#define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_MASK                0x0001
#define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_ALIGN               0
#define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_BITS                1
#define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_SHIFT               0


/****************************************************************************
 * Hypercore_USER_Dsc1bB
 ***************************************************************************/
/****************************************************************************
 * Dsc1bB :: cdr_ctrl0
 ***************************************************************************/
/* Dsc1bB :: cdr_ctrl0 :: reserved_for_eco0 [15:13] */
#define DSC1BB_CDR_CTRL0_RESERVED_FOR_ECO0_MASK                    0xe000
#define DSC1BB_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC1BB_CDR_CTRL0_RESERVED_FOR_ECO0_BITS                    3
#define DSC1BB_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT                   13

/* Dsc1bB :: cdr_ctrl0 :: cdrbr_polarity [12:12] */
#define DSC1BB_CDR_CTRL0_CDRBR_POLARITY_MASK                       0x1000
#define DSC1BB_CDR_CTRL0_CDRBR_POLARITY_ALIGN                      0
#define DSC1BB_CDR_CTRL0_CDRBR_POLARITY_BITS                       1
#define DSC1BB_CDR_CTRL0_CDRBR_POLARITY_SHIFT                      12

/* Dsc1bB :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */
#define DSC1BB_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK                   0x0800
#define DSC1BB_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN                  0
#define DSC1BB_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS                   1
#define DSC1BB_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT                  11

/* Dsc1bB :: cdr_ctrl0 :: cdros_rising_edge [10:10] */
#define DSC1BB_CDR_CTRL0_CDROS_RISING_EDGE_MASK                    0x0400
#define DSC1BB_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN                   0
#define DSC1BB_CDR_CTRL0_CDROS_RISING_EDGE_BITS                    1
#define DSC1BB_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT                   10

/* Dsc1bB :: cdr_ctrl0 :: cdros_falling_edge [09:09] */
#define DSC1BB_CDR_CTRL0_CDROS_FALLING_EDGE_MASK                   0x0200
#define DSC1BB_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN                  0
#define DSC1BB_CDR_CTRL0_CDROS_FALLING_EDGE_BITS                   1
#define DSC1BB_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT                  9

/* Dsc1bB :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */
#define DSC1BB_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK                 0x0180
#define DSC1BB_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN                0
#define DSC1BB_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS                 2
#define DSC1BB_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT                7

/* Dsc1bB :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */
#define DSC1BB_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK                  0x0040
#define DSC1BB_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN                 0
#define DSC1BB_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS                  1
#define DSC1BB_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT                 6

/* Dsc1bB :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */
#define DSC1BB_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK                  0x0020
#define DSC1BB_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN                 0
#define DSC1BB_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS                  1
#define DSC1BB_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT                 5

/* Dsc1bB :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */
#define DSC1BB_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK                    0x0010
#define DSC1BB_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN                   0
#define DSC1BB_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS                    1
#define DSC1BB_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT                   4

/* Dsc1bB :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */
#define DSC1BB_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK                    0x0008
#define DSC1BB_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN                   0
#define DSC1BB_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS                    1
#define DSC1BB_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT                   3

/* Dsc1bB :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */
#define DSC1BB_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK                      0x0004
#define DSC1BB_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN                     0
#define DSC1BB_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS                      1
#define DSC1BB_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT                     2

/* Dsc1bB :: cdr_ctrl0 :: cdr_freq_en [01:01] */
#define DSC1BB_CDR_CTRL0_CDR_FREQ_EN_MASK                          0x0002
#define DSC1BB_CDR_CTRL0_CDR_FREQ_EN_ALIGN                         0
#define DSC1BB_CDR_CTRL0_CDR_FREQ_EN_BITS                          1
#define DSC1BB_CDR_CTRL0_CDR_FREQ_EN_SHIFT                         1

/* Dsc1bB :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */
#define DSC1BB_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK                 0x0001
#define DSC1BB_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN                0
#define DSC1BB_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS                 1
#define DSC1BB_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT                0


/****************************************************************************
 * Dsc1bB :: cdr_ctrl1
 ***************************************************************************/
/* Dsc1bB :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */
#define DSC1BB_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK                0xffff
#define DSC1BB_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN               0
#define DSC1BB_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS                16
#define DSC1BB_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT               0


/****************************************************************************
 * Dsc1bB :: cdr_ctrl2
 ***************************************************************************/
/* Dsc1bB :: cdr_ctrl2 :: reserved_for_eco0 [15:06] */
#define DSC1BB_CDR_CTRL2_RESERVED_FOR_ECO0_MASK                    0xffc0
#define DSC1BB_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC1BB_CDR_CTRL2_RESERVED_FOR_ECO0_BITS                    10
#define DSC1BB_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT                   6

/* Dsc1bB :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */
#define DSC1BB_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK               0x003f
#define DSC1BB_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN              0
#define DSC1BB_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS               6
#define DSC1BB_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT              0


/****************************************************************************
 * Dsc1bB :: pi_ctrl0
 ***************************************************************************/
/* Dsc1bB :: pi_ctrl0 :: pi_cw_rst [15:15] */
#define DSC1BB_PI_CTRL0_PI_CW_RST_MASK                             0x8000
#define DSC1BB_PI_CTRL0_PI_CW_RST_ALIGN                            0
#define DSC1BB_PI_CTRL0_PI_CW_RST_BITS                             1
#define DSC1BB_PI_CTRL0_PI_CW_RST_SHIFT                            15

/* Dsc1bB :: pi_ctrl0 :: intrp_tmuxSelect [14:12] */
#define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_MASK                      0x7000
#define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_ALIGN                     0
#define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_BITS                      3
#define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_SHIFT                     12
#define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_lsb             0
#define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_msb             1
#define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_lsb           2
#define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_msb           3
#define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_lsb            4
#define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_msb            5
#define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_lsb          6
#define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_msb          7

/* Dsc1bB :: pi_ctrl0 :: reserved_for_eco0 [11:11] */
#define DSC1BB_PI_CTRL0_RESERVED_FOR_ECO0_MASK                     0x0800
#define DSC1BB_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC1BB_PI_CTRL0_RESERVED_FOR_ECO0_BITS                     1
#define DSC1BB_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT                    11

/* Dsc1bB :: pi_ctrl0 :: pi_phase_invert [10:10] */
#define DSC1BB_PI_CTRL0_PI_PHASE_INVERT_MASK                       0x0400
#define DSC1BB_PI_CTRL0_PI_PHASE_INVERT_ALIGN                      0
#define DSC1BB_PI_CTRL0_PI_PHASE_INVERT_BITS                       1
#define DSC1BB_PI_CTRL0_PI_PHASE_INVERT_SHIFT                      10

/* Dsc1bB :: pi_ctrl0 :: pi_dual_phase_override [09:09] */
#define DSC1BB_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK                0x0200
#define DSC1BB_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN               0
#define DSC1BB_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS                1
#define DSC1BB_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT               9

/* Dsc1bB :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */
#define DSC1BB_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK              0x0100
#define DSC1BB_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN             0
#define DSC1BB_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS              1
#define DSC1BB_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT             8

/* Dsc1bB :: pi_ctrl0 :: pi_phase_dec [07:07] */
#define DSC1BB_PI_CTRL0_PI_PHASE_DEC_MASK                          0x0080
#define DSC1BB_PI_CTRL0_PI_PHASE_DEC_ALIGN                         0
#define DSC1BB_PI_CTRL0_PI_PHASE_DEC_BITS                          1
#define DSC1BB_PI_CTRL0_PI_PHASE_DEC_SHIFT                         7

/* Dsc1bB :: pi_ctrl0 :: pi_phase_inc [06:06] */
#define DSC1BB_PI_CTRL0_PI_PHASE_INC_MASK                          0x0040
#define DSC1BB_PI_CTRL0_PI_PHASE_INC_ALIGN                         0
#define DSC1BB_PI_CTRL0_PI_PHASE_INC_BITS                          1
#define DSC1BB_PI_CTRL0_PI_PHASE_INC_SHIFT                         6

/* Dsc1bB :: pi_ctrl0 :: pi_phase_strobe [05:05] */
#define DSC1BB_PI_CTRL0_PI_PHASE_STROBE_MASK                       0x0020
#define DSC1BB_PI_CTRL0_PI_PHASE_STROBE_ALIGN                      0
#define DSC1BB_PI_CTRL0_PI_PHASE_STROBE_BITS                       1
#define DSC1BB_PI_CTRL0_PI_PHASE_STROBE_SHIFT                      5

/* Dsc1bB :: pi_ctrl0 :: pi_phase_delta [04:01] */
#define DSC1BB_PI_CTRL0_PI_PHASE_DELTA_MASK                        0x001e
#define DSC1BB_PI_CTRL0_PI_PHASE_DELTA_ALIGN                       0
#define DSC1BB_PI_CTRL0_PI_PHASE_DELTA_BITS                        4
#define DSC1BB_PI_CTRL0_PI_PHASE_DELTA_SHIFT                       1

/* Dsc1bB :: pi_ctrl0 :: pi_phase_step_mult [00:00] */
#define DSC1BB_PI_CTRL0_PI_PHASE_STEP_MULT_MASK                    0x0001
#define DSC1BB_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN                   0
#define DSC1BB_PI_CTRL0_PI_PHASE_STEP_MULT_BITS                    1
#define DSC1BB_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT                   0


/****************************************************************************
 * Dsc1bB :: dfe_vga_ctrl0
 ***************************************************************************/
/* Dsc1bB :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:08] */
#define DSC1BB_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK                0xff00
#define DSC1BB_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1BB_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS                8
#define DSC1BB_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT               8

/* Dsc1bB :: dfe_vga_ctrl0 :: vga_timer_ctrl [07:06] */
#define DSC1BB_DFE_VGA_CTRL0_VGA_TIMER_CTRL_MASK                   0x00c0
#define DSC1BB_DFE_VGA_CTRL0_VGA_TIMER_CTRL_ALIGN                  0
#define DSC1BB_DFE_VGA_CTRL0_VGA_TIMER_CTRL_BITS                   2
#define DSC1BB_DFE_VGA_CTRL0_VGA_TIMER_CTRL_SHIFT                  6

/* Dsc1bB :: dfe_vga_ctrl0 :: vga_polarity [05:05] */
#define DSC1BB_DFE_VGA_CTRL0_VGA_POLARITY_MASK                     0x0020
#define DSC1BB_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN                    0
#define DSC1BB_DFE_VGA_CTRL0_VGA_POLARITY_BITS                     1
#define DSC1BB_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT                    5

/* Dsc1bB :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */
#define DSC1BB_DFE_VGA_CTRL0_DFE_POLARITY_MASK                     0x0010
#define DSC1BB_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN                    0
#define DSC1BB_DFE_VGA_CTRL0_DFE_POLARITY_BITS                     1
#define DSC1BB_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT                    4

/* Dsc1bB :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */
#define DSC1BB_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK                 0x0008
#define DSC1BB_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN                0
#define DSC1BB_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS                 1
#define DSC1BB_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT                3

/* Dsc1bB :: dfe_vga_ctrl0 :: sum_m1err [02:02] */
#define DSC1BB_DFE_VGA_CTRL0_SUM_M1ERR_MASK                        0x0004
#define DSC1BB_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN                       0
#define DSC1BB_DFE_VGA_CTRL0_SUM_M1ERR_BITS                        1
#define DSC1BB_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT                       2

/* Dsc1bB :: dfe_vga_ctrl0 :: trnsum_en [01:01] */
#define DSC1BB_DFE_VGA_CTRL0_TRNSUM_EN_MASK                        0x0002
#define DSC1BB_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN                       0
#define DSC1BB_DFE_VGA_CTRL0_TRNSUM_EN_BITS                        1
#define DSC1BB_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT                       1

/* Dsc1bB :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */
#define DSC1BB_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK                    0x0001
#define DSC1BB_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN                   0
#define DSC1BB_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS                    1
#define DSC1BB_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT                   0


/****************************************************************************
 * Dsc1bB :: dfe_vga_ctrl1
 ***************************************************************************/
/* Dsc1bB :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:13] */
#define DSC1BB_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK                0xe000
#define DSC1BB_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1BB_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS                3
#define DSC1BB_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT               13

/* Dsc1bB :: dfe_vga_ctrl1 :: dfe_write_val [12:07] */
#define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_VAL_MASK                    0x1f80
#define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_VAL_ALIGN                   0
#define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_VAL_BITS                    6
#define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_VAL_SHIFT                   7

/* Dsc1bB :: dfe_vga_ctrl1 :: dfe_write_en [06:06] */
#define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_EN_MASK                     0x0040
#define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_EN_ALIGN                    0
#define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_EN_BITS                     1
#define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_EN_SHIFT                    6

/* Dsc1bB :: dfe_vga_ctrl1 :: vga_write_val [05:01] */
#define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_VAL_MASK                    0x003e
#define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_VAL_ALIGN                   0
#define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_VAL_BITS                    5
#define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_VAL_SHIFT                   1

/* Dsc1bB :: dfe_vga_ctrl1 :: vga_write_en [00:00] */
#define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_EN_MASK                     0x0001
#define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_EN_ALIGN                    0
#define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_EN_BITS                     1
#define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_EN_SHIFT                    0


/****************************************************************************
 * Dsc1bB :: dfe_vga_ctrl2
 ***************************************************************************/
/* Dsc1bB :: dfe_vga_ctrl2 :: reserved_for_eco0 [15:14] */
#define DSC1BB_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_MASK                0xc000
#define DSC1BB_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1BB_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_BITS                2
#define DSC1BB_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_SHIFT               14

/* Dsc1bB :: dfe_vga_ctrl2 :: trnsum_otap_en [13:07] */
#define DSC1BB_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_MASK                   0x3f80
#define DSC1BB_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_ALIGN                  0
#define DSC1BB_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_BITS                   7
#define DSC1BB_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_SHIFT                  7

/* Dsc1bB :: dfe_vga_ctrl2 :: trnsum_etap_en [06:00] */
#define DSC1BB_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_MASK                   0x007f
#define DSC1BB_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_ALIGN                  0
#define DSC1BB_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_BITS                   7
#define DSC1BB_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_SHIFT                  0


/****************************************************************************
 * Dsc1bB :: dfe_vga_ctrl3
 ***************************************************************************/
/* Dsc1bB :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:14] */
#define DSC1BB_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK                0xc000
#define DSC1BB_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1BB_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS                2
#define DSC1BB_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT               14

/* Dsc1bB :: dfe_vga_ctrl3 :: trnsum_otap_sign [13:07] */
#define DSC1BB_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_MASK                 0x3f80
#define DSC1BB_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_ALIGN                0
#define DSC1BB_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_BITS                 7
#define DSC1BB_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_SHIFT                7

/* Dsc1bB :: dfe_vga_ctrl3 :: trnsum_etap_sign [06:00] */
#define DSC1BB_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_MASK                 0x007f
#define DSC1BB_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_ALIGN                0
#define DSC1BB_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_BITS                 7
#define DSC1BB_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_SHIFT                0


/****************************************************************************
 * Dsc1bB :: dfe_vga_ctrl4
 ***************************************************************************/
/* Dsc1bB :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */
#define DSC1BB_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK                0xfc00
#define DSC1BB_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1BB_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS                6
#define DSC1BB_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT               10

/* Dsc1bB :: dfe_vga_ctrl4 :: vga_cor_sel_e [09:05] */
#define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_E_MASK                    0x03e0
#define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_E_ALIGN                   0
#define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_E_BITS                    5
#define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_E_SHIFT                   5

/* Dsc1bB :: dfe_vga_ctrl4 :: vga_cor_sel_o [04:00] */
#define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_O_MASK                    0x001f
#define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_O_ALIGN                   0
#define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_O_BITS                    5
#define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_O_SHIFT                   0


/****************************************************************************
 * Dsc1bB :: dfe_vga_ctrl5
 ***************************************************************************/
/* Dsc1bB :: dfe_vga_ctrl5 :: reserved_for_eco0 [15:10] */
#define DSC1BB_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_MASK                0xfc00
#define DSC1BB_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1BB_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_BITS                6
#define DSC1BB_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_SHIFT               10

/* Dsc1bB :: dfe_vga_ctrl5 :: dfe_cor_sel_e [09:05] */
#define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_E_MASK                    0x03e0
#define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_E_ALIGN                   0
#define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_E_BITS                    5
#define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_E_SHIFT                   5

/* Dsc1bB :: dfe_vga_ctrl5 :: dfe_cor_sel_o [04:00] */
#define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_O_MASK                    0x001f
#define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_O_ALIGN                   0
#define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_O_BITS                    5
#define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_O_SHIFT                   0


/****************************************************************************
 * Dsc1bB :: dsc_ana_ctrl0
 ***************************************************************************/
/* Dsc1bB :: dsc_ana_ctrl0 :: force_odd_ctrl [15:15] */
#define DSC1BB_DSC_ANA_CTRL0_FORCE_ODD_CTRL_MASK                   0x8000
#define DSC1BB_DSC_ANA_CTRL0_FORCE_ODD_CTRL_ALIGN                  0
#define DSC1BB_DSC_ANA_CTRL0_FORCE_ODD_CTRL_BITS                   1
#define DSC1BB_DSC_ANA_CTRL0_FORCE_ODD_CTRL_SHIFT                  15

/* Dsc1bB :: dsc_ana_ctrl0 :: p1_odd_ctrl [14:10] */
#define DSC1BB_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK                      0x7c00
#define DSC1BB_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN                     0
#define DSC1BB_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS                      5
#define DSC1BB_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT                     10

/* Dsc1bB :: dsc_ana_ctrl0 :: d_odd_ctrl [09:05] */
#define DSC1BB_DSC_ANA_CTRL0_D_ODD_CTRL_MASK                       0x03e0
#define DSC1BB_DSC_ANA_CTRL0_D_ODD_CTRL_ALIGN                      0
#define DSC1BB_DSC_ANA_CTRL0_D_ODD_CTRL_BITS                       5
#define DSC1BB_DSC_ANA_CTRL0_D_ODD_CTRL_SHIFT                      5

/* Dsc1bB :: dsc_ana_ctrl0 :: m1_odd_ctrl [04:00] */
#define DSC1BB_DSC_ANA_CTRL0_M1_ODD_CTRL_MASK                      0x001f
#define DSC1BB_DSC_ANA_CTRL0_M1_ODD_CTRL_ALIGN                     0
#define DSC1BB_DSC_ANA_CTRL0_M1_ODD_CTRL_BITS                      5
#define DSC1BB_DSC_ANA_CTRL0_M1_ODD_CTRL_SHIFT                     0


/****************************************************************************
 * Dsc1bB :: dsc_ana_ctrl1
 ***************************************************************************/
/* Dsc1bB :: dsc_ana_ctrl1 :: force_evn_ctrl [15:15] */
#define DSC1BB_DSC_ANA_CTRL1_FORCE_EVN_CTRL_MASK                   0x8000
#define DSC1BB_DSC_ANA_CTRL1_FORCE_EVN_CTRL_ALIGN                  0
#define DSC1BB_DSC_ANA_CTRL1_FORCE_EVN_CTRL_BITS                   1
#define DSC1BB_DSC_ANA_CTRL1_FORCE_EVN_CTRL_SHIFT                  15

/* Dsc1bB :: dsc_ana_ctrl1 :: p1_evn_ctrl [14:10] */
#define DSC1BB_DSC_ANA_CTRL1_P1_EVN_CTRL_MASK                      0x7c00
#define DSC1BB_DSC_ANA_CTRL1_P1_EVN_CTRL_ALIGN                     0
#define DSC1BB_DSC_ANA_CTRL1_P1_EVN_CTRL_BITS                      5
#define DSC1BB_DSC_ANA_CTRL1_P1_EVN_CTRL_SHIFT                     10

/* Dsc1bB :: dsc_ana_ctrl1 :: d_evn_ctrl [09:05] */
#define DSC1BB_DSC_ANA_CTRL1_D_EVN_CTRL_MASK                       0x03e0
#define DSC1BB_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN                      0
#define DSC1BB_DSC_ANA_CTRL1_D_EVN_CTRL_BITS                       5
#define DSC1BB_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT                      5

/* Dsc1bB :: dsc_ana_ctrl1 :: m1_evn_ctrl [04:00] */
#define DSC1BB_DSC_ANA_CTRL1_M1_EVN_CTRL_MASK                      0x001f
#define DSC1BB_DSC_ANA_CTRL1_M1_EVN_CTRL_ALIGN                     0
#define DSC1BB_DSC_ANA_CTRL1_M1_EVN_CTRL_BITS                      5
#define DSC1BB_DSC_ANA_CTRL1_M1_EVN_CTRL_SHIFT                     0


/****************************************************************************
 * Dsc1bB :: dsc_ana_ctrl2
 ***************************************************************************/
/* Dsc1bB :: dsc_ana_ctrl2 :: br_offset_pd [15:15] */
#define DSC1BB_DSC_ANA_CTRL2_BR_OFFSET_PD_MASK                     0x8000
#define DSC1BB_DSC_ANA_CTRL2_BR_OFFSET_PD_ALIGN                    0
#define DSC1BB_DSC_ANA_CTRL2_BR_OFFSET_PD_BITS                     1
#define DSC1BB_DSC_ANA_CTRL2_BR_OFFSET_PD_SHIFT                    15

/* Dsc1bB :: dsc_ana_ctrl2 :: br_en_hgain [14:14] */
#define DSC1BB_DSC_ANA_CTRL2_BR_EN_HGAIN_MASK                      0x4000
#define DSC1BB_DSC_ANA_CTRL2_BR_EN_HGAIN_ALIGN                     0
#define DSC1BB_DSC_ANA_CTRL2_BR_EN_HGAIN_BITS                      1
#define DSC1BB_DSC_ANA_CTRL2_BR_EN_HGAIN_SHIFT                     14

/* Dsc1bB :: dsc_ana_ctrl2 :: br_en_dfe_clk [13:13] */
#define DSC1BB_DSC_ANA_CTRL2_BR_EN_DFE_CLK_MASK                    0x2000
#define DSC1BB_DSC_ANA_CTRL2_BR_EN_DFE_CLK_ALIGN                   0
#define DSC1BB_DSC_ANA_CTRL2_BR_EN_DFE_CLK_BITS                    1
#define DSC1BB_DSC_ANA_CTRL2_BR_EN_DFE_CLK_SHIFT                   13

/* Dsc1bB :: dsc_ana_ctrl2 :: br_pd_ch_p1 [12:12] */
#define DSC1BB_DSC_ANA_CTRL2_BR_PD_CH_P1_MASK                      0x1000
#define DSC1BB_DSC_ANA_CTRL2_BR_PD_CH_P1_ALIGN                     0
#define DSC1BB_DSC_ANA_CTRL2_BR_PD_CH_P1_BITS                      1
#define DSC1BB_DSC_ANA_CTRL2_BR_PD_CH_P1_SHIFT                     12

/* Dsc1bB :: dsc_ana_ctrl2 :: osr_offset_pd [11:11] */
#define DSC1BB_DSC_ANA_CTRL2_OSR_OFFSET_PD_MASK                    0x0800
#define DSC1BB_DSC_ANA_CTRL2_OSR_OFFSET_PD_ALIGN                   0
#define DSC1BB_DSC_ANA_CTRL2_OSR_OFFSET_PD_BITS                    1
#define DSC1BB_DSC_ANA_CTRL2_OSR_OFFSET_PD_SHIFT                   11

/* Dsc1bB :: dsc_ana_ctrl2 :: osr_en_hgain [10:10] */
#define DSC1BB_DSC_ANA_CTRL2_OSR_EN_HGAIN_MASK                     0x0400
#define DSC1BB_DSC_ANA_CTRL2_OSR_EN_HGAIN_ALIGN                    0
#define DSC1BB_DSC_ANA_CTRL2_OSR_EN_HGAIN_BITS                     1
#define DSC1BB_DSC_ANA_CTRL2_OSR_EN_HGAIN_SHIFT                    10

/* Dsc1bB :: dsc_ana_ctrl2 :: osr_en_dfe_clk [09:09] */
#define DSC1BB_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_MASK                   0x0200
#define DSC1BB_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_ALIGN                  0
#define DSC1BB_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_BITS                   1
#define DSC1BB_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_SHIFT                  9

/* Dsc1bB :: dsc_ana_ctrl2 :: osr_pd_ch_p1 [08:08] */
#define DSC1BB_DSC_ANA_CTRL2_OSR_PD_CH_P1_MASK                     0x0100
#define DSC1BB_DSC_ANA_CTRL2_OSR_PD_CH_P1_ALIGN                    0
#define DSC1BB_DSC_ANA_CTRL2_OSR_PD_CH_P1_BITS                     1
#define DSC1BB_DSC_ANA_CTRL2_OSR_PD_CH_P1_SHIFT                    8

/* Dsc1bB :: dsc_ana_ctrl2 :: force_rx_m1_thresh_zero [07:07] */
#define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_MASK          0x0080
#define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_ALIGN         0
#define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_BITS          1
#define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_SHIFT         7

/* Dsc1bB :: dsc_ana_ctrl2 :: rx_m1_thresh_zero [06:06] */
#define DSC1BB_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_MASK                0x0040
#define DSC1BB_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_ALIGN               0
#define DSC1BB_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_BITS                1
#define DSC1BB_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_SHIFT               6

/* Dsc1bB :: dsc_ana_ctrl2 :: rx_thresh_sel [05:04] */
#define DSC1BB_DSC_ANA_CTRL2_RX_THRESH_SEL_MASK                    0x0030
#define DSC1BB_DSC_ANA_CTRL2_RX_THRESH_SEL_ALIGN                   0
#define DSC1BB_DSC_ANA_CTRL2_RX_THRESH_SEL_BITS                    2
#define DSC1BB_DSC_ANA_CTRL2_RX_THRESH_SEL_SHIFT                   4

/* Dsc1bB :: dsc_ana_ctrl2 :: force_rx_pf_ctrl [03:03] */
#define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_MASK                 0x0008
#define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_ALIGN                0
#define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_BITS                 1
#define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_SHIFT                3

/* Dsc1bB :: dsc_ana_ctrl2 :: rx_pf_ctrl [02:00] */
#define DSC1BB_DSC_ANA_CTRL2_RX_PF_CTRL_MASK                       0x0007
#define DSC1BB_DSC_ANA_CTRL2_RX_PF_CTRL_ALIGN                      0
#define DSC1BB_DSC_ANA_CTRL2_RX_PF_CTRL_BITS                       3
#define DSC1BB_DSC_ANA_CTRL2_RX_PF_CTRL_SHIFT                      0


/****************************************************************************
 * Dsc1bB :: dsc_100fx_ctrl
 ***************************************************************************/
/* Dsc1bB :: dsc_100fx_ctrl :: reserved_for_eco0 [15:11] */
#define DSC1BB_DSC_100FX_CTRL_RESERVED_FOR_ECO0_MASK               0xf800
#define DSC1BB_DSC_100FX_CTRL_RESERVED_FOR_ECO0_ALIGN              0
#define DSC1BB_DSC_100FX_CTRL_RESERVED_FOR_ECO0_BITS               5
#define DSC1BB_DSC_100FX_CTRL_RESERVED_FOR_ECO0_SHIFT              11

/* Dsc1bB :: dsc_100fx_ctrl :: phase_sat_ctrl_100fx [10:09] */
#define DSC1BB_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_MASK            0x0600
#define DSC1BB_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_ALIGN           0
#define DSC1BB_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_BITS            2
#define DSC1BB_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_SHIFT           9

/* Dsc1bB :: dsc_100fx_ctrl :: pi_phase_step_mult_100fx [08:08] */
#define DSC1BB_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_MASK        0x0100
#define DSC1BB_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_ALIGN       0
#define DSC1BB_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_BITS        1
#define DSC1BB_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_SHIFT       8

/* Dsc1bB :: dsc_100fx_ctrl :: cdros_bwsel_integ_100fx [07:04] */
#define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_MASK         0x00f0
#define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_ALIGN        0
#define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_BITS         4
#define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_SHIFT        4

/* Dsc1bB :: dsc_100fx_ctrl :: cdros_bwsel_prop_100fx [03:00] */
#define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_MASK          0x000f
#define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_ALIGN         0
#define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_BITS          4
#define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_SHIFT         0


/****************************************************************************
 * Dsc1bB :: dsc_ana_ctrl3
 ***************************************************************************/
/* Dsc1bB :: dsc_ana_ctrl3 :: reserved_for_eco0 [15:06] */
#define DSC1BB_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_MASK                0xffc0
#define DSC1BB_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_ALIGN               0
#define DSC1BB_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_BITS                10
#define DSC1BB_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_SHIFT               6

/* Dsc1bB :: dsc_ana_ctrl3 :: force_p1_evn_ctrl [05:05] */
#define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_MASK                0x0020
#define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_ALIGN               0
#define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_BITS                1
#define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_SHIFT               5

/* Dsc1bB :: dsc_ana_ctrl3 :: force_d_evn_ctrl [04:04] */
#define DSC1BB_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_MASK                 0x0010
#define DSC1BB_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_ALIGN                0
#define DSC1BB_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_BITS                 1
#define DSC1BB_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_SHIFT                4

/* Dsc1bB :: dsc_ana_ctrl3 :: force_m1_evn_ctrl [03:03] */
#define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_MASK                0x0008
#define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_ALIGN               0
#define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_BITS                1
#define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_SHIFT               3

/* Dsc1bB :: dsc_ana_ctrl3 :: force_p1_odd_ctrl [02:02] */
#define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_MASK                0x0004
#define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_ALIGN               0
#define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_BITS                1
#define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_SHIFT               2

/* Dsc1bB :: dsc_ana_ctrl3 :: force_d_odd_ctrl [01:01] */
#define DSC1BB_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_MASK                 0x0002
#define DSC1BB_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_ALIGN                0
#define DSC1BB_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_BITS                 1
#define DSC1BB_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_SHIFT                1

/* Dsc1bB :: dsc_ana_ctrl3 :: force_m1_odd_ctrl [00:00] */
#define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_MASK                0x0001
#define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_ALIGN               0
#define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_BITS                1
#define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_SHIFT               0


/****************************************************************************
 * Hypercore_USER_Dsc2b0
 ***************************************************************************/
/****************************************************************************
 * Dsc2b0 :: sm_ctrl0
 ***************************************************************************/
/* Dsc2b0 :: sm_ctrl0 :: reserved_for_eco0 [15:15] */
#define DSC2B0_SM_CTRL0_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2B0_SM_CTRL0_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B0_SM_CTRL0_RESERVED_FOR_ECO0_BITS                     1
#define DSC2B0_SM_CTRL0_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2b0 :: sm_ctrl0 :: bypass_tx_postc_cal [14:14] */
#define DSC2B0_SM_CTRL0_BYPASS_TX_POSTC_CAL_MASK                   0x4000
#define DSC2B0_SM_CTRL0_BYPASS_TX_POSTC_CAL_ALIGN                  0
#define DSC2B0_SM_CTRL0_BYPASS_TX_POSTC_CAL_BITS                   1
#define DSC2B0_SM_CTRL0_BYPASS_TX_POSTC_CAL_SHIFT                  14

/* Dsc2b0 :: sm_ctrl0 :: bypass_br_vga [13:13] */
#define DSC2B0_SM_CTRL0_BYPASS_BR_VGA_MASK                         0x2000
#define DSC2B0_SM_CTRL0_BYPASS_BR_VGA_ALIGN                        0
#define DSC2B0_SM_CTRL0_BYPASS_BR_VGA_BITS                         1
#define DSC2B0_SM_CTRL0_BYPASS_BR_VGA_SHIFT                        13

/* Dsc2b0 :: sm_ctrl0 :: postc_metric_ctrl [12:12] */
#define DSC2B0_SM_CTRL0_POSTC_METRIC_CTRL_MASK                     0x1000
#define DSC2B0_SM_CTRL0_POSTC_METRIC_CTRL_ALIGN                    0
#define DSC2B0_SM_CTRL0_POSTC_METRIC_CTRL_BITS                     1
#define DSC2B0_SM_CTRL0_POSTC_METRIC_CTRL_SHIFT                    12

/* Dsc2b0 :: sm_ctrl0 :: hysteresis_en [11:11] */
#define DSC2B0_SM_CTRL0_HYSTERESIS_EN_MASK                         0x0800
#define DSC2B0_SM_CTRL0_HYSTERESIS_EN_ALIGN                        0
#define DSC2B0_SM_CTRL0_HYSTERESIS_EN_BITS                         1
#define DSC2B0_SM_CTRL0_HYSTERESIS_EN_SHIFT                        11

/* Dsc2b0 :: sm_ctrl0 :: slicer_cal_linear_srch [10:10] */
#define DSC2B0_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_MASK                0x0400
#define DSC2B0_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_ALIGN               0
#define DSC2B0_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_BITS                1
#define DSC2B0_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_SHIFT               10

/* Dsc2b0 :: sm_ctrl0 :: bypass_br_pf_cal [09:09] */
#define DSC2B0_SM_CTRL0_BYPASS_BR_PF_CAL_MASK                      0x0200
#define DSC2B0_SM_CTRL0_BYPASS_BR_PF_CAL_ALIGN                     0
#define DSC2B0_SM_CTRL0_BYPASS_BR_PF_CAL_BITS                      1
#define DSC2B0_SM_CTRL0_BYPASS_BR_PF_CAL_SHIFT                     9

/* Dsc2b0 :: sm_ctrl0 :: bypass_osx2_pf_cal [08:08] */
#define DSC2B0_SM_CTRL0_BYPASS_OSX2_PF_CAL_MASK                    0x0100
#define DSC2B0_SM_CTRL0_BYPASS_OSX2_PF_CAL_ALIGN                   0
#define DSC2B0_SM_CTRL0_BYPASS_OSX2_PF_CAL_BITS                    1
#define DSC2B0_SM_CTRL0_BYPASS_OSX2_PF_CAL_SHIFT                   8

/* Dsc2b0 :: sm_ctrl0 :: bypass_osx1_pf_cal [07:07] */
#define DSC2B0_SM_CTRL0_BYPASS_OSX1_PF_CAL_MASK                    0x0080
#define DSC2B0_SM_CTRL0_BYPASS_OSX1_PF_CAL_ALIGN                   0
#define DSC2B0_SM_CTRL0_BYPASS_OSX1_PF_CAL_BITS                    1
#define DSC2B0_SM_CTRL0_BYPASS_OSX1_PF_CAL_SHIFT                   7

/* Dsc2b0 :: sm_ctrl0 :: bypass_data_slicer_recal [06:06] */
#define DSC2B0_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_MASK              0x0040
#define DSC2B0_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_ALIGN             0
#define DSC2B0_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_BITS              1
#define DSC2B0_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_SHIFT             6

/* Dsc2b0 :: sm_ctrl0 :: bypass_osx45_slicer_cal [05:05] */
#define DSC2B0_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_MASK               0x0020
#define DSC2B0_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_ALIGN              0
#define DSC2B0_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_BITS               1
#define DSC2B0_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_SHIFT              5

/* Dsc2b0 :: sm_ctrl0 :: bypass_phase_slicer_cal [04:04] */
#define DSC2B0_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_MASK               0x0010
#define DSC2B0_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_ALIGN              0
#define DSC2B0_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_BITS               1
#define DSC2B0_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_SHIFT              4

/* Dsc2b0 :: sm_ctrl0 :: bypass_br_data_slicer_cal [03:03] */
#define DSC2B0_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_MASK             0x0008
#define DSC2B0_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_ALIGN            0
#define DSC2B0_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_BITS             1
#define DSC2B0_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_SHIFT            3

/* Dsc2b0 :: sm_ctrl0 :: bypass_os_data_slicer_cal [02:02] */
#define DSC2B0_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_MASK             0x0004
#define DSC2B0_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_ALIGN            0
#define DSC2B0_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_BITS             1
#define DSC2B0_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_SHIFT            2

/* Dsc2b0 :: sm_ctrl0 :: restart_tuning [01:01] */
#define DSC2B0_SM_CTRL0_RESTART_TUNING_MASK                        0x0002
#define DSC2B0_SM_CTRL0_RESTART_TUNING_ALIGN                       0
#define DSC2B0_SM_CTRL0_RESTART_TUNING_BITS                        1
#define DSC2B0_SM_CTRL0_RESTART_TUNING_SHIFT                       1

/* Dsc2b0 :: sm_ctrl0 :: tuning_sm_en [00:00] */
#define DSC2B0_SM_CTRL0_TUNING_SM_EN_MASK                          0x0001
#define DSC2B0_SM_CTRL0_TUNING_SM_EN_ALIGN                         0
#define DSC2B0_SM_CTRL0_TUNING_SM_EN_BITS                          1
#define DSC2B0_SM_CTRL0_TUNING_SM_EN_SHIFT                         0


/****************************************************************************
 * Dsc2b0 :: sm_ctrl1
 ***************************************************************************/
/* Dsc2b0 :: sm_ctrl1 :: fast_timer [15:15] */
#define DSC2B0_SM_CTRL1_FAST_TIMER_MASK                            0x8000
#define DSC2B0_SM_CTRL1_FAST_TIMER_ALIGN                           0
#define DSC2B0_SM_CTRL1_FAST_TIMER_BITS                            1
#define DSC2B0_SM_CTRL1_FAST_TIMER_SHIFT                           15

/* Dsc2b0 :: sm_ctrl1 :: acq2_timeout [14:10] */
#define DSC2B0_SM_CTRL1_ACQ2_TIMEOUT_MASK                          0x7c00
#define DSC2B0_SM_CTRL1_ACQ2_TIMEOUT_ALIGN                         0
#define DSC2B0_SM_CTRL1_ACQ2_TIMEOUT_BITS                          5
#define DSC2B0_SM_CTRL1_ACQ2_TIMEOUT_SHIFT                         10

/* Dsc2b0 :: sm_ctrl1 :: acq1_timeout [09:05] */
#define DSC2B0_SM_CTRL1_ACQ1_TIMEOUT_MASK                          0x03e0
#define DSC2B0_SM_CTRL1_ACQ1_TIMEOUT_ALIGN                         0
#define DSC2B0_SM_CTRL1_ACQ1_TIMEOUT_BITS                          5
#define DSC2B0_SM_CTRL1_ACQ1_TIMEOUT_SHIFT                         5

/* Dsc2b0 :: sm_ctrl1 :: acqcdr_timeout [04:00] */
#define DSC2B0_SM_CTRL1_ACQCDR_TIMEOUT_MASK                        0x001f
#define DSC2B0_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN                       0
#define DSC2B0_SM_CTRL1_ACQCDR_TIMEOUT_BITS                        5
#define DSC2B0_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT                       0


/****************************************************************************
 * Dsc2b0 :: sm_ctrl2
 ***************************************************************************/
/* Dsc2b0 :: sm_ctrl2 :: acqvga_timeout [15:11] */
#define DSC2B0_SM_CTRL2_ACQVGA_TIMEOUT_MASK                        0xf800
#define DSC2B0_SM_CTRL2_ACQVGA_TIMEOUT_ALIGN                       0
#define DSC2B0_SM_CTRL2_ACQVGA_TIMEOUT_BITS                        5
#define DSC2B0_SM_CTRL2_ACQVGA_TIMEOUT_SHIFT                       11

/* Dsc2b0 :: sm_ctrl2 :: bypass_os_integ_xfer [10:10] */
#define DSC2B0_SM_CTRL2_BYPASS_OS_INTEG_XFER_MASK                  0x0400
#define DSC2B0_SM_CTRL2_BYPASS_OS_INTEG_XFER_ALIGN                 0
#define DSC2B0_SM_CTRL2_BYPASS_OS_INTEG_XFER_BITS                  1
#define DSC2B0_SM_CTRL2_BYPASS_OS_INTEG_XFER_SHIFT                 10

/* Dsc2b0 :: sm_ctrl2 :: vga_frzval [09:09] */
#define DSC2B0_SM_CTRL2_VGA_FRZVAL_MASK                            0x0200
#define DSC2B0_SM_CTRL2_VGA_FRZVAL_ALIGN                           0
#define DSC2B0_SM_CTRL2_VGA_FRZVAL_BITS                            1
#define DSC2B0_SM_CTRL2_VGA_FRZVAL_SHIFT                           9

/* Dsc2b0 :: sm_ctrl2 :: vga_frcfrz [08:08] */
#define DSC2B0_SM_CTRL2_VGA_FRCFRZ_MASK                            0x0100
#define DSC2B0_SM_CTRL2_VGA_FRCFRZ_ALIGN                           0
#define DSC2B0_SM_CTRL2_VGA_FRCFRZ_BITS                            1
#define DSC2B0_SM_CTRL2_VGA_FRCFRZ_SHIFT                           8

/* Dsc2b0 :: sm_ctrl2 :: dfe_frzval [07:07] */
#define DSC2B0_SM_CTRL2_DFE_FRZVAL_MASK                            0x0080
#define DSC2B0_SM_CTRL2_DFE_FRZVAL_ALIGN                           0
#define DSC2B0_SM_CTRL2_DFE_FRZVAL_BITS                            1
#define DSC2B0_SM_CTRL2_DFE_FRZVAL_SHIFT                           7

/* Dsc2b0 :: sm_ctrl2 :: dfe_frcfrz [06:06] */
#define DSC2B0_SM_CTRL2_DFE_FRCFRZ_MASK                            0x0040
#define DSC2B0_SM_CTRL2_DFE_FRCFRZ_ALIGN                           0
#define DSC2B0_SM_CTRL2_DFE_FRCFRZ_BITS                            1
#define DSC2B0_SM_CTRL2_DFE_FRCFRZ_SHIFT                           6

/* Dsc2b0 :: sm_ctrl2 :: dsc_clr_val [05:05] */
#define DSC2B0_SM_CTRL2_DSC_CLR_VAL_MASK                           0x0020
#define DSC2B0_SM_CTRL2_DSC_CLR_VAL_ALIGN                          0
#define DSC2B0_SM_CTRL2_DSC_CLR_VAL_BITS                           1
#define DSC2B0_SM_CTRL2_DSC_CLR_VAL_SHIFT                          5

/* Dsc2b0 :: sm_ctrl2 :: dsc_clr_frc [04:04] */
#define DSC2B0_SM_CTRL2_DSC_CLR_FRC_MASK                           0x0010
#define DSC2B0_SM_CTRL2_DSC_CLR_FRC_ALIGN                          0
#define DSC2B0_SM_CTRL2_DSC_CLR_FRC_BITS                           1
#define DSC2B0_SM_CTRL2_DSC_CLR_FRC_SHIFT                          4

/* Dsc2b0 :: sm_ctrl2 :: train2_req [03:03] */
#define DSC2B0_SM_CTRL2_TRAIN2_REQ_MASK                            0x0008
#define DSC2B0_SM_CTRL2_TRAIN2_REQ_ALIGN                           0
#define DSC2B0_SM_CTRL2_TRAIN2_REQ_BITS                            1
#define DSC2B0_SM_CTRL2_TRAIN2_REQ_SHIFT                           3

/* Dsc2b0 :: sm_ctrl2 :: train1_req [02:02] */
#define DSC2B0_SM_CTRL2_TRAIN1_REQ_MASK                            0x0004
#define DSC2B0_SM_CTRL2_TRAIN1_REQ_ALIGN                           0
#define DSC2B0_SM_CTRL2_TRAIN1_REQ_BITS                            1
#define DSC2B0_SM_CTRL2_TRAIN1_REQ_SHIFT                           2

/* Dsc2b0 :: sm_ctrl2 :: soft_ack [01:01] */
#define DSC2B0_SM_CTRL2_SOFT_ACK_MASK                              0x0002
#define DSC2B0_SM_CTRL2_SOFT_ACK_ALIGN                             0
#define DSC2B0_SM_CTRL2_SOFT_ACK_BITS                              1
#define DSC2B0_SM_CTRL2_SOFT_ACK_SHIFT                             1

/* Dsc2b0 :: sm_ctrl2 :: train_mode_en [00:00] */
#define DSC2B0_SM_CTRL2_TRAIN_MODE_EN_MASK                         0x0001
#define DSC2B0_SM_CTRL2_TRAIN_MODE_EN_ALIGN                        0
#define DSC2B0_SM_CTRL2_TRAIN_MODE_EN_BITS                         1
#define DSC2B0_SM_CTRL2_TRAIN_MODE_EN_SHIFT                        0


/****************************************************************************
 * Dsc2b0 :: sm_ctrl3
 ***************************************************************************/
/* Dsc2b0 :: sm_ctrl3 :: reserved_for_eco0 [15:15] */
#define DSC2B0_SM_CTRL3_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2B0_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B0_SM_CTRL3_RESERVED_FOR_ECO0_BITS                     1
#define DSC2B0_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2b0 :: sm_ctrl3 :: cdrbr_bwsel_prop_acqcdr [14:12] */
#define DSC2B0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_MASK               0x7000
#define DSC2B0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_ALIGN              0
#define DSC2B0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_BITS               3
#define DSC2B0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_SHIFT              12

/* Dsc2b0 :: sm_ctrl3 :: dfe_gain_acq2 [11:10] */
#define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ2_MASK                         0x0c00
#define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN                        0
#define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ2_BITS                         2
#define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT                        10

/* Dsc2b0 :: sm_ctrl3 :: dfe_gain_acq1 [09:08] */
#define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ1_MASK                         0x0300
#define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN                        0
#define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ1_BITS                         2
#define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT                        8

/* Dsc2b0 :: sm_ctrl3 :: vga_gain_acq2 [07:06] */
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ2_MASK                         0x00c0
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN                        0
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ2_BITS                         2
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT                        6

/* Dsc2b0 :: sm_ctrl3 :: vga_gain_acq1 [05:04] */
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ1_MASK                         0x0030
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN                        0
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ1_BITS                         2
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT                        4

/* Dsc2b0 :: sm_ctrl3 :: vga_gain_acqcdr [03:02] */
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQCDR_MASK                       0x000c
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN                      0
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQCDR_BITS                       2
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT                      2

/* Dsc2b0 :: sm_ctrl3 :: vga_gain_acqvga [01:00] */
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQVGA_MASK                       0x0003
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN                      0
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQVGA_BITS                       2
#define DSC2B0_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT                      0


/****************************************************************************
 * Dsc2b0 :: sm_ctrl4
 ***************************************************************************/
/* Dsc2b0 :: sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */
#define DSC2B0_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK             0xc000
#define DSC2B0_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN            0
#define DSC2B0_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS             2
#define DSC2B0_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT            14

/* Dsc2b0 :: sm_ctrl4 :: cdros45_bwsel_integ_offset [13:12] */
#define DSC2B0_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_MASK            0x3000
#define DSC2B0_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_ALIGN           0
#define DSC2B0_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_BITS            2
#define DSC2B0_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_SHIFT           12

/* Dsc2b0 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq2 [11:10] */
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_MASK                0x0c00
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_ALIGN               0
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_BITS                2
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_SHIFT               10

/* Dsc2b0 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq1 [09:08] */
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_MASK                0x0300
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_ALIGN               0
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_BITS                2
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_SHIFT               8

/* Dsc2b0 :: sm_ctrl4 :: cdrbr_bwsel_integ_acqcdr [07:06] */
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_MASK              0x00c0
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN             0
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_BITS              2
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT             6

/* Dsc2b0 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq2 [05:03] */
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_MASK                 0x0038
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_ALIGN                0
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_BITS                 3
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_SHIFT                3

/* Dsc2b0 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq1 [02:00] */
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_MASK                 0x0007
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_ALIGN                0
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_BITS                 3
#define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_SHIFT                0


/****************************************************************************
 * Dsc2b0 :: sm_ctrl5
 ***************************************************************************/
/* Dsc2b0 :: sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [15:12] */
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK              0xf000
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN             0
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS              4
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT             12

/* Dsc2b0 :: sm_ctrl5 :: cdros_bwsel_integ_acqcdr [11:08] */
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK              0x0f00
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN             0
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS              4
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT             8

/* Dsc2b0 :: sm_ctrl5 :: cdros_bwsel_prop_acq1_2 [07:04] */
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_MASK               0x00f0
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_ALIGN              0
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_BITS               4
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_SHIFT              4

/* Dsc2b0 :: sm_ctrl5 :: cdros_bwsel_prop_acqcdr [03:00] */
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_MASK               0x000f
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_ALIGN              0
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_BITS               4
#define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_SHIFT              0


/****************************************************************************
 * Dsc2b0 :: sm_ctrl6
 ***************************************************************************/
/* Dsc2b0 :: sm_ctrl6 :: reserved_for_eco0 [15:13] */
#define DSC2B0_SM_CTRL6_RESERVED_FOR_ECO0_MASK                     0xe000
#define DSC2B0_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B0_SM_CTRL6_RESERVED_FOR_ECO0_BITS                     3
#define DSC2B0_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT                    13

/* Dsc2b0 :: sm_ctrl6 :: cdrbr_bwsel_integ_acqphase [12:11] */
#define DSC2B0_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_MASK            0x1800
#define DSC2B0_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN           0
#define DSC2B0_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_BITS            2
#define DSC2B0_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT           11

/* Dsc2b0 :: sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [10:08] */
#define DSC2B0_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK             0x0700
#define DSC2B0_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN            0
#define DSC2B0_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS             3
#define DSC2B0_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT            8

/* Dsc2b0 :: sm_ctrl6 :: cdros_bwsel_integ_acqvga [07:04] */
#define DSC2B0_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_MASK              0x00f0
#define DSC2B0_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_ALIGN             0
#define DSC2B0_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_BITS              4
#define DSC2B0_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_SHIFT             4

/* Dsc2b0 :: sm_ctrl6 :: cdros_bwsel_prop_acqvga [03:00] */
#define DSC2B0_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_MASK               0x000f
#define DSC2B0_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_ALIGN              0
#define DSC2B0_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_BITS               4
#define DSC2B0_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_SHIFT              0


/****************************************************************************
 * Dsc2b0 :: sm_ctrl7
 ***************************************************************************/
/* Dsc2b0 :: sm_ctrl7 :: reserved_for_eco0 [15:15] */
#define DSC2B0_SM_CTRL7_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2B0_SM_CTRL7_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B0_SM_CTRL7_RESERVED_FOR_ECO0_BITS                     1
#define DSC2B0_SM_CTRL7_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2b0 :: sm_ctrl7 :: pf_ctrl_br_offset [14:12] */
#define DSC2B0_SM_CTRL7_PF_CTRL_BR_OFFSET_MASK                     0x7000
#define DSC2B0_SM_CTRL7_PF_CTRL_BR_OFFSET_ALIGN                    0
#define DSC2B0_SM_CTRL7_PF_CTRL_BR_OFFSET_BITS                     3
#define DSC2B0_SM_CTRL7_PF_CTRL_BR_OFFSET_SHIFT                    12

/* Dsc2b0 :: sm_ctrl7 :: pf_ctrl_osx1_offset [11:09] */
#define DSC2B0_SM_CTRL7_PF_CTRL_OSX1_OFFSET_MASK                   0x0e00
#define DSC2B0_SM_CTRL7_PF_CTRL_OSX1_OFFSET_ALIGN                  0
#define DSC2B0_SM_CTRL7_PF_CTRL_OSX1_OFFSET_BITS                   3
#define DSC2B0_SM_CTRL7_PF_CTRL_OSX1_OFFSET_SHIFT                  9

/* Dsc2b0 :: sm_ctrl7 :: pf_ctrl_osx2_offset [08:06] */
#define DSC2B0_SM_CTRL7_PF_CTRL_OSX2_OFFSET_MASK                   0x01c0
#define DSC2B0_SM_CTRL7_PF_CTRL_OSX2_OFFSET_ALIGN                  0
#define DSC2B0_SM_CTRL7_PF_CTRL_OSX2_OFFSET_BITS                   3
#define DSC2B0_SM_CTRL7_PF_CTRL_OSX2_OFFSET_SHIFT                  6

/* Dsc2b0 :: sm_ctrl7 :: pf_ctrl_br_init [05:03] */
#define DSC2B0_SM_CTRL7_PF_CTRL_BR_INIT_MASK                       0x0038
#define DSC2B0_SM_CTRL7_PF_CTRL_BR_INIT_ALIGN                      0
#define DSC2B0_SM_CTRL7_PF_CTRL_BR_INIT_BITS                       3
#define DSC2B0_SM_CTRL7_PF_CTRL_BR_INIT_SHIFT                      3

/* Dsc2b0 :: sm_ctrl7 :: pf_ctrl_os_init [02:00] */
#define DSC2B0_SM_CTRL7_PF_CTRL_OS_INIT_MASK                       0x0007
#define DSC2B0_SM_CTRL7_PF_CTRL_OS_INIT_ALIGN                      0
#define DSC2B0_SM_CTRL7_PF_CTRL_OS_INIT_BITS                       3
#define DSC2B0_SM_CTRL7_PF_CTRL_OS_INIT_SHIFT                      0


/****************************************************************************
 * Dsc2b0 :: sm_ctrl8
 ***************************************************************************/
/* Dsc2b0 :: sm_ctrl8 :: reserved_for_eco0 [15:10] */
#define DSC2B0_SM_CTRL8_RESERVED_FOR_ECO0_MASK                     0xfc00
#define DSC2B0_SM_CTRL8_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B0_SM_CTRL8_RESERVED_FOR_ECO0_BITS                     6
#define DSC2B0_SM_CTRL8_RESERVED_FOR_ECO0_SHIFT                    10

/* Dsc2b0 :: sm_ctrl8 :: vga_max_val [09:05] */
#define DSC2B0_SM_CTRL8_VGA_MAX_VAL_MASK                           0x03e0
#define DSC2B0_SM_CTRL8_VGA_MAX_VAL_ALIGN                          0
#define DSC2B0_SM_CTRL8_VGA_MAX_VAL_BITS                           5
#define DSC2B0_SM_CTRL8_VGA_MAX_VAL_SHIFT                          5

/* Dsc2b0 :: sm_ctrl8 :: vga_min_val [04:00] */
#define DSC2B0_SM_CTRL8_VGA_MIN_VAL_MASK                           0x001f
#define DSC2B0_SM_CTRL8_VGA_MIN_VAL_ALIGN                          0
#define DSC2B0_SM_CTRL8_VGA_MIN_VAL_BITS                           5
#define DSC2B0_SM_CTRL8_VGA_MIN_VAL_SHIFT                          0


/****************************************************************************
 * Dsc2b0 :: sm_ctrl9
 ***************************************************************************/
/* Dsc2b0 :: sm_ctrl9 :: reserved_for_eco0 [15:12] */
#define DSC2B0_SM_CTRL9_RESERVED_FOR_ECO0_MASK                     0xf000
#define DSC2B0_SM_CTRL9_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B0_SM_CTRL9_RESERVED_FOR_ECO0_BITS                     4
#define DSC2B0_SM_CTRL9_RESERVED_FOR_ECO0_SHIFT                    12

/* Dsc2b0 :: sm_ctrl9 :: dfe_max_val [11:06] */
#define DSC2B0_SM_CTRL9_DFE_MAX_VAL_MASK                           0x0fc0
#define DSC2B0_SM_CTRL9_DFE_MAX_VAL_ALIGN                          0
#define DSC2B0_SM_CTRL9_DFE_MAX_VAL_BITS                           6
#define DSC2B0_SM_CTRL9_DFE_MAX_VAL_SHIFT                          6

/* Dsc2b0 :: sm_ctrl9 :: dfe_min_val [05:00] */
#define DSC2B0_SM_CTRL9_DFE_MIN_VAL_MASK                           0x003f
#define DSC2B0_SM_CTRL9_DFE_MIN_VAL_ALIGN                          0
#define DSC2B0_SM_CTRL9_DFE_MIN_VAL_BITS                           6
#define DSC2B0_SM_CTRL9_DFE_MIN_VAL_SHIFT                          0


/****************************************************************************
 * Dsc2b0 :: sm_ctrl10
 ***************************************************************************/
/* Dsc2b0 :: sm_ctrl10 :: reserved_for_eco0 [15:14] */
#define DSC2B0_SM_CTRL10_RESERVED_FOR_ECO0_MASK                    0xc000
#define DSC2B0_SM_CTRL10_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2B0_SM_CTRL10_RESERVED_FOR_ECO0_BITS                    2
#define DSC2B0_SM_CTRL10_RESERVED_FOR_ECO0_SHIFT                   14

/* Dsc2b0 :: sm_ctrl10 :: br_pf_tap_en [13:07] */
#define DSC2B0_SM_CTRL10_BR_PF_TAP_EN_MASK                         0x3f80
#define DSC2B0_SM_CTRL10_BR_PF_TAP_EN_ALIGN                        0
#define DSC2B0_SM_CTRL10_BR_PF_TAP_EN_BITS                         7
#define DSC2B0_SM_CTRL10_BR_PF_TAP_EN_SHIFT                        7

/* Dsc2b0 :: sm_ctrl10 :: osx1_pf_tap_en [06:00] */
#define DSC2B0_SM_CTRL10_OSX1_PF_TAP_EN_MASK                       0x007f
#define DSC2B0_SM_CTRL10_OSX1_PF_TAP_EN_ALIGN                      0
#define DSC2B0_SM_CTRL10_OSX1_PF_TAP_EN_BITS                       7
#define DSC2B0_SM_CTRL10_OSX1_PF_TAP_EN_SHIFT                      0


/****************************************************************************
 * Dsc2b0 :: sm_ctrl11
 ***************************************************************************/
/* Dsc2b0 :: sm_ctrl11 :: reserved_for_eco0 [15:15] */
#define DSC2B0_SM_CTRL11_RESERVED_FOR_ECO0_MASK                    0x8000
#define DSC2B0_SM_CTRL11_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2B0_SM_CTRL11_RESERVED_FOR_ECO0_BITS                    1
#define DSC2B0_SM_CTRL11_RESERVED_FOR_ECO0_SHIFT                   15

/* Dsc2b0 :: sm_ctrl11 :: msr_br_vga_timeout [14:10] */
#define DSC2B0_SM_CTRL11_MSR_BR_VGA_TIMEOUT_MASK                   0x7c00
#define DSC2B0_SM_CTRL11_MSR_BR_VGA_TIMEOUT_ALIGN                  0
#define DSC2B0_SM_CTRL11_MSR_BR_VGA_TIMEOUT_BITS                   5
#define DSC2B0_SM_CTRL11_MSR_BR_VGA_TIMEOUT_SHIFT                  10

/* Dsc2b0 :: sm_ctrl11 :: hysteresis_timeout [09:05] */
#define DSC2B0_SM_CTRL11_HYSTERESIS_TIMEOUT_MASK                   0x03e0
#define DSC2B0_SM_CTRL11_HYSTERESIS_TIMEOUT_ALIGN                  0
#define DSC2B0_SM_CTRL11_HYSTERESIS_TIMEOUT_BITS                   5
#define DSC2B0_SM_CTRL11_HYSTERESIS_TIMEOUT_SHIFT                  5

/* Dsc2b0 :: sm_ctrl11 :: msr_postc_timeout [04:00] */
#define DSC2B0_SM_CTRL11_MSR_POSTC_TIMEOUT_MASK                    0x001f
#define DSC2B0_SM_CTRL11_MSR_POSTC_TIMEOUT_ALIGN                   0
#define DSC2B0_SM_CTRL11_MSR_POSTC_TIMEOUT_BITS                    5
#define DSC2B0_SM_CTRL11_MSR_POSTC_TIMEOUT_SHIFT                   0


/****************************************************************************
 * Dsc2b0 :: sm_ctrl12
 ***************************************************************************/
/* Dsc2b0 :: sm_ctrl12 :: reserved_for_eco0 [15:14] */
#define DSC2B0_SM_CTRL12_RESERVED_FOR_ECO0_MASK                    0xc000
#define DSC2B0_SM_CTRL12_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2B0_SM_CTRL12_RESERVED_FOR_ECO0_BITS                    2
#define DSC2B0_SM_CTRL12_RESERVED_FOR_ECO0_SHIFT                   14

/* Dsc2b0 :: sm_ctrl12 :: br_vga_lms_gain [13:12] */
#define DSC2B0_SM_CTRL12_BR_VGA_LMS_GAIN_MASK                      0x3000
#define DSC2B0_SM_CTRL12_BR_VGA_LMS_GAIN_ALIGN                     0
#define DSC2B0_SM_CTRL12_BR_VGA_LMS_GAIN_BITS                      2
#define DSC2B0_SM_CTRL12_BR_VGA_LMS_GAIN_SHIFT                     12

/* Dsc2b0 :: sm_ctrl12 :: postc_dfe_lms_gain [11:10] */
#define DSC2B0_SM_CTRL12_POSTC_DFE_LMS_GAIN_MASK                   0x0c00
#define DSC2B0_SM_CTRL12_POSTC_DFE_LMS_GAIN_ALIGN                  0
#define DSC2B0_SM_CTRL12_POSTC_DFE_LMS_GAIN_BITS                   2
#define DSC2B0_SM_CTRL12_POSTC_DFE_LMS_GAIN_SHIFT                  10

/* Dsc2b0 :: sm_ctrl12 :: cdr_phase_inversion_timeout [09:05] */
#define DSC2B0_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_MASK          0x03e0
#define DSC2B0_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_ALIGN         0
#define DSC2B0_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_BITS          5
#define DSC2B0_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_SHIFT         5

/* Dsc2b0 :: sm_ctrl12 :: msr_pf_timeout [04:00] */
#define DSC2B0_SM_CTRL12_MSR_PF_TIMEOUT_MASK                       0x001f
#define DSC2B0_SM_CTRL12_MSR_PF_TIMEOUT_ALIGN                      0
#define DSC2B0_SM_CTRL12_MSR_PF_TIMEOUT_BITS                       5
#define DSC2B0_SM_CTRL12_MSR_PF_TIMEOUT_SHIFT                      0


/****************************************************************************
 * Dsc2b0 :: dsc_diag_ctrl0
 ***************************************************************************/
/* Dsc2b0 :: dsc_diag_ctrl0 :: reserved_for_eco0 [15:11] */
#define DSC2B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_MASK               0xf800
#define DSC2B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC2B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_BITS               5
#define DSC2B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_SHIFT              11

/* Dsc2b0 :: dsc_diag_ctrl0 :: voffset [10:07] */
#define DSC2B0_DSC_DIAG_CTRL0_VOFFSET_MASK                         0x0780
#define DSC2B0_DSC_DIAG_CTRL0_VOFFSET_ALIGN                        0
#define DSC2B0_DSC_DIAG_CTRL0_VOFFSET_BITS                         4
#define DSC2B0_DSC_DIAG_CTRL0_VOFFSET_SHIFT                        7

/* Dsc2b0 :: dsc_diag_ctrl0 :: hoffset [06:01] */
#define DSC2B0_DSC_DIAG_CTRL0_HOFFSET_MASK                         0x007e
#define DSC2B0_DSC_DIAG_CTRL0_HOFFSET_ALIGN                        0
#define DSC2B0_DSC_DIAG_CTRL0_HOFFSET_BITS                         6
#define DSC2B0_DSC_DIAG_CTRL0_HOFFSET_SHIFT                        1

/* Dsc2b0 :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */
#define DSC2B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK                  0x0001
#define DSC2B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN                 0
#define DSC2B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS                  1
#define DSC2B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT                 0


/****************************************************************************
 * Dsc2b0 :: dsc_misc_ctrl0
 ***************************************************************************/
/* Dsc2b0 :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */
#define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_MASK                      0x8000
#define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_ALIGN                     0
#define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_BITS                      1
#define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_SHIFT                     15

/* Dsc2b0 :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */
#define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK                  0x4000
#define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN                 0
#define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS                  1
#define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT                 14

/* Dsc2b0 :: dsc_misc_ctrl0 :: enable_acor_picw [13:13] */
#define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_MASK                0x2000
#define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_ALIGN               0
#define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_BITS                1
#define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_SHIFT               13

/* Dsc2b0 :: dsc_misc_ctrl0 :: reserved_for_eco0 [12:10] */
#define DSC2B0_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_MASK               0x1c00
#define DSC2B0_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC2B0_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_BITS               3
#define DSC2B0_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_SHIFT              10

/* Dsc2b0 :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */
#define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK                 0x0200
#define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN                0
#define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS                 1
#define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT                9

/* Dsc2b0 :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */
#define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK             0x0100
#define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN            0
#define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS             1
#define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT            8

/* Dsc2b0 :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */
#define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK                  0x0080
#define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN                 0
#define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS                  1
#define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT                 7

/* Dsc2b0 :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */
#define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK              0x0070
#define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN             0
#define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS              3
#define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT             4

/* Dsc2b0 :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */
#define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK                    0x000f
#define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN                   0
#define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS                    4
#define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT                   0
#define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_Off                     0
#define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data                1
#define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1             2
#define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1           3
#define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco             4
#define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg                 6
#define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr             7
#define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd           8
#define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe            9
#define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum               10


/****************************************************************************
 * Hypercore_USER_Dsc2b1
 ***************************************************************************/
/****************************************************************************
 * Dsc2b1 :: sm_ctrl0
 ***************************************************************************/
/* Dsc2b1 :: sm_ctrl0 :: reserved_for_eco0 [15:15] */
#define DSC2B1_SM_CTRL0_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2B1_SM_CTRL0_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B1_SM_CTRL0_RESERVED_FOR_ECO0_BITS                     1
#define DSC2B1_SM_CTRL0_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2b1 :: sm_ctrl0 :: bypass_tx_postc_cal [14:14] */
#define DSC2B1_SM_CTRL0_BYPASS_TX_POSTC_CAL_MASK                   0x4000
#define DSC2B1_SM_CTRL0_BYPASS_TX_POSTC_CAL_ALIGN                  0
#define DSC2B1_SM_CTRL0_BYPASS_TX_POSTC_CAL_BITS                   1
#define DSC2B1_SM_CTRL0_BYPASS_TX_POSTC_CAL_SHIFT                  14

/* Dsc2b1 :: sm_ctrl0 :: bypass_br_vga [13:13] */
#define DSC2B1_SM_CTRL0_BYPASS_BR_VGA_MASK                         0x2000
#define DSC2B1_SM_CTRL0_BYPASS_BR_VGA_ALIGN                        0
#define DSC2B1_SM_CTRL0_BYPASS_BR_VGA_BITS                         1
#define DSC2B1_SM_CTRL0_BYPASS_BR_VGA_SHIFT                        13

/* Dsc2b1 :: sm_ctrl0 :: postc_metric_ctrl [12:12] */
#define DSC2B1_SM_CTRL0_POSTC_METRIC_CTRL_MASK                     0x1000
#define DSC2B1_SM_CTRL0_POSTC_METRIC_CTRL_ALIGN                    0
#define DSC2B1_SM_CTRL0_POSTC_METRIC_CTRL_BITS                     1
#define DSC2B1_SM_CTRL0_POSTC_METRIC_CTRL_SHIFT                    12

/* Dsc2b1 :: sm_ctrl0 :: hysteresis_en [11:11] */
#define DSC2B1_SM_CTRL0_HYSTERESIS_EN_MASK                         0x0800
#define DSC2B1_SM_CTRL0_HYSTERESIS_EN_ALIGN                        0
#define DSC2B1_SM_CTRL0_HYSTERESIS_EN_BITS                         1
#define DSC2B1_SM_CTRL0_HYSTERESIS_EN_SHIFT                        11

/* Dsc2b1 :: sm_ctrl0 :: slicer_cal_linear_srch [10:10] */
#define DSC2B1_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_MASK                0x0400
#define DSC2B1_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_ALIGN               0
#define DSC2B1_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_BITS                1
#define DSC2B1_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_SHIFT               10

/* Dsc2b1 :: sm_ctrl0 :: bypass_br_pf_cal [09:09] */
#define DSC2B1_SM_CTRL0_BYPASS_BR_PF_CAL_MASK                      0x0200
#define DSC2B1_SM_CTRL0_BYPASS_BR_PF_CAL_ALIGN                     0
#define DSC2B1_SM_CTRL0_BYPASS_BR_PF_CAL_BITS                      1
#define DSC2B1_SM_CTRL0_BYPASS_BR_PF_CAL_SHIFT                     9

/* Dsc2b1 :: sm_ctrl0 :: bypass_osx2_pf_cal [08:08] */
#define DSC2B1_SM_CTRL0_BYPASS_OSX2_PF_CAL_MASK                    0x0100
#define DSC2B1_SM_CTRL0_BYPASS_OSX2_PF_CAL_ALIGN                   0
#define DSC2B1_SM_CTRL0_BYPASS_OSX2_PF_CAL_BITS                    1
#define DSC2B1_SM_CTRL0_BYPASS_OSX2_PF_CAL_SHIFT                   8

/* Dsc2b1 :: sm_ctrl0 :: bypass_osx1_pf_cal [07:07] */
#define DSC2B1_SM_CTRL0_BYPASS_OSX1_PF_CAL_MASK                    0x0080
#define DSC2B1_SM_CTRL0_BYPASS_OSX1_PF_CAL_ALIGN                   0
#define DSC2B1_SM_CTRL0_BYPASS_OSX1_PF_CAL_BITS                    1
#define DSC2B1_SM_CTRL0_BYPASS_OSX1_PF_CAL_SHIFT                   7

/* Dsc2b1 :: sm_ctrl0 :: bypass_data_slicer_recal [06:06] */
#define DSC2B1_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_MASK              0x0040
#define DSC2B1_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_ALIGN             0
#define DSC2B1_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_BITS              1
#define DSC2B1_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_SHIFT             6

/* Dsc2b1 :: sm_ctrl0 :: bypass_osx45_slicer_cal [05:05] */
#define DSC2B1_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_MASK               0x0020
#define DSC2B1_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_ALIGN              0
#define DSC2B1_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_BITS               1
#define DSC2B1_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_SHIFT              5

/* Dsc2b1 :: sm_ctrl0 :: bypass_phase_slicer_cal [04:04] */
#define DSC2B1_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_MASK               0x0010
#define DSC2B1_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_ALIGN              0
#define DSC2B1_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_BITS               1
#define DSC2B1_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_SHIFT              4

/* Dsc2b1 :: sm_ctrl0 :: bypass_br_data_slicer_cal [03:03] */
#define DSC2B1_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_MASK             0x0008
#define DSC2B1_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_ALIGN            0
#define DSC2B1_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_BITS             1
#define DSC2B1_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_SHIFT            3

/* Dsc2b1 :: sm_ctrl0 :: bypass_os_data_slicer_cal [02:02] */
#define DSC2B1_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_MASK             0x0004
#define DSC2B1_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_ALIGN            0
#define DSC2B1_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_BITS             1
#define DSC2B1_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_SHIFT            2

/* Dsc2b1 :: sm_ctrl0 :: restart_tuning [01:01] */
#define DSC2B1_SM_CTRL0_RESTART_TUNING_MASK                        0x0002
#define DSC2B1_SM_CTRL0_RESTART_TUNING_ALIGN                       0
#define DSC2B1_SM_CTRL0_RESTART_TUNING_BITS                        1
#define DSC2B1_SM_CTRL0_RESTART_TUNING_SHIFT                       1

/* Dsc2b1 :: sm_ctrl0 :: tuning_sm_en [00:00] */
#define DSC2B1_SM_CTRL0_TUNING_SM_EN_MASK                          0x0001
#define DSC2B1_SM_CTRL0_TUNING_SM_EN_ALIGN                         0
#define DSC2B1_SM_CTRL0_TUNING_SM_EN_BITS                          1
#define DSC2B1_SM_CTRL0_TUNING_SM_EN_SHIFT                         0


/****************************************************************************
 * Dsc2b1 :: sm_ctrl1
 ***************************************************************************/
/* Dsc2b1 :: sm_ctrl1 :: fast_timer [15:15] */
#define DSC2B1_SM_CTRL1_FAST_TIMER_MASK                            0x8000
#define DSC2B1_SM_CTRL1_FAST_TIMER_ALIGN                           0
#define DSC2B1_SM_CTRL1_FAST_TIMER_BITS                            1
#define DSC2B1_SM_CTRL1_FAST_TIMER_SHIFT                           15

/* Dsc2b1 :: sm_ctrl1 :: acq2_timeout [14:10] */
#define DSC2B1_SM_CTRL1_ACQ2_TIMEOUT_MASK                          0x7c00
#define DSC2B1_SM_CTRL1_ACQ2_TIMEOUT_ALIGN                         0
#define DSC2B1_SM_CTRL1_ACQ2_TIMEOUT_BITS                          5
#define DSC2B1_SM_CTRL1_ACQ2_TIMEOUT_SHIFT                         10

/* Dsc2b1 :: sm_ctrl1 :: acq1_timeout [09:05] */
#define DSC2B1_SM_CTRL1_ACQ1_TIMEOUT_MASK                          0x03e0
#define DSC2B1_SM_CTRL1_ACQ1_TIMEOUT_ALIGN                         0
#define DSC2B1_SM_CTRL1_ACQ1_TIMEOUT_BITS                          5
#define DSC2B1_SM_CTRL1_ACQ1_TIMEOUT_SHIFT                         5

/* Dsc2b1 :: sm_ctrl1 :: acqcdr_timeout [04:00] */
#define DSC2B1_SM_CTRL1_ACQCDR_TIMEOUT_MASK                        0x001f
#define DSC2B1_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN                       0
#define DSC2B1_SM_CTRL1_ACQCDR_TIMEOUT_BITS                        5
#define DSC2B1_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT                       0


/****************************************************************************
 * Dsc2b1 :: sm_ctrl2
 ***************************************************************************/
/* Dsc2b1 :: sm_ctrl2 :: acqvga_timeout [15:11] */
#define DSC2B1_SM_CTRL2_ACQVGA_TIMEOUT_MASK                        0xf800
#define DSC2B1_SM_CTRL2_ACQVGA_TIMEOUT_ALIGN                       0
#define DSC2B1_SM_CTRL2_ACQVGA_TIMEOUT_BITS                        5
#define DSC2B1_SM_CTRL2_ACQVGA_TIMEOUT_SHIFT                       11

/* Dsc2b1 :: sm_ctrl2 :: bypass_os_integ_xfer [10:10] */
#define DSC2B1_SM_CTRL2_BYPASS_OS_INTEG_XFER_MASK                  0x0400
#define DSC2B1_SM_CTRL2_BYPASS_OS_INTEG_XFER_ALIGN                 0
#define DSC2B1_SM_CTRL2_BYPASS_OS_INTEG_XFER_BITS                  1
#define DSC2B1_SM_CTRL2_BYPASS_OS_INTEG_XFER_SHIFT                 10

/* Dsc2b1 :: sm_ctrl2 :: vga_frzval [09:09] */
#define DSC2B1_SM_CTRL2_VGA_FRZVAL_MASK                            0x0200
#define DSC2B1_SM_CTRL2_VGA_FRZVAL_ALIGN                           0
#define DSC2B1_SM_CTRL2_VGA_FRZVAL_BITS                            1
#define DSC2B1_SM_CTRL2_VGA_FRZVAL_SHIFT                           9

/* Dsc2b1 :: sm_ctrl2 :: vga_frcfrz [08:08] */
#define DSC2B1_SM_CTRL2_VGA_FRCFRZ_MASK                            0x0100
#define DSC2B1_SM_CTRL2_VGA_FRCFRZ_ALIGN                           0
#define DSC2B1_SM_CTRL2_VGA_FRCFRZ_BITS                            1
#define DSC2B1_SM_CTRL2_VGA_FRCFRZ_SHIFT                           8

/* Dsc2b1 :: sm_ctrl2 :: dfe_frzval [07:07] */
#define DSC2B1_SM_CTRL2_DFE_FRZVAL_MASK                            0x0080
#define DSC2B1_SM_CTRL2_DFE_FRZVAL_ALIGN                           0
#define DSC2B1_SM_CTRL2_DFE_FRZVAL_BITS                            1
#define DSC2B1_SM_CTRL2_DFE_FRZVAL_SHIFT                           7

/* Dsc2b1 :: sm_ctrl2 :: dfe_frcfrz [06:06] */
#define DSC2B1_SM_CTRL2_DFE_FRCFRZ_MASK                            0x0040
#define DSC2B1_SM_CTRL2_DFE_FRCFRZ_ALIGN                           0
#define DSC2B1_SM_CTRL2_DFE_FRCFRZ_BITS                            1
#define DSC2B1_SM_CTRL2_DFE_FRCFRZ_SHIFT                           6

/* Dsc2b1 :: sm_ctrl2 :: dsc_clr_val [05:05] */
#define DSC2B1_SM_CTRL2_DSC_CLR_VAL_MASK                           0x0020
#define DSC2B1_SM_CTRL2_DSC_CLR_VAL_ALIGN                          0
#define DSC2B1_SM_CTRL2_DSC_CLR_VAL_BITS                           1
#define DSC2B1_SM_CTRL2_DSC_CLR_VAL_SHIFT                          5

/* Dsc2b1 :: sm_ctrl2 :: dsc_clr_frc [04:04] */
#define DSC2B1_SM_CTRL2_DSC_CLR_FRC_MASK                           0x0010
#define DSC2B1_SM_CTRL2_DSC_CLR_FRC_ALIGN                          0
#define DSC2B1_SM_CTRL2_DSC_CLR_FRC_BITS                           1
#define DSC2B1_SM_CTRL2_DSC_CLR_FRC_SHIFT                          4

/* Dsc2b1 :: sm_ctrl2 :: train2_req [03:03] */
#define DSC2B1_SM_CTRL2_TRAIN2_REQ_MASK                            0x0008
#define DSC2B1_SM_CTRL2_TRAIN2_REQ_ALIGN                           0
#define DSC2B1_SM_CTRL2_TRAIN2_REQ_BITS                            1
#define DSC2B1_SM_CTRL2_TRAIN2_REQ_SHIFT                           3

/* Dsc2b1 :: sm_ctrl2 :: train1_req [02:02] */
#define DSC2B1_SM_CTRL2_TRAIN1_REQ_MASK                            0x0004
#define DSC2B1_SM_CTRL2_TRAIN1_REQ_ALIGN                           0
#define DSC2B1_SM_CTRL2_TRAIN1_REQ_BITS                            1
#define DSC2B1_SM_CTRL2_TRAIN1_REQ_SHIFT                           2

/* Dsc2b1 :: sm_ctrl2 :: soft_ack [01:01] */
#define DSC2B1_SM_CTRL2_SOFT_ACK_MASK                              0x0002
#define DSC2B1_SM_CTRL2_SOFT_ACK_ALIGN                             0
#define DSC2B1_SM_CTRL2_SOFT_ACK_BITS                              1
#define DSC2B1_SM_CTRL2_SOFT_ACK_SHIFT                             1

/* Dsc2b1 :: sm_ctrl2 :: train_mode_en [00:00] */
#define DSC2B1_SM_CTRL2_TRAIN_MODE_EN_MASK                         0x0001
#define DSC2B1_SM_CTRL2_TRAIN_MODE_EN_ALIGN                        0
#define DSC2B1_SM_CTRL2_TRAIN_MODE_EN_BITS                         1
#define DSC2B1_SM_CTRL2_TRAIN_MODE_EN_SHIFT                        0


/****************************************************************************
 * Dsc2b1 :: sm_ctrl3
 ***************************************************************************/
/* Dsc2b1 :: sm_ctrl3 :: reserved_for_eco0 [15:15] */
#define DSC2B1_SM_CTRL3_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2B1_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B1_SM_CTRL3_RESERVED_FOR_ECO0_BITS                     1
#define DSC2B1_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2b1 :: sm_ctrl3 :: cdrbr_bwsel_prop_acqcdr [14:12] */
#define DSC2B1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_MASK               0x7000
#define DSC2B1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_ALIGN              0
#define DSC2B1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_BITS               3
#define DSC2B1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_SHIFT              12

/* Dsc2b1 :: sm_ctrl3 :: dfe_gain_acq2 [11:10] */
#define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ2_MASK                         0x0c00
#define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN                        0
#define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ2_BITS                         2
#define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT                        10

/* Dsc2b1 :: sm_ctrl3 :: dfe_gain_acq1 [09:08] */
#define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ1_MASK                         0x0300
#define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN                        0
#define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ1_BITS                         2
#define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT                        8

/* Dsc2b1 :: sm_ctrl3 :: vga_gain_acq2 [07:06] */
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ2_MASK                         0x00c0
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN                        0
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ2_BITS                         2
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT                        6

/* Dsc2b1 :: sm_ctrl3 :: vga_gain_acq1 [05:04] */
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ1_MASK                         0x0030
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN                        0
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ1_BITS                         2
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT                        4

/* Dsc2b1 :: sm_ctrl3 :: vga_gain_acqcdr [03:02] */
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQCDR_MASK                       0x000c
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN                      0
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQCDR_BITS                       2
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT                      2

/* Dsc2b1 :: sm_ctrl3 :: vga_gain_acqvga [01:00] */
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQVGA_MASK                       0x0003
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN                      0
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQVGA_BITS                       2
#define DSC2B1_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT                      0


/****************************************************************************
 * Dsc2b1 :: sm_ctrl4
 ***************************************************************************/
/* Dsc2b1 :: sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */
#define DSC2B1_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK             0xc000
#define DSC2B1_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN            0
#define DSC2B1_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS             2
#define DSC2B1_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT            14

/* Dsc2b1 :: sm_ctrl4 :: cdros45_bwsel_integ_offset [13:12] */
#define DSC2B1_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_MASK            0x3000
#define DSC2B1_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_ALIGN           0
#define DSC2B1_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_BITS            2
#define DSC2B1_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_SHIFT           12

/* Dsc2b1 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq2 [11:10] */
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_MASK                0x0c00
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_ALIGN               0
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_BITS                2
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_SHIFT               10

/* Dsc2b1 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq1 [09:08] */
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_MASK                0x0300
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_ALIGN               0
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_BITS                2
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_SHIFT               8

/* Dsc2b1 :: sm_ctrl4 :: cdrbr_bwsel_integ_acqcdr [07:06] */
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_MASK              0x00c0
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN             0
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_BITS              2
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT             6

/* Dsc2b1 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq2 [05:03] */
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_MASK                 0x0038
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_ALIGN                0
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_BITS                 3
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_SHIFT                3

/* Dsc2b1 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq1 [02:00] */
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_MASK                 0x0007
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_ALIGN                0
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_BITS                 3
#define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_SHIFT                0


/****************************************************************************
 * Dsc2b1 :: sm_ctrl5
 ***************************************************************************/
/* Dsc2b1 :: sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [15:12] */
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK              0xf000
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN             0
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS              4
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT             12

/* Dsc2b1 :: sm_ctrl5 :: cdros_bwsel_integ_acqcdr [11:08] */
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK              0x0f00
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN             0
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS              4
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT             8

/* Dsc2b1 :: sm_ctrl5 :: cdros_bwsel_prop_acq1_2 [07:04] */
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_MASK               0x00f0
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_ALIGN              0
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_BITS               4
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_SHIFT              4

/* Dsc2b1 :: sm_ctrl5 :: cdros_bwsel_prop_acqcdr [03:00] */
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_MASK               0x000f
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_ALIGN              0
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_BITS               4
#define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_SHIFT              0


/****************************************************************************
 * Dsc2b1 :: sm_ctrl6
 ***************************************************************************/
/* Dsc2b1 :: sm_ctrl6 :: reserved_for_eco0 [15:13] */
#define DSC2B1_SM_CTRL6_RESERVED_FOR_ECO0_MASK                     0xe000
#define DSC2B1_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B1_SM_CTRL6_RESERVED_FOR_ECO0_BITS                     3
#define DSC2B1_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT                    13

/* Dsc2b1 :: sm_ctrl6 :: cdrbr_bwsel_integ_acqphase [12:11] */
#define DSC2B1_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_MASK            0x1800
#define DSC2B1_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN           0
#define DSC2B1_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_BITS            2
#define DSC2B1_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT           11

/* Dsc2b1 :: sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [10:08] */
#define DSC2B1_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK             0x0700
#define DSC2B1_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN            0
#define DSC2B1_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS             3
#define DSC2B1_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT            8

/* Dsc2b1 :: sm_ctrl6 :: cdros_bwsel_integ_acqvga [07:04] */
#define DSC2B1_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_MASK              0x00f0
#define DSC2B1_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_ALIGN             0
#define DSC2B1_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_BITS              4
#define DSC2B1_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_SHIFT             4

/* Dsc2b1 :: sm_ctrl6 :: cdros_bwsel_prop_acqvga [03:00] */
#define DSC2B1_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_MASK               0x000f
#define DSC2B1_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_ALIGN              0
#define DSC2B1_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_BITS               4
#define DSC2B1_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_SHIFT              0


/****************************************************************************
 * Dsc2b1 :: sm_ctrl7
 ***************************************************************************/
/* Dsc2b1 :: sm_ctrl7 :: reserved_for_eco0 [15:15] */
#define DSC2B1_SM_CTRL7_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2B1_SM_CTRL7_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B1_SM_CTRL7_RESERVED_FOR_ECO0_BITS                     1
#define DSC2B1_SM_CTRL7_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2b1 :: sm_ctrl7 :: pf_ctrl_br_offset [14:12] */
#define DSC2B1_SM_CTRL7_PF_CTRL_BR_OFFSET_MASK                     0x7000
#define DSC2B1_SM_CTRL7_PF_CTRL_BR_OFFSET_ALIGN                    0
#define DSC2B1_SM_CTRL7_PF_CTRL_BR_OFFSET_BITS                     3
#define DSC2B1_SM_CTRL7_PF_CTRL_BR_OFFSET_SHIFT                    12

/* Dsc2b1 :: sm_ctrl7 :: pf_ctrl_osx1_offset [11:09] */
#define DSC2B1_SM_CTRL7_PF_CTRL_OSX1_OFFSET_MASK                   0x0e00
#define DSC2B1_SM_CTRL7_PF_CTRL_OSX1_OFFSET_ALIGN                  0
#define DSC2B1_SM_CTRL7_PF_CTRL_OSX1_OFFSET_BITS                   3
#define DSC2B1_SM_CTRL7_PF_CTRL_OSX1_OFFSET_SHIFT                  9

/* Dsc2b1 :: sm_ctrl7 :: pf_ctrl_osx2_offset [08:06] */
#define DSC2B1_SM_CTRL7_PF_CTRL_OSX2_OFFSET_MASK                   0x01c0
#define DSC2B1_SM_CTRL7_PF_CTRL_OSX2_OFFSET_ALIGN                  0
#define DSC2B1_SM_CTRL7_PF_CTRL_OSX2_OFFSET_BITS                   3
#define DSC2B1_SM_CTRL7_PF_CTRL_OSX2_OFFSET_SHIFT                  6

/* Dsc2b1 :: sm_ctrl7 :: pf_ctrl_br_init [05:03] */
#define DSC2B1_SM_CTRL7_PF_CTRL_BR_INIT_MASK                       0x0038
#define DSC2B1_SM_CTRL7_PF_CTRL_BR_INIT_ALIGN                      0
#define DSC2B1_SM_CTRL7_PF_CTRL_BR_INIT_BITS                       3
#define DSC2B1_SM_CTRL7_PF_CTRL_BR_INIT_SHIFT                      3

/* Dsc2b1 :: sm_ctrl7 :: pf_ctrl_os_init [02:00] */
#define DSC2B1_SM_CTRL7_PF_CTRL_OS_INIT_MASK                       0x0007
#define DSC2B1_SM_CTRL7_PF_CTRL_OS_INIT_ALIGN                      0
#define DSC2B1_SM_CTRL7_PF_CTRL_OS_INIT_BITS                       3
#define DSC2B1_SM_CTRL7_PF_CTRL_OS_INIT_SHIFT                      0


/****************************************************************************
 * Dsc2b1 :: sm_ctrl8
 ***************************************************************************/
/* Dsc2b1 :: sm_ctrl8 :: reserved_for_eco0 [15:10] */
#define DSC2B1_SM_CTRL8_RESERVED_FOR_ECO0_MASK                     0xfc00
#define DSC2B1_SM_CTRL8_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B1_SM_CTRL8_RESERVED_FOR_ECO0_BITS                     6
#define DSC2B1_SM_CTRL8_RESERVED_FOR_ECO0_SHIFT                    10

/* Dsc2b1 :: sm_ctrl8 :: vga_max_val [09:05] */
#define DSC2B1_SM_CTRL8_VGA_MAX_VAL_MASK                           0x03e0
#define DSC2B1_SM_CTRL8_VGA_MAX_VAL_ALIGN                          0
#define DSC2B1_SM_CTRL8_VGA_MAX_VAL_BITS                           5
#define DSC2B1_SM_CTRL8_VGA_MAX_VAL_SHIFT                          5

/* Dsc2b1 :: sm_ctrl8 :: vga_min_val [04:00] */
#define DSC2B1_SM_CTRL8_VGA_MIN_VAL_MASK                           0x001f
#define DSC2B1_SM_CTRL8_VGA_MIN_VAL_ALIGN                          0
#define DSC2B1_SM_CTRL8_VGA_MIN_VAL_BITS                           5
#define DSC2B1_SM_CTRL8_VGA_MIN_VAL_SHIFT                          0


/****************************************************************************
 * Dsc2b1 :: sm_ctrl9
 ***************************************************************************/
/* Dsc2b1 :: sm_ctrl9 :: reserved_for_eco0 [15:12] */
#define DSC2B1_SM_CTRL9_RESERVED_FOR_ECO0_MASK                     0xf000
#define DSC2B1_SM_CTRL9_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B1_SM_CTRL9_RESERVED_FOR_ECO0_BITS                     4
#define DSC2B1_SM_CTRL9_RESERVED_FOR_ECO0_SHIFT                    12

/* Dsc2b1 :: sm_ctrl9 :: dfe_max_val [11:06] */
#define DSC2B1_SM_CTRL9_DFE_MAX_VAL_MASK                           0x0fc0
#define DSC2B1_SM_CTRL9_DFE_MAX_VAL_ALIGN                          0
#define DSC2B1_SM_CTRL9_DFE_MAX_VAL_BITS                           6
#define DSC2B1_SM_CTRL9_DFE_MAX_VAL_SHIFT                          6

/* Dsc2b1 :: sm_ctrl9 :: dfe_min_val [05:00] */
#define DSC2B1_SM_CTRL9_DFE_MIN_VAL_MASK                           0x003f
#define DSC2B1_SM_CTRL9_DFE_MIN_VAL_ALIGN                          0
#define DSC2B1_SM_CTRL9_DFE_MIN_VAL_BITS                           6
#define DSC2B1_SM_CTRL9_DFE_MIN_VAL_SHIFT                          0


/****************************************************************************
 * Dsc2b1 :: sm_ctrl10
 ***************************************************************************/
/* Dsc2b1 :: sm_ctrl10 :: reserved_for_eco0 [15:14] */
#define DSC2B1_SM_CTRL10_RESERVED_FOR_ECO0_MASK                    0xc000
#define DSC2B1_SM_CTRL10_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2B1_SM_CTRL10_RESERVED_FOR_ECO0_BITS                    2
#define DSC2B1_SM_CTRL10_RESERVED_FOR_ECO0_SHIFT                   14

/* Dsc2b1 :: sm_ctrl10 :: br_pf_tap_en [13:07] */
#define DSC2B1_SM_CTRL10_BR_PF_TAP_EN_MASK                         0x3f80
#define DSC2B1_SM_CTRL10_BR_PF_TAP_EN_ALIGN                        0
#define DSC2B1_SM_CTRL10_BR_PF_TAP_EN_BITS                         7
#define DSC2B1_SM_CTRL10_BR_PF_TAP_EN_SHIFT                        7

/* Dsc2b1 :: sm_ctrl10 :: osx1_pf_tap_en [06:00] */
#define DSC2B1_SM_CTRL10_OSX1_PF_TAP_EN_MASK                       0x007f
#define DSC2B1_SM_CTRL10_OSX1_PF_TAP_EN_ALIGN                      0
#define DSC2B1_SM_CTRL10_OSX1_PF_TAP_EN_BITS                       7
#define DSC2B1_SM_CTRL10_OSX1_PF_TAP_EN_SHIFT                      0


/****************************************************************************
 * Dsc2b1 :: sm_ctrl11
 ***************************************************************************/
/* Dsc2b1 :: sm_ctrl11 :: reserved_for_eco0 [15:15] */
#define DSC2B1_SM_CTRL11_RESERVED_FOR_ECO0_MASK                    0x8000
#define DSC2B1_SM_CTRL11_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2B1_SM_CTRL11_RESERVED_FOR_ECO0_BITS                    1
#define DSC2B1_SM_CTRL11_RESERVED_FOR_ECO0_SHIFT                   15

/* Dsc2b1 :: sm_ctrl11 :: msr_br_vga_timeout [14:10] */
#define DSC2B1_SM_CTRL11_MSR_BR_VGA_TIMEOUT_MASK                   0x7c00
#define DSC2B1_SM_CTRL11_MSR_BR_VGA_TIMEOUT_ALIGN                  0
#define DSC2B1_SM_CTRL11_MSR_BR_VGA_TIMEOUT_BITS                   5
#define DSC2B1_SM_CTRL11_MSR_BR_VGA_TIMEOUT_SHIFT                  10

/* Dsc2b1 :: sm_ctrl11 :: hysteresis_timeout [09:05] */
#define DSC2B1_SM_CTRL11_HYSTERESIS_TIMEOUT_MASK                   0x03e0
#define DSC2B1_SM_CTRL11_HYSTERESIS_TIMEOUT_ALIGN                  0
#define DSC2B1_SM_CTRL11_HYSTERESIS_TIMEOUT_BITS                   5
#define DSC2B1_SM_CTRL11_HYSTERESIS_TIMEOUT_SHIFT                  5

/* Dsc2b1 :: sm_ctrl11 :: msr_postc_timeout [04:00] */
#define DSC2B1_SM_CTRL11_MSR_POSTC_TIMEOUT_MASK                    0x001f
#define DSC2B1_SM_CTRL11_MSR_POSTC_TIMEOUT_ALIGN                   0
#define DSC2B1_SM_CTRL11_MSR_POSTC_TIMEOUT_BITS                    5
#define DSC2B1_SM_CTRL11_MSR_POSTC_TIMEOUT_SHIFT                   0


/****************************************************************************
 * Dsc2b1 :: sm_ctrl12
 ***************************************************************************/
/* Dsc2b1 :: sm_ctrl12 :: reserved_for_eco0 [15:14] */
#define DSC2B1_SM_CTRL12_RESERVED_FOR_ECO0_MASK                    0xc000
#define DSC2B1_SM_CTRL12_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2B1_SM_CTRL12_RESERVED_FOR_ECO0_BITS                    2
#define DSC2B1_SM_CTRL12_RESERVED_FOR_ECO0_SHIFT                   14

/* Dsc2b1 :: sm_ctrl12 :: br_vga_lms_gain [13:12] */
#define DSC2B1_SM_CTRL12_BR_VGA_LMS_GAIN_MASK                      0x3000
#define DSC2B1_SM_CTRL12_BR_VGA_LMS_GAIN_ALIGN                     0
#define DSC2B1_SM_CTRL12_BR_VGA_LMS_GAIN_BITS                      2
#define DSC2B1_SM_CTRL12_BR_VGA_LMS_GAIN_SHIFT                     12

/* Dsc2b1 :: sm_ctrl12 :: postc_dfe_lms_gain [11:10] */
#define DSC2B1_SM_CTRL12_POSTC_DFE_LMS_GAIN_MASK                   0x0c00
#define DSC2B1_SM_CTRL12_POSTC_DFE_LMS_GAIN_ALIGN                  0
#define DSC2B1_SM_CTRL12_POSTC_DFE_LMS_GAIN_BITS                   2
#define DSC2B1_SM_CTRL12_POSTC_DFE_LMS_GAIN_SHIFT                  10

/* Dsc2b1 :: sm_ctrl12 :: cdr_phase_inversion_timeout [09:05] */
#define DSC2B1_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_MASK          0x03e0
#define DSC2B1_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_ALIGN         0
#define DSC2B1_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_BITS          5
#define DSC2B1_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_SHIFT         5

/* Dsc2b1 :: sm_ctrl12 :: msr_pf_timeout [04:00] */
#define DSC2B1_SM_CTRL12_MSR_PF_TIMEOUT_MASK                       0x001f
#define DSC2B1_SM_CTRL12_MSR_PF_TIMEOUT_ALIGN                      0
#define DSC2B1_SM_CTRL12_MSR_PF_TIMEOUT_BITS                       5
#define DSC2B1_SM_CTRL12_MSR_PF_TIMEOUT_SHIFT                      0


/****************************************************************************
 * Dsc2b1 :: dsc_diag_ctrl0
 ***************************************************************************/
/* Dsc2b1 :: dsc_diag_ctrl0 :: reserved_for_eco0 [15:11] */
#define DSC2B1_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_MASK               0xf800
#define DSC2B1_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC2B1_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_BITS               5
#define DSC2B1_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_SHIFT              11

/* Dsc2b1 :: dsc_diag_ctrl0 :: voffset [10:07] */
#define DSC2B1_DSC_DIAG_CTRL0_VOFFSET_MASK                         0x0780
#define DSC2B1_DSC_DIAG_CTRL0_VOFFSET_ALIGN                        0
#define DSC2B1_DSC_DIAG_CTRL0_VOFFSET_BITS                         4
#define DSC2B1_DSC_DIAG_CTRL0_VOFFSET_SHIFT                        7

/* Dsc2b1 :: dsc_diag_ctrl0 :: hoffset [06:01] */
#define DSC2B1_DSC_DIAG_CTRL0_HOFFSET_MASK                         0x007e
#define DSC2B1_DSC_DIAG_CTRL0_HOFFSET_ALIGN                        0
#define DSC2B1_DSC_DIAG_CTRL0_HOFFSET_BITS                         6
#define DSC2B1_DSC_DIAG_CTRL0_HOFFSET_SHIFT                        1

/* Dsc2b1 :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */
#define DSC2B1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK                  0x0001
#define DSC2B1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN                 0
#define DSC2B1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS                  1
#define DSC2B1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT                 0


/****************************************************************************
 * Dsc2b1 :: dsc_misc_ctrl0
 ***************************************************************************/
/* Dsc2b1 :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */
#define DSC2B1_DSC_MISC_CTRL0_RXSEQSTART_MASK                      0x8000
#define DSC2B1_DSC_MISC_CTRL0_RXSEQSTART_ALIGN                     0
#define DSC2B1_DSC_MISC_CTRL0_RXSEQSTART_BITS                      1
#define DSC2B1_DSC_MISC_CTRL0_RXSEQSTART_SHIFT                     15

/* Dsc2b1 :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */
#define DSC2B1_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK                  0x4000
#define DSC2B1_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN                 0
#define DSC2B1_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS                  1
#define DSC2B1_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT                 14

/* Dsc2b1 :: dsc_misc_ctrl0 :: enable_acor_picw [13:13] */
#define DSC2B1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_MASK                0x2000
#define DSC2B1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_ALIGN               0
#define DSC2B1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_BITS                1
#define DSC2B1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_SHIFT               13

/* Dsc2b1 :: dsc_misc_ctrl0 :: reserved_for_eco0 [12:10] */
#define DSC2B1_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_MASK               0x1c00
#define DSC2B1_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC2B1_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_BITS               3
#define DSC2B1_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_SHIFT              10

/* Dsc2b1 :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */
#define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK                 0x0200
#define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN                0
#define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS                 1
#define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT                9

/* Dsc2b1 :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */
#define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK             0x0100
#define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN            0
#define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS             1
#define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT            8

/* Dsc2b1 :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */
#define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK                  0x0080
#define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN                 0
#define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS                  1
#define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT                 7

/* Dsc2b1 :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */
#define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK              0x0070
#define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN             0
#define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS              3
#define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT             4

/* Dsc2b1 :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */
#define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK                    0x000f
#define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN                   0
#define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS                    4
#define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT                   0
#define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_Off                     0
#define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data                1
#define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1             2
#define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1           3
#define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco             4
#define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg                 6
#define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr             7
#define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd           8
#define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe            9
#define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum               10


/****************************************************************************
 * Hypercore_USER_Dsc2b2
 ***************************************************************************/
/****************************************************************************
 * Dsc2b2 :: sm_ctrl0
 ***************************************************************************/
/* Dsc2b2 :: sm_ctrl0 :: reserved_for_eco0 [15:15] */
#define DSC2B2_SM_CTRL0_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2B2_SM_CTRL0_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B2_SM_CTRL0_RESERVED_FOR_ECO0_BITS                     1
#define DSC2B2_SM_CTRL0_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2b2 :: sm_ctrl0 :: bypass_tx_postc_cal [14:14] */
#define DSC2B2_SM_CTRL0_BYPASS_TX_POSTC_CAL_MASK                   0x4000
#define DSC2B2_SM_CTRL0_BYPASS_TX_POSTC_CAL_ALIGN                  0
#define DSC2B2_SM_CTRL0_BYPASS_TX_POSTC_CAL_BITS                   1
#define DSC2B2_SM_CTRL0_BYPASS_TX_POSTC_CAL_SHIFT                  14

/* Dsc2b2 :: sm_ctrl0 :: bypass_br_vga [13:13] */
#define DSC2B2_SM_CTRL0_BYPASS_BR_VGA_MASK                         0x2000
#define DSC2B2_SM_CTRL0_BYPASS_BR_VGA_ALIGN                        0
#define DSC2B2_SM_CTRL0_BYPASS_BR_VGA_BITS                         1
#define DSC2B2_SM_CTRL0_BYPASS_BR_VGA_SHIFT                        13

/* Dsc2b2 :: sm_ctrl0 :: postc_metric_ctrl [12:12] */
#define DSC2B2_SM_CTRL0_POSTC_METRIC_CTRL_MASK                     0x1000
#define DSC2B2_SM_CTRL0_POSTC_METRIC_CTRL_ALIGN                    0
#define DSC2B2_SM_CTRL0_POSTC_METRIC_CTRL_BITS                     1
#define DSC2B2_SM_CTRL0_POSTC_METRIC_CTRL_SHIFT                    12

/* Dsc2b2 :: sm_ctrl0 :: hysteresis_en [11:11] */
#define DSC2B2_SM_CTRL0_HYSTERESIS_EN_MASK                         0x0800
#define DSC2B2_SM_CTRL0_HYSTERESIS_EN_ALIGN                        0
#define DSC2B2_SM_CTRL0_HYSTERESIS_EN_BITS                         1
#define DSC2B2_SM_CTRL0_HYSTERESIS_EN_SHIFT                        11

/* Dsc2b2 :: sm_ctrl0 :: slicer_cal_linear_srch [10:10] */
#define DSC2B2_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_MASK                0x0400
#define DSC2B2_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_ALIGN               0
#define DSC2B2_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_BITS                1
#define DSC2B2_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_SHIFT               10

/* Dsc2b2 :: sm_ctrl0 :: bypass_br_pf_cal [09:09] */
#define DSC2B2_SM_CTRL0_BYPASS_BR_PF_CAL_MASK                      0x0200
#define DSC2B2_SM_CTRL0_BYPASS_BR_PF_CAL_ALIGN                     0
#define DSC2B2_SM_CTRL0_BYPASS_BR_PF_CAL_BITS                      1
#define DSC2B2_SM_CTRL0_BYPASS_BR_PF_CAL_SHIFT                     9

/* Dsc2b2 :: sm_ctrl0 :: bypass_osx2_pf_cal [08:08] */
#define DSC2B2_SM_CTRL0_BYPASS_OSX2_PF_CAL_MASK                    0x0100
#define DSC2B2_SM_CTRL0_BYPASS_OSX2_PF_CAL_ALIGN                   0
#define DSC2B2_SM_CTRL0_BYPASS_OSX2_PF_CAL_BITS                    1
#define DSC2B2_SM_CTRL0_BYPASS_OSX2_PF_CAL_SHIFT                   8

/* Dsc2b2 :: sm_ctrl0 :: bypass_osx1_pf_cal [07:07] */
#define DSC2B2_SM_CTRL0_BYPASS_OSX1_PF_CAL_MASK                    0x0080
#define DSC2B2_SM_CTRL0_BYPASS_OSX1_PF_CAL_ALIGN                   0
#define DSC2B2_SM_CTRL0_BYPASS_OSX1_PF_CAL_BITS                    1
#define DSC2B2_SM_CTRL0_BYPASS_OSX1_PF_CAL_SHIFT                   7

/* Dsc2b2 :: sm_ctrl0 :: bypass_data_slicer_recal [06:06] */
#define DSC2B2_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_MASK              0x0040
#define DSC2B2_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_ALIGN             0
#define DSC2B2_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_BITS              1
#define DSC2B2_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_SHIFT             6

/* Dsc2b2 :: sm_ctrl0 :: bypass_osx45_slicer_cal [05:05] */
#define DSC2B2_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_MASK               0x0020
#define DSC2B2_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_ALIGN              0
#define DSC2B2_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_BITS               1
#define DSC2B2_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_SHIFT              5

/* Dsc2b2 :: sm_ctrl0 :: bypass_phase_slicer_cal [04:04] */
#define DSC2B2_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_MASK               0x0010
#define DSC2B2_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_ALIGN              0
#define DSC2B2_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_BITS               1
#define DSC2B2_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_SHIFT              4

/* Dsc2b2 :: sm_ctrl0 :: bypass_br_data_slicer_cal [03:03] */
#define DSC2B2_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_MASK             0x0008
#define DSC2B2_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_ALIGN            0
#define DSC2B2_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_BITS             1
#define DSC2B2_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_SHIFT            3

/* Dsc2b2 :: sm_ctrl0 :: bypass_os_data_slicer_cal [02:02] */
#define DSC2B2_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_MASK             0x0004
#define DSC2B2_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_ALIGN            0
#define DSC2B2_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_BITS             1
#define DSC2B2_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_SHIFT            2

/* Dsc2b2 :: sm_ctrl0 :: restart_tuning [01:01] */
#define DSC2B2_SM_CTRL0_RESTART_TUNING_MASK                        0x0002
#define DSC2B2_SM_CTRL0_RESTART_TUNING_ALIGN                       0
#define DSC2B2_SM_CTRL0_RESTART_TUNING_BITS                        1
#define DSC2B2_SM_CTRL0_RESTART_TUNING_SHIFT                       1

/* Dsc2b2 :: sm_ctrl0 :: tuning_sm_en [00:00] */
#define DSC2B2_SM_CTRL0_TUNING_SM_EN_MASK                          0x0001
#define DSC2B2_SM_CTRL0_TUNING_SM_EN_ALIGN                         0
#define DSC2B2_SM_CTRL0_TUNING_SM_EN_BITS                          1
#define DSC2B2_SM_CTRL0_TUNING_SM_EN_SHIFT                         0


/****************************************************************************
 * Dsc2b2 :: sm_ctrl1
 ***************************************************************************/
/* Dsc2b2 :: sm_ctrl1 :: fast_timer [15:15] */
#define DSC2B2_SM_CTRL1_FAST_TIMER_MASK                            0x8000
#define DSC2B2_SM_CTRL1_FAST_TIMER_ALIGN                           0
#define DSC2B2_SM_CTRL1_FAST_TIMER_BITS                            1
#define DSC2B2_SM_CTRL1_FAST_TIMER_SHIFT                           15

/* Dsc2b2 :: sm_ctrl1 :: acq2_timeout [14:10] */
#define DSC2B2_SM_CTRL1_ACQ2_TIMEOUT_MASK                          0x7c00
#define DSC2B2_SM_CTRL1_ACQ2_TIMEOUT_ALIGN                         0
#define DSC2B2_SM_CTRL1_ACQ2_TIMEOUT_BITS                          5
#define DSC2B2_SM_CTRL1_ACQ2_TIMEOUT_SHIFT                         10

/* Dsc2b2 :: sm_ctrl1 :: acq1_timeout [09:05] */
#define DSC2B2_SM_CTRL1_ACQ1_TIMEOUT_MASK                          0x03e0
#define DSC2B2_SM_CTRL1_ACQ1_TIMEOUT_ALIGN                         0
#define DSC2B2_SM_CTRL1_ACQ1_TIMEOUT_BITS                          5
#define DSC2B2_SM_CTRL1_ACQ1_TIMEOUT_SHIFT                         5

/* Dsc2b2 :: sm_ctrl1 :: acqcdr_timeout [04:00] */
#define DSC2B2_SM_CTRL1_ACQCDR_TIMEOUT_MASK                        0x001f
#define DSC2B2_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN                       0
#define DSC2B2_SM_CTRL1_ACQCDR_TIMEOUT_BITS                        5
#define DSC2B2_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT                       0


/****************************************************************************
 * Dsc2b2 :: sm_ctrl2
 ***************************************************************************/
/* Dsc2b2 :: sm_ctrl2 :: acqvga_timeout [15:11] */
#define DSC2B2_SM_CTRL2_ACQVGA_TIMEOUT_MASK                        0xf800
#define DSC2B2_SM_CTRL2_ACQVGA_TIMEOUT_ALIGN                       0
#define DSC2B2_SM_CTRL2_ACQVGA_TIMEOUT_BITS                        5
#define DSC2B2_SM_CTRL2_ACQVGA_TIMEOUT_SHIFT                       11

/* Dsc2b2 :: sm_ctrl2 :: bypass_os_integ_xfer [10:10] */
#define DSC2B2_SM_CTRL2_BYPASS_OS_INTEG_XFER_MASK                  0x0400
#define DSC2B2_SM_CTRL2_BYPASS_OS_INTEG_XFER_ALIGN                 0
#define DSC2B2_SM_CTRL2_BYPASS_OS_INTEG_XFER_BITS                  1
#define DSC2B2_SM_CTRL2_BYPASS_OS_INTEG_XFER_SHIFT                 10

/* Dsc2b2 :: sm_ctrl2 :: vga_frzval [09:09] */
#define DSC2B2_SM_CTRL2_VGA_FRZVAL_MASK                            0x0200
#define DSC2B2_SM_CTRL2_VGA_FRZVAL_ALIGN                           0
#define DSC2B2_SM_CTRL2_VGA_FRZVAL_BITS                            1
#define DSC2B2_SM_CTRL2_VGA_FRZVAL_SHIFT                           9

/* Dsc2b2 :: sm_ctrl2 :: vga_frcfrz [08:08] */
#define DSC2B2_SM_CTRL2_VGA_FRCFRZ_MASK                            0x0100
#define DSC2B2_SM_CTRL2_VGA_FRCFRZ_ALIGN                           0
#define DSC2B2_SM_CTRL2_VGA_FRCFRZ_BITS                            1
#define DSC2B2_SM_CTRL2_VGA_FRCFRZ_SHIFT                           8

/* Dsc2b2 :: sm_ctrl2 :: dfe_frzval [07:07] */
#define DSC2B2_SM_CTRL2_DFE_FRZVAL_MASK                            0x0080
#define DSC2B2_SM_CTRL2_DFE_FRZVAL_ALIGN                           0
#define DSC2B2_SM_CTRL2_DFE_FRZVAL_BITS                            1
#define DSC2B2_SM_CTRL2_DFE_FRZVAL_SHIFT                           7

/* Dsc2b2 :: sm_ctrl2 :: dfe_frcfrz [06:06] */
#define DSC2B2_SM_CTRL2_DFE_FRCFRZ_MASK                            0x0040
#define DSC2B2_SM_CTRL2_DFE_FRCFRZ_ALIGN                           0
#define DSC2B2_SM_CTRL2_DFE_FRCFRZ_BITS                            1
#define DSC2B2_SM_CTRL2_DFE_FRCFRZ_SHIFT                           6

/* Dsc2b2 :: sm_ctrl2 :: dsc_clr_val [05:05] */
#define DSC2B2_SM_CTRL2_DSC_CLR_VAL_MASK                           0x0020
#define DSC2B2_SM_CTRL2_DSC_CLR_VAL_ALIGN                          0
#define DSC2B2_SM_CTRL2_DSC_CLR_VAL_BITS                           1
#define DSC2B2_SM_CTRL2_DSC_CLR_VAL_SHIFT                          5

/* Dsc2b2 :: sm_ctrl2 :: dsc_clr_frc [04:04] */
#define DSC2B2_SM_CTRL2_DSC_CLR_FRC_MASK                           0x0010
#define DSC2B2_SM_CTRL2_DSC_CLR_FRC_ALIGN                          0
#define DSC2B2_SM_CTRL2_DSC_CLR_FRC_BITS                           1
#define DSC2B2_SM_CTRL2_DSC_CLR_FRC_SHIFT                          4

/* Dsc2b2 :: sm_ctrl2 :: train2_req [03:03] */
#define DSC2B2_SM_CTRL2_TRAIN2_REQ_MASK                            0x0008
#define DSC2B2_SM_CTRL2_TRAIN2_REQ_ALIGN                           0
#define DSC2B2_SM_CTRL2_TRAIN2_REQ_BITS                            1
#define DSC2B2_SM_CTRL2_TRAIN2_REQ_SHIFT                           3

/* Dsc2b2 :: sm_ctrl2 :: train1_req [02:02] */
#define DSC2B2_SM_CTRL2_TRAIN1_REQ_MASK                            0x0004
#define DSC2B2_SM_CTRL2_TRAIN1_REQ_ALIGN                           0
#define DSC2B2_SM_CTRL2_TRAIN1_REQ_BITS                            1
#define DSC2B2_SM_CTRL2_TRAIN1_REQ_SHIFT                           2

/* Dsc2b2 :: sm_ctrl2 :: soft_ack [01:01] */
#define DSC2B2_SM_CTRL2_SOFT_ACK_MASK                              0x0002
#define DSC2B2_SM_CTRL2_SOFT_ACK_ALIGN                             0
#define DSC2B2_SM_CTRL2_SOFT_ACK_BITS                              1
#define DSC2B2_SM_CTRL2_SOFT_ACK_SHIFT                             1

/* Dsc2b2 :: sm_ctrl2 :: train_mode_en [00:00] */
#define DSC2B2_SM_CTRL2_TRAIN_MODE_EN_MASK                         0x0001
#define DSC2B2_SM_CTRL2_TRAIN_MODE_EN_ALIGN                        0
#define DSC2B2_SM_CTRL2_TRAIN_MODE_EN_BITS                         1
#define DSC2B2_SM_CTRL2_TRAIN_MODE_EN_SHIFT                        0


/****************************************************************************
 * Dsc2b2 :: sm_ctrl3
 ***************************************************************************/
/* Dsc2b2 :: sm_ctrl3 :: reserved_for_eco0 [15:15] */
#define DSC2B2_SM_CTRL3_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2B2_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B2_SM_CTRL3_RESERVED_FOR_ECO0_BITS                     1
#define DSC2B2_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2b2 :: sm_ctrl3 :: cdrbr_bwsel_prop_acqcdr [14:12] */
#define DSC2B2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_MASK               0x7000
#define DSC2B2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_ALIGN              0
#define DSC2B2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_BITS               3
#define DSC2B2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_SHIFT              12

/* Dsc2b2 :: sm_ctrl3 :: dfe_gain_acq2 [11:10] */
#define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ2_MASK                         0x0c00
#define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN                        0
#define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ2_BITS                         2
#define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT                        10

/* Dsc2b2 :: sm_ctrl3 :: dfe_gain_acq1 [09:08] */
#define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ1_MASK                         0x0300
#define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN                        0
#define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ1_BITS                         2
#define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT                        8

/* Dsc2b2 :: sm_ctrl3 :: vga_gain_acq2 [07:06] */
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ2_MASK                         0x00c0
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN                        0
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ2_BITS                         2
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT                        6

/* Dsc2b2 :: sm_ctrl3 :: vga_gain_acq1 [05:04] */
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ1_MASK                         0x0030
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN                        0
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ1_BITS                         2
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT                        4

/* Dsc2b2 :: sm_ctrl3 :: vga_gain_acqcdr [03:02] */
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQCDR_MASK                       0x000c
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN                      0
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQCDR_BITS                       2
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT                      2

/* Dsc2b2 :: sm_ctrl3 :: vga_gain_acqvga [01:00] */
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQVGA_MASK                       0x0003
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN                      0
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQVGA_BITS                       2
#define DSC2B2_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT                      0


/****************************************************************************
 * Dsc2b2 :: sm_ctrl4
 ***************************************************************************/
/* Dsc2b2 :: sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */
#define DSC2B2_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK             0xc000
#define DSC2B2_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN            0
#define DSC2B2_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS             2
#define DSC2B2_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT            14

/* Dsc2b2 :: sm_ctrl4 :: cdros45_bwsel_integ_offset [13:12] */
#define DSC2B2_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_MASK            0x3000
#define DSC2B2_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_ALIGN           0
#define DSC2B2_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_BITS            2
#define DSC2B2_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_SHIFT           12

/* Dsc2b2 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq2 [11:10] */
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_MASK                0x0c00
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_ALIGN               0
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_BITS                2
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_SHIFT               10

/* Dsc2b2 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq1 [09:08] */
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_MASK                0x0300
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_ALIGN               0
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_BITS                2
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_SHIFT               8

/* Dsc2b2 :: sm_ctrl4 :: cdrbr_bwsel_integ_acqcdr [07:06] */
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_MASK              0x00c0
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN             0
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_BITS              2
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT             6

/* Dsc2b2 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq2 [05:03] */
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_MASK                 0x0038
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_ALIGN                0
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_BITS                 3
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_SHIFT                3

/* Dsc2b2 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq1 [02:00] */
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_MASK                 0x0007
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_ALIGN                0
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_BITS                 3
#define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_SHIFT                0


/****************************************************************************
 * Dsc2b2 :: sm_ctrl5
 ***************************************************************************/
/* Dsc2b2 :: sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [15:12] */
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK              0xf000
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN             0
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS              4
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT             12

/* Dsc2b2 :: sm_ctrl5 :: cdros_bwsel_integ_acqcdr [11:08] */
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK              0x0f00
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN             0
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS              4
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT             8

/* Dsc2b2 :: sm_ctrl5 :: cdros_bwsel_prop_acq1_2 [07:04] */
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_MASK               0x00f0
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_ALIGN              0
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_BITS               4
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_SHIFT              4

/* Dsc2b2 :: sm_ctrl5 :: cdros_bwsel_prop_acqcdr [03:00] */
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_MASK               0x000f
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_ALIGN              0
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_BITS               4
#define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_SHIFT              0


/****************************************************************************
 * Dsc2b2 :: sm_ctrl6
 ***************************************************************************/
/* Dsc2b2 :: sm_ctrl6 :: reserved_for_eco0 [15:13] */
#define DSC2B2_SM_CTRL6_RESERVED_FOR_ECO0_MASK                     0xe000
#define DSC2B2_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B2_SM_CTRL6_RESERVED_FOR_ECO0_BITS                     3
#define DSC2B2_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT                    13

/* Dsc2b2 :: sm_ctrl6 :: cdrbr_bwsel_integ_acqphase [12:11] */
#define DSC2B2_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_MASK            0x1800
#define DSC2B2_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN           0
#define DSC2B2_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_BITS            2
#define DSC2B2_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT           11

/* Dsc2b2 :: sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [10:08] */
#define DSC2B2_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK             0x0700
#define DSC2B2_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN            0
#define DSC2B2_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS             3
#define DSC2B2_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT            8

/* Dsc2b2 :: sm_ctrl6 :: cdros_bwsel_integ_acqvga [07:04] */
#define DSC2B2_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_MASK              0x00f0
#define DSC2B2_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_ALIGN             0
#define DSC2B2_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_BITS              4
#define DSC2B2_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_SHIFT             4

/* Dsc2b2 :: sm_ctrl6 :: cdros_bwsel_prop_acqvga [03:00] */
#define DSC2B2_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_MASK               0x000f
#define DSC2B2_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_ALIGN              0
#define DSC2B2_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_BITS               4
#define DSC2B2_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_SHIFT              0


/****************************************************************************
 * Dsc2b2 :: sm_ctrl7
 ***************************************************************************/
/* Dsc2b2 :: sm_ctrl7 :: reserved_for_eco0 [15:15] */
#define DSC2B2_SM_CTRL7_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2B2_SM_CTRL7_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B2_SM_CTRL7_RESERVED_FOR_ECO0_BITS                     1
#define DSC2B2_SM_CTRL7_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2b2 :: sm_ctrl7 :: pf_ctrl_br_offset [14:12] */
#define DSC2B2_SM_CTRL7_PF_CTRL_BR_OFFSET_MASK                     0x7000
#define DSC2B2_SM_CTRL7_PF_CTRL_BR_OFFSET_ALIGN                    0
#define DSC2B2_SM_CTRL7_PF_CTRL_BR_OFFSET_BITS                     3
#define DSC2B2_SM_CTRL7_PF_CTRL_BR_OFFSET_SHIFT                    12

/* Dsc2b2 :: sm_ctrl7 :: pf_ctrl_osx1_offset [11:09] */
#define DSC2B2_SM_CTRL7_PF_CTRL_OSX1_OFFSET_MASK                   0x0e00
#define DSC2B2_SM_CTRL7_PF_CTRL_OSX1_OFFSET_ALIGN                  0
#define DSC2B2_SM_CTRL7_PF_CTRL_OSX1_OFFSET_BITS                   3
#define DSC2B2_SM_CTRL7_PF_CTRL_OSX1_OFFSET_SHIFT                  9

/* Dsc2b2 :: sm_ctrl7 :: pf_ctrl_osx2_offset [08:06] */
#define DSC2B2_SM_CTRL7_PF_CTRL_OSX2_OFFSET_MASK                   0x01c0
#define DSC2B2_SM_CTRL7_PF_CTRL_OSX2_OFFSET_ALIGN                  0
#define DSC2B2_SM_CTRL7_PF_CTRL_OSX2_OFFSET_BITS                   3
#define DSC2B2_SM_CTRL7_PF_CTRL_OSX2_OFFSET_SHIFT                  6

/* Dsc2b2 :: sm_ctrl7 :: pf_ctrl_br_init [05:03] */
#define DSC2B2_SM_CTRL7_PF_CTRL_BR_INIT_MASK                       0x0038
#define DSC2B2_SM_CTRL7_PF_CTRL_BR_INIT_ALIGN                      0
#define DSC2B2_SM_CTRL7_PF_CTRL_BR_INIT_BITS                       3
#define DSC2B2_SM_CTRL7_PF_CTRL_BR_INIT_SHIFT                      3

/* Dsc2b2 :: sm_ctrl7 :: pf_ctrl_os_init [02:00] */
#define DSC2B2_SM_CTRL7_PF_CTRL_OS_INIT_MASK                       0x0007
#define DSC2B2_SM_CTRL7_PF_CTRL_OS_INIT_ALIGN                      0
#define DSC2B2_SM_CTRL7_PF_CTRL_OS_INIT_BITS                       3
#define DSC2B2_SM_CTRL7_PF_CTRL_OS_INIT_SHIFT                      0


/****************************************************************************
 * Dsc2b2 :: sm_ctrl8
 ***************************************************************************/
/* Dsc2b2 :: sm_ctrl8 :: reserved_for_eco0 [15:10] */
#define DSC2B2_SM_CTRL8_RESERVED_FOR_ECO0_MASK                     0xfc00
#define DSC2B2_SM_CTRL8_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B2_SM_CTRL8_RESERVED_FOR_ECO0_BITS                     6
#define DSC2B2_SM_CTRL8_RESERVED_FOR_ECO0_SHIFT                    10

/* Dsc2b2 :: sm_ctrl8 :: vga_max_val [09:05] */
#define DSC2B2_SM_CTRL8_VGA_MAX_VAL_MASK                           0x03e0
#define DSC2B2_SM_CTRL8_VGA_MAX_VAL_ALIGN                          0
#define DSC2B2_SM_CTRL8_VGA_MAX_VAL_BITS                           5
#define DSC2B2_SM_CTRL8_VGA_MAX_VAL_SHIFT                          5

/* Dsc2b2 :: sm_ctrl8 :: vga_min_val [04:00] */
#define DSC2B2_SM_CTRL8_VGA_MIN_VAL_MASK                           0x001f
#define DSC2B2_SM_CTRL8_VGA_MIN_VAL_ALIGN                          0
#define DSC2B2_SM_CTRL8_VGA_MIN_VAL_BITS                           5
#define DSC2B2_SM_CTRL8_VGA_MIN_VAL_SHIFT                          0


/****************************************************************************
 * Dsc2b2 :: sm_ctrl9
 ***************************************************************************/
/* Dsc2b2 :: sm_ctrl9 :: reserved_for_eco0 [15:12] */
#define DSC2B2_SM_CTRL9_RESERVED_FOR_ECO0_MASK                     0xf000
#define DSC2B2_SM_CTRL9_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B2_SM_CTRL9_RESERVED_FOR_ECO0_BITS                     4
#define DSC2B2_SM_CTRL9_RESERVED_FOR_ECO0_SHIFT                    12

/* Dsc2b2 :: sm_ctrl9 :: dfe_max_val [11:06] */
#define DSC2B2_SM_CTRL9_DFE_MAX_VAL_MASK                           0x0fc0
#define DSC2B2_SM_CTRL9_DFE_MAX_VAL_ALIGN                          0
#define DSC2B2_SM_CTRL9_DFE_MAX_VAL_BITS                           6
#define DSC2B2_SM_CTRL9_DFE_MAX_VAL_SHIFT                          6

/* Dsc2b2 :: sm_ctrl9 :: dfe_min_val [05:00] */
#define DSC2B2_SM_CTRL9_DFE_MIN_VAL_MASK                           0x003f
#define DSC2B2_SM_CTRL9_DFE_MIN_VAL_ALIGN                          0
#define DSC2B2_SM_CTRL9_DFE_MIN_VAL_BITS                           6
#define DSC2B2_SM_CTRL9_DFE_MIN_VAL_SHIFT                          0


/****************************************************************************
 * Dsc2b2 :: sm_ctrl10
 ***************************************************************************/
/* Dsc2b2 :: sm_ctrl10 :: reserved_for_eco0 [15:14] */
#define DSC2B2_SM_CTRL10_RESERVED_FOR_ECO0_MASK                    0xc000
#define DSC2B2_SM_CTRL10_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2B2_SM_CTRL10_RESERVED_FOR_ECO0_BITS                    2
#define DSC2B2_SM_CTRL10_RESERVED_FOR_ECO0_SHIFT                   14

/* Dsc2b2 :: sm_ctrl10 :: br_pf_tap_en [13:07] */
#define DSC2B2_SM_CTRL10_BR_PF_TAP_EN_MASK                         0x3f80
#define DSC2B2_SM_CTRL10_BR_PF_TAP_EN_ALIGN                        0
#define DSC2B2_SM_CTRL10_BR_PF_TAP_EN_BITS                         7
#define DSC2B2_SM_CTRL10_BR_PF_TAP_EN_SHIFT                        7

/* Dsc2b2 :: sm_ctrl10 :: osx1_pf_tap_en [06:00] */
#define DSC2B2_SM_CTRL10_OSX1_PF_TAP_EN_MASK                       0x007f
#define DSC2B2_SM_CTRL10_OSX1_PF_TAP_EN_ALIGN                      0
#define DSC2B2_SM_CTRL10_OSX1_PF_TAP_EN_BITS                       7
#define DSC2B2_SM_CTRL10_OSX1_PF_TAP_EN_SHIFT                      0


/****************************************************************************
 * Dsc2b2 :: sm_ctrl11
 ***************************************************************************/
/* Dsc2b2 :: sm_ctrl11 :: reserved_for_eco0 [15:15] */
#define DSC2B2_SM_CTRL11_RESERVED_FOR_ECO0_MASK                    0x8000
#define DSC2B2_SM_CTRL11_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2B2_SM_CTRL11_RESERVED_FOR_ECO0_BITS                    1
#define DSC2B2_SM_CTRL11_RESERVED_FOR_ECO0_SHIFT                   15

/* Dsc2b2 :: sm_ctrl11 :: msr_br_vga_timeout [14:10] */
#define DSC2B2_SM_CTRL11_MSR_BR_VGA_TIMEOUT_MASK                   0x7c00
#define DSC2B2_SM_CTRL11_MSR_BR_VGA_TIMEOUT_ALIGN                  0
#define DSC2B2_SM_CTRL11_MSR_BR_VGA_TIMEOUT_BITS                   5
#define DSC2B2_SM_CTRL11_MSR_BR_VGA_TIMEOUT_SHIFT                  10

/* Dsc2b2 :: sm_ctrl11 :: hysteresis_timeout [09:05] */
#define DSC2B2_SM_CTRL11_HYSTERESIS_TIMEOUT_MASK                   0x03e0
#define DSC2B2_SM_CTRL11_HYSTERESIS_TIMEOUT_ALIGN                  0
#define DSC2B2_SM_CTRL11_HYSTERESIS_TIMEOUT_BITS                   5
#define DSC2B2_SM_CTRL11_HYSTERESIS_TIMEOUT_SHIFT                  5

/* Dsc2b2 :: sm_ctrl11 :: msr_postc_timeout [04:00] */
#define DSC2B2_SM_CTRL11_MSR_POSTC_TIMEOUT_MASK                    0x001f
#define DSC2B2_SM_CTRL11_MSR_POSTC_TIMEOUT_ALIGN                   0
#define DSC2B2_SM_CTRL11_MSR_POSTC_TIMEOUT_BITS                    5
#define DSC2B2_SM_CTRL11_MSR_POSTC_TIMEOUT_SHIFT                   0


/****************************************************************************
 * Dsc2b2 :: sm_ctrl12
 ***************************************************************************/
/* Dsc2b2 :: sm_ctrl12 :: reserved_for_eco0 [15:14] */
#define DSC2B2_SM_CTRL12_RESERVED_FOR_ECO0_MASK                    0xc000
#define DSC2B2_SM_CTRL12_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2B2_SM_CTRL12_RESERVED_FOR_ECO0_BITS                    2
#define DSC2B2_SM_CTRL12_RESERVED_FOR_ECO0_SHIFT                   14

/* Dsc2b2 :: sm_ctrl12 :: br_vga_lms_gain [13:12] */
#define DSC2B2_SM_CTRL12_BR_VGA_LMS_GAIN_MASK                      0x3000
#define DSC2B2_SM_CTRL12_BR_VGA_LMS_GAIN_ALIGN                     0
#define DSC2B2_SM_CTRL12_BR_VGA_LMS_GAIN_BITS                      2
#define DSC2B2_SM_CTRL12_BR_VGA_LMS_GAIN_SHIFT                     12

/* Dsc2b2 :: sm_ctrl12 :: postc_dfe_lms_gain [11:10] */
#define DSC2B2_SM_CTRL12_POSTC_DFE_LMS_GAIN_MASK                   0x0c00
#define DSC2B2_SM_CTRL12_POSTC_DFE_LMS_GAIN_ALIGN                  0
#define DSC2B2_SM_CTRL12_POSTC_DFE_LMS_GAIN_BITS                   2
#define DSC2B2_SM_CTRL12_POSTC_DFE_LMS_GAIN_SHIFT                  10

/* Dsc2b2 :: sm_ctrl12 :: cdr_phase_inversion_timeout [09:05] */
#define DSC2B2_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_MASK          0x03e0
#define DSC2B2_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_ALIGN         0
#define DSC2B2_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_BITS          5
#define DSC2B2_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_SHIFT         5

/* Dsc2b2 :: sm_ctrl12 :: msr_pf_timeout [04:00] */
#define DSC2B2_SM_CTRL12_MSR_PF_TIMEOUT_MASK                       0x001f
#define DSC2B2_SM_CTRL12_MSR_PF_TIMEOUT_ALIGN                      0
#define DSC2B2_SM_CTRL12_MSR_PF_TIMEOUT_BITS                       5
#define DSC2B2_SM_CTRL12_MSR_PF_TIMEOUT_SHIFT                      0


/****************************************************************************
 * Dsc2b2 :: dsc_diag_ctrl0
 ***************************************************************************/
/* Dsc2b2 :: dsc_diag_ctrl0 :: reserved_for_eco0 [15:11] */
#define DSC2B2_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_MASK               0xf800
#define DSC2B2_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC2B2_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_BITS               5
#define DSC2B2_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_SHIFT              11

/* Dsc2b2 :: dsc_diag_ctrl0 :: voffset [10:07] */
#define DSC2B2_DSC_DIAG_CTRL0_VOFFSET_MASK                         0x0780
#define DSC2B2_DSC_DIAG_CTRL0_VOFFSET_ALIGN                        0
#define DSC2B2_DSC_DIAG_CTRL0_VOFFSET_BITS                         4
#define DSC2B2_DSC_DIAG_CTRL0_VOFFSET_SHIFT                        7

/* Dsc2b2 :: dsc_diag_ctrl0 :: hoffset [06:01] */
#define DSC2B2_DSC_DIAG_CTRL0_HOFFSET_MASK                         0x007e
#define DSC2B2_DSC_DIAG_CTRL0_HOFFSET_ALIGN                        0
#define DSC2B2_DSC_DIAG_CTRL0_HOFFSET_BITS                         6
#define DSC2B2_DSC_DIAG_CTRL0_HOFFSET_SHIFT                        1

/* Dsc2b2 :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */
#define DSC2B2_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK                  0x0001
#define DSC2B2_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN                 0
#define DSC2B2_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS                  1
#define DSC2B2_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT                 0


/****************************************************************************
 * Dsc2b2 :: dsc_misc_ctrl0
 ***************************************************************************/
/* Dsc2b2 :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */
#define DSC2B2_DSC_MISC_CTRL0_RXSEQSTART_MASK                      0x8000
#define DSC2B2_DSC_MISC_CTRL0_RXSEQSTART_ALIGN                     0
#define DSC2B2_DSC_MISC_CTRL0_RXSEQSTART_BITS                      1
#define DSC2B2_DSC_MISC_CTRL0_RXSEQSTART_SHIFT                     15

/* Dsc2b2 :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */
#define DSC2B2_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK                  0x4000
#define DSC2B2_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN                 0
#define DSC2B2_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS                  1
#define DSC2B2_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT                 14

/* Dsc2b2 :: dsc_misc_ctrl0 :: enable_acor_picw [13:13] */
#define DSC2B2_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_MASK                0x2000
#define DSC2B2_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_ALIGN               0
#define DSC2B2_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_BITS                1
#define DSC2B2_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_SHIFT               13

/* Dsc2b2 :: dsc_misc_ctrl0 :: reserved_for_eco0 [12:10] */
#define DSC2B2_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_MASK               0x1c00
#define DSC2B2_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC2B2_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_BITS               3
#define DSC2B2_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_SHIFT              10

/* Dsc2b2 :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */
#define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK                 0x0200
#define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN                0
#define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS                 1
#define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT                9

/* Dsc2b2 :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */
#define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK             0x0100
#define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN            0
#define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS             1
#define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT            8

/* Dsc2b2 :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */
#define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK                  0x0080
#define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN                 0
#define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS                  1
#define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT                 7

/* Dsc2b2 :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */
#define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK              0x0070
#define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN             0
#define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS              3
#define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT             4

/* Dsc2b2 :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */
#define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK                    0x000f
#define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN                   0
#define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS                    4
#define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT                   0
#define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_Off                     0
#define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data                1
#define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1             2
#define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1           3
#define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco             4
#define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg                 6
#define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr             7
#define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd           8
#define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe            9
#define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum               10


/****************************************************************************
 * Hypercore_USER_Dsc2b3
 ***************************************************************************/
/****************************************************************************
 * Dsc2b3 :: sm_ctrl0
 ***************************************************************************/
/* Dsc2b3 :: sm_ctrl0 :: reserved_for_eco0 [15:15] */
#define DSC2B3_SM_CTRL0_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2B3_SM_CTRL0_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B3_SM_CTRL0_RESERVED_FOR_ECO0_BITS                     1
#define DSC2B3_SM_CTRL0_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2b3 :: sm_ctrl0 :: bypass_tx_postc_cal [14:14] */
#define DSC2B3_SM_CTRL0_BYPASS_TX_POSTC_CAL_MASK                   0x4000
#define DSC2B3_SM_CTRL0_BYPASS_TX_POSTC_CAL_ALIGN                  0
#define DSC2B3_SM_CTRL0_BYPASS_TX_POSTC_CAL_BITS                   1
#define DSC2B3_SM_CTRL0_BYPASS_TX_POSTC_CAL_SHIFT                  14

/* Dsc2b3 :: sm_ctrl0 :: bypass_br_vga [13:13] */
#define DSC2B3_SM_CTRL0_BYPASS_BR_VGA_MASK                         0x2000
#define DSC2B3_SM_CTRL0_BYPASS_BR_VGA_ALIGN                        0
#define DSC2B3_SM_CTRL0_BYPASS_BR_VGA_BITS                         1
#define DSC2B3_SM_CTRL0_BYPASS_BR_VGA_SHIFT                        13

/* Dsc2b3 :: sm_ctrl0 :: postc_metric_ctrl [12:12] */
#define DSC2B3_SM_CTRL0_POSTC_METRIC_CTRL_MASK                     0x1000
#define DSC2B3_SM_CTRL0_POSTC_METRIC_CTRL_ALIGN                    0
#define DSC2B3_SM_CTRL0_POSTC_METRIC_CTRL_BITS                     1
#define DSC2B3_SM_CTRL0_POSTC_METRIC_CTRL_SHIFT                    12

/* Dsc2b3 :: sm_ctrl0 :: hysteresis_en [11:11] */
#define DSC2B3_SM_CTRL0_HYSTERESIS_EN_MASK                         0x0800
#define DSC2B3_SM_CTRL0_HYSTERESIS_EN_ALIGN                        0
#define DSC2B3_SM_CTRL0_HYSTERESIS_EN_BITS                         1
#define DSC2B3_SM_CTRL0_HYSTERESIS_EN_SHIFT                        11

/* Dsc2b3 :: sm_ctrl0 :: slicer_cal_linear_srch [10:10] */
#define DSC2B3_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_MASK                0x0400
#define DSC2B3_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_ALIGN               0
#define DSC2B3_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_BITS                1
#define DSC2B3_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_SHIFT               10

/* Dsc2b3 :: sm_ctrl0 :: bypass_br_pf_cal [09:09] */
#define DSC2B3_SM_CTRL0_BYPASS_BR_PF_CAL_MASK                      0x0200
#define DSC2B3_SM_CTRL0_BYPASS_BR_PF_CAL_ALIGN                     0
#define DSC2B3_SM_CTRL0_BYPASS_BR_PF_CAL_BITS                      1
#define DSC2B3_SM_CTRL0_BYPASS_BR_PF_CAL_SHIFT                     9

/* Dsc2b3 :: sm_ctrl0 :: bypass_osx2_pf_cal [08:08] */
#define DSC2B3_SM_CTRL0_BYPASS_OSX2_PF_CAL_MASK                    0x0100
#define DSC2B3_SM_CTRL0_BYPASS_OSX2_PF_CAL_ALIGN                   0
#define DSC2B3_SM_CTRL0_BYPASS_OSX2_PF_CAL_BITS                    1
#define DSC2B3_SM_CTRL0_BYPASS_OSX2_PF_CAL_SHIFT                   8

/* Dsc2b3 :: sm_ctrl0 :: bypass_osx1_pf_cal [07:07] */
#define DSC2B3_SM_CTRL0_BYPASS_OSX1_PF_CAL_MASK                    0x0080
#define DSC2B3_SM_CTRL0_BYPASS_OSX1_PF_CAL_ALIGN                   0
#define DSC2B3_SM_CTRL0_BYPASS_OSX1_PF_CAL_BITS                    1
#define DSC2B3_SM_CTRL0_BYPASS_OSX1_PF_CAL_SHIFT                   7

/* Dsc2b3 :: sm_ctrl0 :: bypass_data_slicer_recal [06:06] */
#define DSC2B3_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_MASK              0x0040
#define DSC2B3_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_ALIGN             0
#define DSC2B3_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_BITS              1
#define DSC2B3_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_SHIFT             6

/* Dsc2b3 :: sm_ctrl0 :: bypass_osx45_slicer_cal [05:05] */
#define DSC2B3_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_MASK               0x0020
#define DSC2B3_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_ALIGN              0
#define DSC2B3_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_BITS               1
#define DSC2B3_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_SHIFT              5

/* Dsc2b3 :: sm_ctrl0 :: bypass_phase_slicer_cal [04:04] */
#define DSC2B3_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_MASK               0x0010
#define DSC2B3_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_ALIGN              0
#define DSC2B3_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_BITS               1
#define DSC2B3_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_SHIFT              4

/* Dsc2b3 :: sm_ctrl0 :: bypass_br_data_slicer_cal [03:03] */
#define DSC2B3_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_MASK             0x0008
#define DSC2B3_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_ALIGN            0
#define DSC2B3_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_BITS             1
#define DSC2B3_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_SHIFT            3

/* Dsc2b3 :: sm_ctrl0 :: bypass_os_data_slicer_cal [02:02] */
#define DSC2B3_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_MASK             0x0004
#define DSC2B3_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_ALIGN            0
#define DSC2B3_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_BITS             1
#define DSC2B3_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_SHIFT            2

/* Dsc2b3 :: sm_ctrl0 :: restart_tuning [01:01] */
#define DSC2B3_SM_CTRL0_RESTART_TUNING_MASK                        0x0002
#define DSC2B3_SM_CTRL0_RESTART_TUNING_ALIGN                       0
#define DSC2B3_SM_CTRL0_RESTART_TUNING_BITS                        1
#define DSC2B3_SM_CTRL0_RESTART_TUNING_SHIFT                       1

/* Dsc2b3 :: sm_ctrl0 :: tuning_sm_en [00:00] */
#define DSC2B3_SM_CTRL0_TUNING_SM_EN_MASK                          0x0001
#define DSC2B3_SM_CTRL0_TUNING_SM_EN_ALIGN                         0
#define DSC2B3_SM_CTRL0_TUNING_SM_EN_BITS                          1
#define DSC2B3_SM_CTRL0_TUNING_SM_EN_SHIFT                         0


/****************************************************************************
 * Dsc2b3 :: sm_ctrl1
 ***************************************************************************/
/* Dsc2b3 :: sm_ctrl1 :: fast_timer [15:15] */
#define DSC2B3_SM_CTRL1_FAST_TIMER_MASK                            0x8000
#define DSC2B3_SM_CTRL1_FAST_TIMER_ALIGN                           0
#define DSC2B3_SM_CTRL1_FAST_TIMER_BITS                            1
#define DSC2B3_SM_CTRL1_FAST_TIMER_SHIFT                           15

/* Dsc2b3 :: sm_ctrl1 :: acq2_timeout [14:10] */
#define DSC2B3_SM_CTRL1_ACQ2_TIMEOUT_MASK                          0x7c00
#define DSC2B3_SM_CTRL1_ACQ2_TIMEOUT_ALIGN                         0
#define DSC2B3_SM_CTRL1_ACQ2_TIMEOUT_BITS                          5
#define DSC2B3_SM_CTRL1_ACQ2_TIMEOUT_SHIFT                         10

/* Dsc2b3 :: sm_ctrl1 :: acq1_timeout [09:05] */
#define DSC2B3_SM_CTRL1_ACQ1_TIMEOUT_MASK                          0x03e0
#define DSC2B3_SM_CTRL1_ACQ1_TIMEOUT_ALIGN                         0
#define DSC2B3_SM_CTRL1_ACQ1_TIMEOUT_BITS                          5
#define DSC2B3_SM_CTRL1_ACQ1_TIMEOUT_SHIFT                         5

/* Dsc2b3 :: sm_ctrl1 :: acqcdr_timeout [04:00] */
#define DSC2B3_SM_CTRL1_ACQCDR_TIMEOUT_MASK                        0x001f
#define DSC2B3_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN                       0
#define DSC2B3_SM_CTRL1_ACQCDR_TIMEOUT_BITS                        5
#define DSC2B3_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT                       0


/****************************************************************************
 * Dsc2b3 :: sm_ctrl2
 ***************************************************************************/
/* Dsc2b3 :: sm_ctrl2 :: acqvga_timeout [15:11] */
#define DSC2B3_SM_CTRL2_ACQVGA_TIMEOUT_MASK                        0xf800
#define DSC2B3_SM_CTRL2_ACQVGA_TIMEOUT_ALIGN                       0
#define DSC2B3_SM_CTRL2_ACQVGA_TIMEOUT_BITS                        5
#define DSC2B3_SM_CTRL2_ACQVGA_TIMEOUT_SHIFT                       11

/* Dsc2b3 :: sm_ctrl2 :: bypass_os_integ_xfer [10:10] */
#define DSC2B3_SM_CTRL2_BYPASS_OS_INTEG_XFER_MASK                  0x0400
#define DSC2B3_SM_CTRL2_BYPASS_OS_INTEG_XFER_ALIGN                 0
#define DSC2B3_SM_CTRL2_BYPASS_OS_INTEG_XFER_BITS                  1
#define DSC2B3_SM_CTRL2_BYPASS_OS_INTEG_XFER_SHIFT                 10

/* Dsc2b3 :: sm_ctrl2 :: vga_frzval [09:09] */
#define DSC2B3_SM_CTRL2_VGA_FRZVAL_MASK                            0x0200
#define DSC2B3_SM_CTRL2_VGA_FRZVAL_ALIGN                           0
#define DSC2B3_SM_CTRL2_VGA_FRZVAL_BITS                            1
#define DSC2B3_SM_CTRL2_VGA_FRZVAL_SHIFT                           9

/* Dsc2b3 :: sm_ctrl2 :: vga_frcfrz [08:08] */
#define DSC2B3_SM_CTRL2_VGA_FRCFRZ_MASK                            0x0100
#define DSC2B3_SM_CTRL2_VGA_FRCFRZ_ALIGN                           0
#define DSC2B3_SM_CTRL2_VGA_FRCFRZ_BITS                            1
#define DSC2B3_SM_CTRL2_VGA_FRCFRZ_SHIFT                           8

/* Dsc2b3 :: sm_ctrl2 :: dfe_frzval [07:07] */
#define DSC2B3_SM_CTRL2_DFE_FRZVAL_MASK                            0x0080
#define DSC2B3_SM_CTRL2_DFE_FRZVAL_ALIGN                           0
#define DSC2B3_SM_CTRL2_DFE_FRZVAL_BITS                            1
#define DSC2B3_SM_CTRL2_DFE_FRZVAL_SHIFT                           7

/* Dsc2b3 :: sm_ctrl2 :: dfe_frcfrz [06:06] */
#define DSC2B3_SM_CTRL2_DFE_FRCFRZ_MASK                            0x0040
#define DSC2B3_SM_CTRL2_DFE_FRCFRZ_ALIGN                           0
#define DSC2B3_SM_CTRL2_DFE_FRCFRZ_BITS                            1
#define DSC2B3_SM_CTRL2_DFE_FRCFRZ_SHIFT                           6

/* Dsc2b3 :: sm_ctrl2 :: dsc_clr_val [05:05] */
#define DSC2B3_SM_CTRL2_DSC_CLR_VAL_MASK                           0x0020
#define DSC2B3_SM_CTRL2_DSC_CLR_VAL_ALIGN                          0
#define DSC2B3_SM_CTRL2_DSC_CLR_VAL_BITS                           1
#define DSC2B3_SM_CTRL2_DSC_CLR_VAL_SHIFT                          5

/* Dsc2b3 :: sm_ctrl2 :: dsc_clr_frc [04:04] */
#define DSC2B3_SM_CTRL2_DSC_CLR_FRC_MASK                           0x0010
#define DSC2B3_SM_CTRL2_DSC_CLR_FRC_ALIGN                          0
#define DSC2B3_SM_CTRL2_DSC_CLR_FRC_BITS                           1
#define DSC2B3_SM_CTRL2_DSC_CLR_FRC_SHIFT                          4

/* Dsc2b3 :: sm_ctrl2 :: train2_req [03:03] */
#define DSC2B3_SM_CTRL2_TRAIN2_REQ_MASK                            0x0008
#define DSC2B3_SM_CTRL2_TRAIN2_REQ_ALIGN                           0
#define DSC2B3_SM_CTRL2_TRAIN2_REQ_BITS                            1
#define DSC2B3_SM_CTRL2_TRAIN2_REQ_SHIFT                           3

/* Dsc2b3 :: sm_ctrl2 :: train1_req [02:02] */
#define DSC2B3_SM_CTRL2_TRAIN1_REQ_MASK                            0x0004
#define DSC2B3_SM_CTRL2_TRAIN1_REQ_ALIGN                           0
#define DSC2B3_SM_CTRL2_TRAIN1_REQ_BITS                            1
#define DSC2B3_SM_CTRL2_TRAIN1_REQ_SHIFT                           2

/* Dsc2b3 :: sm_ctrl2 :: soft_ack [01:01] */
#define DSC2B3_SM_CTRL2_SOFT_ACK_MASK                              0x0002
#define DSC2B3_SM_CTRL2_SOFT_ACK_ALIGN                             0
#define DSC2B3_SM_CTRL2_SOFT_ACK_BITS                              1
#define DSC2B3_SM_CTRL2_SOFT_ACK_SHIFT                             1

/* Dsc2b3 :: sm_ctrl2 :: train_mode_en [00:00] */
#define DSC2B3_SM_CTRL2_TRAIN_MODE_EN_MASK                         0x0001
#define DSC2B3_SM_CTRL2_TRAIN_MODE_EN_ALIGN                        0
#define DSC2B3_SM_CTRL2_TRAIN_MODE_EN_BITS                         1
#define DSC2B3_SM_CTRL2_TRAIN_MODE_EN_SHIFT                        0


/****************************************************************************
 * Dsc2b3 :: sm_ctrl3
 ***************************************************************************/
/* Dsc2b3 :: sm_ctrl3 :: reserved_for_eco0 [15:15] */
#define DSC2B3_SM_CTRL3_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2B3_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B3_SM_CTRL3_RESERVED_FOR_ECO0_BITS                     1
#define DSC2B3_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2b3 :: sm_ctrl3 :: cdrbr_bwsel_prop_acqcdr [14:12] */
#define DSC2B3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_MASK               0x7000
#define DSC2B3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_ALIGN              0
#define DSC2B3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_BITS               3
#define DSC2B3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_SHIFT              12

/* Dsc2b3 :: sm_ctrl3 :: dfe_gain_acq2 [11:10] */
#define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ2_MASK                         0x0c00
#define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN                        0
#define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ2_BITS                         2
#define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT                        10

/* Dsc2b3 :: sm_ctrl3 :: dfe_gain_acq1 [09:08] */
#define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ1_MASK                         0x0300
#define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN                        0
#define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ1_BITS                         2
#define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT                        8

/* Dsc2b3 :: sm_ctrl3 :: vga_gain_acq2 [07:06] */
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ2_MASK                         0x00c0
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN                        0
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ2_BITS                         2
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT                        6

/* Dsc2b3 :: sm_ctrl3 :: vga_gain_acq1 [05:04] */
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ1_MASK                         0x0030
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN                        0
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ1_BITS                         2
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT                        4

/* Dsc2b3 :: sm_ctrl3 :: vga_gain_acqcdr [03:02] */
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQCDR_MASK                       0x000c
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN                      0
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQCDR_BITS                       2
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT                      2

/* Dsc2b3 :: sm_ctrl3 :: vga_gain_acqvga [01:00] */
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQVGA_MASK                       0x0003
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN                      0
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQVGA_BITS                       2
#define DSC2B3_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT                      0


/****************************************************************************
 * Dsc2b3 :: sm_ctrl4
 ***************************************************************************/
/* Dsc2b3 :: sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */
#define DSC2B3_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK             0xc000
#define DSC2B3_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN            0
#define DSC2B3_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS             2
#define DSC2B3_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT            14

/* Dsc2b3 :: sm_ctrl4 :: cdros45_bwsel_integ_offset [13:12] */
#define DSC2B3_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_MASK            0x3000
#define DSC2B3_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_ALIGN           0
#define DSC2B3_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_BITS            2
#define DSC2B3_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_SHIFT           12

/* Dsc2b3 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq2 [11:10] */
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_MASK                0x0c00
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_ALIGN               0
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_BITS                2
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_SHIFT               10

/* Dsc2b3 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq1 [09:08] */
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_MASK                0x0300
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_ALIGN               0
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_BITS                2
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_SHIFT               8

/* Dsc2b3 :: sm_ctrl4 :: cdrbr_bwsel_integ_acqcdr [07:06] */
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_MASK              0x00c0
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN             0
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_BITS              2
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT             6

/* Dsc2b3 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq2 [05:03] */
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_MASK                 0x0038
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_ALIGN                0
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_BITS                 3
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_SHIFT                3

/* Dsc2b3 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq1 [02:00] */
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_MASK                 0x0007
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_ALIGN                0
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_BITS                 3
#define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_SHIFT                0


/****************************************************************************
 * Dsc2b3 :: sm_ctrl5
 ***************************************************************************/
/* Dsc2b3 :: sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [15:12] */
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK              0xf000
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN             0
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS              4
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT             12

/* Dsc2b3 :: sm_ctrl5 :: cdros_bwsel_integ_acqcdr [11:08] */
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK              0x0f00
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN             0
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS              4
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT             8

/* Dsc2b3 :: sm_ctrl5 :: cdros_bwsel_prop_acq1_2 [07:04] */
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_MASK               0x00f0
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_ALIGN              0
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_BITS               4
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_SHIFT              4

/* Dsc2b3 :: sm_ctrl5 :: cdros_bwsel_prop_acqcdr [03:00] */
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_MASK               0x000f
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_ALIGN              0
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_BITS               4
#define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_SHIFT              0


/****************************************************************************
 * Dsc2b3 :: sm_ctrl6
 ***************************************************************************/
/* Dsc2b3 :: sm_ctrl6 :: reserved_for_eco0 [15:13] */
#define DSC2B3_SM_CTRL6_RESERVED_FOR_ECO0_MASK                     0xe000
#define DSC2B3_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B3_SM_CTRL6_RESERVED_FOR_ECO0_BITS                     3
#define DSC2B3_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT                    13

/* Dsc2b3 :: sm_ctrl6 :: cdrbr_bwsel_integ_acqphase [12:11] */
#define DSC2B3_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_MASK            0x1800
#define DSC2B3_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN           0
#define DSC2B3_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_BITS            2
#define DSC2B3_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT           11

/* Dsc2b3 :: sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [10:08] */
#define DSC2B3_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK             0x0700
#define DSC2B3_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN            0
#define DSC2B3_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS             3
#define DSC2B3_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT            8

/* Dsc2b3 :: sm_ctrl6 :: cdros_bwsel_integ_acqvga [07:04] */
#define DSC2B3_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_MASK              0x00f0
#define DSC2B3_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_ALIGN             0
#define DSC2B3_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_BITS              4
#define DSC2B3_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_SHIFT             4

/* Dsc2b3 :: sm_ctrl6 :: cdros_bwsel_prop_acqvga [03:00] */
#define DSC2B3_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_MASK               0x000f
#define DSC2B3_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_ALIGN              0
#define DSC2B3_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_BITS               4
#define DSC2B3_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_SHIFT              0


/****************************************************************************
 * Dsc2b3 :: sm_ctrl7
 ***************************************************************************/
/* Dsc2b3 :: sm_ctrl7 :: reserved_for_eco0 [15:15] */
#define DSC2B3_SM_CTRL7_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2B3_SM_CTRL7_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B3_SM_CTRL7_RESERVED_FOR_ECO0_BITS                     1
#define DSC2B3_SM_CTRL7_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2b3 :: sm_ctrl7 :: pf_ctrl_br_offset [14:12] */
#define DSC2B3_SM_CTRL7_PF_CTRL_BR_OFFSET_MASK                     0x7000
#define DSC2B3_SM_CTRL7_PF_CTRL_BR_OFFSET_ALIGN                    0
#define DSC2B3_SM_CTRL7_PF_CTRL_BR_OFFSET_BITS                     3
#define DSC2B3_SM_CTRL7_PF_CTRL_BR_OFFSET_SHIFT                    12

/* Dsc2b3 :: sm_ctrl7 :: pf_ctrl_osx1_offset [11:09] */
#define DSC2B3_SM_CTRL7_PF_CTRL_OSX1_OFFSET_MASK                   0x0e00
#define DSC2B3_SM_CTRL7_PF_CTRL_OSX1_OFFSET_ALIGN                  0
#define DSC2B3_SM_CTRL7_PF_CTRL_OSX1_OFFSET_BITS                   3
#define DSC2B3_SM_CTRL7_PF_CTRL_OSX1_OFFSET_SHIFT                  9

/* Dsc2b3 :: sm_ctrl7 :: pf_ctrl_osx2_offset [08:06] */
#define DSC2B3_SM_CTRL7_PF_CTRL_OSX2_OFFSET_MASK                   0x01c0
#define DSC2B3_SM_CTRL7_PF_CTRL_OSX2_OFFSET_ALIGN                  0
#define DSC2B3_SM_CTRL7_PF_CTRL_OSX2_OFFSET_BITS                   3
#define DSC2B3_SM_CTRL7_PF_CTRL_OSX2_OFFSET_SHIFT                  6

/* Dsc2b3 :: sm_ctrl7 :: pf_ctrl_br_init [05:03] */
#define DSC2B3_SM_CTRL7_PF_CTRL_BR_INIT_MASK                       0x0038
#define DSC2B3_SM_CTRL7_PF_CTRL_BR_INIT_ALIGN                      0
#define DSC2B3_SM_CTRL7_PF_CTRL_BR_INIT_BITS                       3
#define DSC2B3_SM_CTRL7_PF_CTRL_BR_INIT_SHIFT                      3

/* Dsc2b3 :: sm_ctrl7 :: pf_ctrl_os_init [02:00] */
#define DSC2B3_SM_CTRL7_PF_CTRL_OS_INIT_MASK                       0x0007
#define DSC2B3_SM_CTRL7_PF_CTRL_OS_INIT_ALIGN                      0
#define DSC2B3_SM_CTRL7_PF_CTRL_OS_INIT_BITS                       3
#define DSC2B3_SM_CTRL7_PF_CTRL_OS_INIT_SHIFT                      0


/****************************************************************************
 * Dsc2b3 :: sm_ctrl8
 ***************************************************************************/
/* Dsc2b3 :: sm_ctrl8 :: reserved_for_eco0 [15:10] */
#define DSC2B3_SM_CTRL8_RESERVED_FOR_ECO0_MASK                     0xfc00
#define DSC2B3_SM_CTRL8_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B3_SM_CTRL8_RESERVED_FOR_ECO0_BITS                     6
#define DSC2B3_SM_CTRL8_RESERVED_FOR_ECO0_SHIFT                    10

/* Dsc2b3 :: sm_ctrl8 :: vga_max_val [09:05] */
#define DSC2B3_SM_CTRL8_VGA_MAX_VAL_MASK                           0x03e0
#define DSC2B3_SM_CTRL8_VGA_MAX_VAL_ALIGN                          0
#define DSC2B3_SM_CTRL8_VGA_MAX_VAL_BITS                           5
#define DSC2B3_SM_CTRL8_VGA_MAX_VAL_SHIFT                          5

/* Dsc2b3 :: sm_ctrl8 :: vga_min_val [04:00] */
#define DSC2B3_SM_CTRL8_VGA_MIN_VAL_MASK                           0x001f
#define DSC2B3_SM_CTRL8_VGA_MIN_VAL_ALIGN                          0
#define DSC2B3_SM_CTRL8_VGA_MIN_VAL_BITS                           5
#define DSC2B3_SM_CTRL8_VGA_MIN_VAL_SHIFT                          0


/****************************************************************************
 * Dsc2b3 :: sm_ctrl9
 ***************************************************************************/
/* Dsc2b3 :: sm_ctrl9 :: reserved_for_eco0 [15:12] */
#define DSC2B3_SM_CTRL9_RESERVED_FOR_ECO0_MASK                     0xf000
#define DSC2B3_SM_CTRL9_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2B3_SM_CTRL9_RESERVED_FOR_ECO0_BITS                     4
#define DSC2B3_SM_CTRL9_RESERVED_FOR_ECO0_SHIFT                    12

/* Dsc2b3 :: sm_ctrl9 :: dfe_max_val [11:06] */
#define DSC2B3_SM_CTRL9_DFE_MAX_VAL_MASK                           0x0fc0
#define DSC2B3_SM_CTRL9_DFE_MAX_VAL_ALIGN                          0
#define DSC2B3_SM_CTRL9_DFE_MAX_VAL_BITS                           6
#define DSC2B3_SM_CTRL9_DFE_MAX_VAL_SHIFT                          6

/* Dsc2b3 :: sm_ctrl9 :: dfe_min_val [05:00] */
#define DSC2B3_SM_CTRL9_DFE_MIN_VAL_MASK                           0x003f
#define DSC2B3_SM_CTRL9_DFE_MIN_VAL_ALIGN                          0
#define DSC2B3_SM_CTRL9_DFE_MIN_VAL_BITS                           6
#define DSC2B3_SM_CTRL9_DFE_MIN_VAL_SHIFT                          0


/****************************************************************************
 * Dsc2b3 :: sm_ctrl10
 ***************************************************************************/
/* Dsc2b3 :: sm_ctrl10 :: reserved_for_eco0 [15:14] */
#define DSC2B3_SM_CTRL10_RESERVED_FOR_ECO0_MASK                    0xc000
#define DSC2B3_SM_CTRL10_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2B3_SM_CTRL10_RESERVED_FOR_ECO0_BITS                    2
#define DSC2B3_SM_CTRL10_RESERVED_FOR_ECO0_SHIFT                   14

/* Dsc2b3 :: sm_ctrl10 :: br_pf_tap_en [13:07] */
#define DSC2B3_SM_CTRL10_BR_PF_TAP_EN_MASK                         0x3f80
#define DSC2B3_SM_CTRL10_BR_PF_TAP_EN_ALIGN                        0
#define DSC2B3_SM_CTRL10_BR_PF_TAP_EN_BITS                         7
#define DSC2B3_SM_CTRL10_BR_PF_TAP_EN_SHIFT                        7

/* Dsc2b3 :: sm_ctrl10 :: osx1_pf_tap_en [06:00] */
#define DSC2B3_SM_CTRL10_OSX1_PF_TAP_EN_MASK                       0x007f
#define DSC2B3_SM_CTRL10_OSX1_PF_TAP_EN_ALIGN                      0
#define DSC2B3_SM_CTRL10_OSX1_PF_TAP_EN_BITS                       7
#define DSC2B3_SM_CTRL10_OSX1_PF_TAP_EN_SHIFT                      0


/****************************************************************************
 * Dsc2b3 :: sm_ctrl11
 ***************************************************************************/
/* Dsc2b3 :: sm_ctrl11 :: reserved_for_eco0 [15:15] */
#define DSC2B3_SM_CTRL11_RESERVED_FOR_ECO0_MASK                    0x8000
#define DSC2B3_SM_CTRL11_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2B3_SM_CTRL11_RESERVED_FOR_ECO0_BITS                    1
#define DSC2B3_SM_CTRL11_RESERVED_FOR_ECO0_SHIFT                   15

/* Dsc2b3 :: sm_ctrl11 :: msr_br_vga_timeout [14:10] */
#define DSC2B3_SM_CTRL11_MSR_BR_VGA_TIMEOUT_MASK                   0x7c00
#define DSC2B3_SM_CTRL11_MSR_BR_VGA_TIMEOUT_ALIGN                  0
#define DSC2B3_SM_CTRL11_MSR_BR_VGA_TIMEOUT_BITS                   5
#define DSC2B3_SM_CTRL11_MSR_BR_VGA_TIMEOUT_SHIFT                  10

/* Dsc2b3 :: sm_ctrl11 :: hysteresis_timeout [09:05] */
#define DSC2B3_SM_CTRL11_HYSTERESIS_TIMEOUT_MASK                   0x03e0
#define DSC2B3_SM_CTRL11_HYSTERESIS_TIMEOUT_ALIGN                  0
#define DSC2B3_SM_CTRL11_HYSTERESIS_TIMEOUT_BITS                   5
#define DSC2B3_SM_CTRL11_HYSTERESIS_TIMEOUT_SHIFT                  5

/* Dsc2b3 :: sm_ctrl11 :: msr_postc_timeout [04:00] */
#define DSC2B3_SM_CTRL11_MSR_POSTC_TIMEOUT_MASK                    0x001f
#define DSC2B3_SM_CTRL11_MSR_POSTC_TIMEOUT_ALIGN                   0
#define DSC2B3_SM_CTRL11_MSR_POSTC_TIMEOUT_BITS                    5
#define DSC2B3_SM_CTRL11_MSR_POSTC_TIMEOUT_SHIFT                   0


/****************************************************************************
 * Dsc2b3 :: sm_ctrl12
 ***************************************************************************/
/* Dsc2b3 :: sm_ctrl12 :: reserved_for_eco0 [15:14] */
#define DSC2B3_SM_CTRL12_RESERVED_FOR_ECO0_MASK                    0xc000
#define DSC2B3_SM_CTRL12_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2B3_SM_CTRL12_RESERVED_FOR_ECO0_BITS                    2
#define DSC2B3_SM_CTRL12_RESERVED_FOR_ECO0_SHIFT                   14

/* Dsc2b3 :: sm_ctrl12 :: br_vga_lms_gain [13:12] */
#define DSC2B3_SM_CTRL12_BR_VGA_LMS_GAIN_MASK                      0x3000
#define DSC2B3_SM_CTRL12_BR_VGA_LMS_GAIN_ALIGN                     0
#define DSC2B3_SM_CTRL12_BR_VGA_LMS_GAIN_BITS                      2
#define DSC2B3_SM_CTRL12_BR_VGA_LMS_GAIN_SHIFT                     12

/* Dsc2b3 :: sm_ctrl12 :: postc_dfe_lms_gain [11:10] */
#define DSC2B3_SM_CTRL12_POSTC_DFE_LMS_GAIN_MASK                   0x0c00
#define DSC2B3_SM_CTRL12_POSTC_DFE_LMS_GAIN_ALIGN                  0
#define DSC2B3_SM_CTRL12_POSTC_DFE_LMS_GAIN_BITS                   2
#define DSC2B3_SM_CTRL12_POSTC_DFE_LMS_GAIN_SHIFT                  10

/* Dsc2b3 :: sm_ctrl12 :: cdr_phase_inversion_timeout [09:05] */
#define DSC2B3_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_MASK          0x03e0
#define DSC2B3_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_ALIGN         0
#define DSC2B3_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_BITS          5
#define DSC2B3_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_SHIFT         5

/* Dsc2b3 :: sm_ctrl12 :: msr_pf_timeout [04:00] */
#define DSC2B3_SM_CTRL12_MSR_PF_TIMEOUT_MASK                       0x001f
#define DSC2B3_SM_CTRL12_MSR_PF_TIMEOUT_ALIGN                      0
#define DSC2B3_SM_CTRL12_MSR_PF_TIMEOUT_BITS                       5
#define DSC2B3_SM_CTRL12_MSR_PF_TIMEOUT_SHIFT                      0


/****************************************************************************
 * Dsc2b3 :: dsc_diag_ctrl0
 ***************************************************************************/
/* Dsc2b3 :: dsc_diag_ctrl0 :: reserved_for_eco0 [15:11] */
#define DSC2B3_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_MASK               0xf800
#define DSC2B3_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC2B3_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_BITS               5
#define DSC2B3_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_SHIFT              11

/* Dsc2b3 :: dsc_diag_ctrl0 :: voffset [10:07] */
#define DSC2B3_DSC_DIAG_CTRL0_VOFFSET_MASK                         0x0780
#define DSC2B3_DSC_DIAG_CTRL0_VOFFSET_ALIGN                        0
#define DSC2B3_DSC_DIAG_CTRL0_VOFFSET_BITS                         4
#define DSC2B3_DSC_DIAG_CTRL0_VOFFSET_SHIFT                        7

/* Dsc2b3 :: dsc_diag_ctrl0 :: hoffset [06:01] */
#define DSC2B3_DSC_DIAG_CTRL0_HOFFSET_MASK                         0x007e
#define DSC2B3_DSC_DIAG_CTRL0_HOFFSET_ALIGN                        0
#define DSC2B3_DSC_DIAG_CTRL0_HOFFSET_BITS                         6
#define DSC2B3_DSC_DIAG_CTRL0_HOFFSET_SHIFT                        1

/* Dsc2b3 :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */
#define DSC2B3_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK                  0x0001
#define DSC2B3_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN                 0
#define DSC2B3_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS                  1
#define DSC2B3_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT                 0


/****************************************************************************
 * Dsc2b3 :: dsc_misc_ctrl0
 ***************************************************************************/
/* Dsc2b3 :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */
#define DSC2B3_DSC_MISC_CTRL0_RXSEQSTART_MASK                      0x8000
#define DSC2B3_DSC_MISC_CTRL0_RXSEQSTART_ALIGN                     0
#define DSC2B3_DSC_MISC_CTRL0_RXSEQSTART_BITS                      1
#define DSC2B3_DSC_MISC_CTRL0_RXSEQSTART_SHIFT                     15

/* Dsc2b3 :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */
#define DSC2B3_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK                  0x4000
#define DSC2B3_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN                 0
#define DSC2B3_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS                  1
#define DSC2B3_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT                 14

/* Dsc2b3 :: dsc_misc_ctrl0 :: enable_acor_picw [13:13] */
#define DSC2B3_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_MASK                0x2000
#define DSC2B3_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_ALIGN               0
#define DSC2B3_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_BITS                1
#define DSC2B3_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_SHIFT               13

/* Dsc2b3 :: dsc_misc_ctrl0 :: reserved_for_eco0 [12:10] */
#define DSC2B3_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_MASK               0x1c00
#define DSC2B3_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC2B3_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_BITS               3
#define DSC2B3_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_SHIFT              10

/* Dsc2b3 :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */
#define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK                 0x0200
#define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN                0
#define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS                 1
#define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT                9

/* Dsc2b3 :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */
#define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK             0x0100
#define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN            0
#define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS             1
#define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT            8

/* Dsc2b3 :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */
#define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK                  0x0080
#define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN                 0
#define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS                  1
#define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT                 7

/* Dsc2b3 :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */
#define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK              0x0070
#define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN             0
#define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS              3
#define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT             4

/* Dsc2b3 :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */
#define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK                    0x000f
#define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN                   0
#define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS                    4
#define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT                   0
#define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_Off                     0
#define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data                1
#define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1             2
#define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1           3
#define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco             4
#define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg                 6
#define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr             7
#define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd           8
#define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe            9
#define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum               10


/****************************************************************************
 * Hypercore_USER_Dsc2bB
 ***************************************************************************/
/****************************************************************************
 * Dsc2bB :: sm_ctrl0
 ***************************************************************************/
/* Dsc2bB :: sm_ctrl0 :: reserved_for_eco0 [15:15] */
#define DSC2BB_SM_CTRL0_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2BB_SM_CTRL0_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2BB_SM_CTRL0_RESERVED_FOR_ECO0_BITS                     1
#define DSC2BB_SM_CTRL0_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2bB :: sm_ctrl0 :: bypass_tx_postc_cal [14:14] */
#define DSC2BB_SM_CTRL0_BYPASS_TX_POSTC_CAL_MASK                   0x4000
#define DSC2BB_SM_CTRL0_BYPASS_TX_POSTC_CAL_ALIGN                  0
#define DSC2BB_SM_CTRL0_BYPASS_TX_POSTC_CAL_BITS                   1
#define DSC2BB_SM_CTRL0_BYPASS_TX_POSTC_CAL_SHIFT                  14

/* Dsc2bB :: sm_ctrl0 :: bypass_br_vga [13:13] */
#define DSC2BB_SM_CTRL0_BYPASS_BR_VGA_MASK                         0x2000
#define DSC2BB_SM_CTRL0_BYPASS_BR_VGA_ALIGN                        0
#define DSC2BB_SM_CTRL0_BYPASS_BR_VGA_BITS                         1
#define DSC2BB_SM_CTRL0_BYPASS_BR_VGA_SHIFT                        13

/* Dsc2bB :: sm_ctrl0 :: postc_metric_ctrl [12:12] */
#define DSC2BB_SM_CTRL0_POSTC_METRIC_CTRL_MASK                     0x1000
#define DSC2BB_SM_CTRL0_POSTC_METRIC_CTRL_ALIGN                    0
#define DSC2BB_SM_CTRL0_POSTC_METRIC_CTRL_BITS                     1
#define DSC2BB_SM_CTRL0_POSTC_METRIC_CTRL_SHIFT                    12

/* Dsc2bB :: sm_ctrl0 :: hysteresis_en [11:11] */
#define DSC2BB_SM_CTRL0_HYSTERESIS_EN_MASK                         0x0800
#define DSC2BB_SM_CTRL0_HYSTERESIS_EN_ALIGN                        0
#define DSC2BB_SM_CTRL0_HYSTERESIS_EN_BITS                         1
#define DSC2BB_SM_CTRL0_HYSTERESIS_EN_SHIFT                        11

/* Dsc2bB :: sm_ctrl0 :: slicer_cal_linear_srch [10:10] */
#define DSC2BB_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_MASK                0x0400
#define DSC2BB_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_ALIGN               0
#define DSC2BB_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_BITS                1
#define DSC2BB_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_SHIFT               10

/* Dsc2bB :: sm_ctrl0 :: bypass_br_pf_cal [09:09] */
#define DSC2BB_SM_CTRL0_BYPASS_BR_PF_CAL_MASK                      0x0200
#define DSC2BB_SM_CTRL0_BYPASS_BR_PF_CAL_ALIGN                     0
#define DSC2BB_SM_CTRL0_BYPASS_BR_PF_CAL_BITS                      1
#define DSC2BB_SM_CTRL0_BYPASS_BR_PF_CAL_SHIFT                     9

/* Dsc2bB :: sm_ctrl0 :: bypass_osx2_pf_cal [08:08] */
#define DSC2BB_SM_CTRL0_BYPASS_OSX2_PF_CAL_MASK                    0x0100
#define DSC2BB_SM_CTRL0_BYPASS_OSX2_PF_CAL_ALIGN                   0
#define DSC2BB_SM_CTRL0_BYPASS_OSX2_PF_CAL_BITS                    1
#define DSC2BB_SM_CTRL0_BYPASS_OSX2_PF_CAL_SHIFT                   8

/* Dsc2bB :: sm_ctrl0 :: bypass_osx1_pf_cal [07:07] */
#define DSC2BB_SM_CTRL0_BYPASS_OSX1_PF_CAL_MASK                    0x0080
#define DSC2BB_SM_CTRL0_BYPASS_OSX1_PF_CAL_ALIGN                   0
#define DSC2BB_SM_CTRL0_BYPASS_OSX1_PF_CAL_BITS                    1
#define DSC2BB_SM_CTRL0_BYPASS_OSX1_PF_CAL_SHIFT                   7

/* Dsc2bB :: sm_ctrl0 :: bypass_data_slicer_recal [06:06] */
#define DSC2BB_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_MASK              0x0040
#define DSC2BB_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_ALIGN             0
#define DSC2BB_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_BITS              1
#define DSC2BB_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_SHIFT             6

/* Dsc2bB :: sm_ctrl0 :: bypass_osx45_slicer_cal [05:05] */
#define DSC2BB_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_MASK               0x0020
#define DSC2BB_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_ALIGN              0
#define DSC2BB_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_BITS               1
#define DSC2BB_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_SHIFT              5

/* Dsc2bB :: sm_ctrl0 :: bypass_phase_slicer_cal [04:04] */
#define DSC2BB_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_MASK               0x0010
#define DSC2BB_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_ALIGN              0
#define DSC2BB_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_BITS               1
#define DSC2BB_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_SHIFT              4

/* Dsc2bB :: sm_ctrl0 :: bypass_br_data_slicer_cal [03:03] */
#define DSC2BB_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_MASK             0x0008
#define DSC2BB_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_ALIGN            0
#define DSC2BB_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_BITS             1
#define DSC2BB_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_SHIFT            3

/* Dsc2bB :: sm_ctrl0 :: bypass_os_data_slicer_cal [02:02] */
#define DSC2BB_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_MASK             0x0004
#define DSC2BB_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_ALIGN            0
#define DSC2BB_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_BITS             1
#define DSC2BB_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_SHIFT            2

/* Dsc2bB :: sm_ctrl0 :: restart_tuning [01:01] */
#define DSC2BB_SM_CTRL0_RESTART_TUNING_MASK                        0x0002
#define DSC2BB_SM_CTRL0_RESTART_TUNING_ALIGN                       0
#define DSC2BB_SM_CTRL0_RESTART_TUNING_BITS                        1
#define DSC2BB_SM_CTRL0_RESTART_TUNING_SHIFT                       1

/* Dsc2bB :: sm_ctrl0 :: tuning_sm_en [00:00] */
#define DSC2BB_SM_CTRL0_TUNING_SM_EN_MASK                          0x0001
#define DSC2BB_SM_CTRL0_TUNING_SM_EN_ALIGN                         0
#define DSC2BB_SM_CTRL0_TUNING_SM_EN_BITS                          1
#define DSC2BB_SM_CTRL0_TUNING_SM_EN_SHIFT                         0


/****************************************************************************
 * Dsc2bB :: sm_ctrl1
 ***************************************************************************/
/* Dsc2bB :: sm_ctrl1 :: fast_timer [15:15] */
#define DSC2BB_SM_CTRL1_FAST_TIMER_MASK                            0x8000
#define DSC2BB_SM_CTRL1_FAST_TIMER_ALIGN                           0
#define DSC2BB_SM_CTRL1_FAST_TIMER_BITS                            1
#define DSC2BB_SM_CTRL1_FAST_TIMER_SHIFT                           15

/* Dsc2bB :: sm_ctrl1 :: acq2_timeout [14:10] */
#define DSC2BB_SM_CTRL1_ACQ2_TIMEOUT_MASK                          0x7c00
#define DSC2BB_SM_CTRL1_ACQ2_TIMEOUT_ALIGN                         0
#define DSC2BB_SM_CTRL1_ACQ2_TIMEOUT_BITS                          5
#define DSC2BB_SM_CTRL1_ACQ2_TIMEOUT_SHIFT                         10

/* Dsc2bB :: sm_ctrl1 :: acq1_timeout [09:05] */
#define DSC2BB_SM_CTRL1_ACQ1_TIMEOUT_MASK                          0x03e0
#define DSC2BB_SM_CTRL1_ACQ1_TIMEOUT_ALIGN                         0
#define DSC2BB_SM_CTRL1_ACQ1_TIMEOUT_BITS                          5
#define DSC2BB_SM_CTRL1_ACQ1_TIMEOUT_SHIFT                         5

/* Dsc2bB :: sm_ctrl1 :: acqcdr_timeout [04:00] */
#define DSC2BB_SM_CTRL1_ACQCDR_TIMEOUT_MASK                        0x001f
#define DSC2BB_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN                       0
#define DSC2BB_SM_CTRL1_ACQCDR_TIMEOUT_BITS                        5
#define DSC2BB_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT                       0


/****************************************************************************
 * Dsc2bB :: sm_ctrl2
 ***************************************************************************/
/* Dsc2bB :: sm_ctrl2 :: acqvga_timeout [15:11] */
#define DSC2BB_SM_CTRL2_ACQVGA_TIMEOUT_MASK                        0xf800
#define DSC2BB_SM_CTRL2_ACQVGA_TIMEOUT_ALIGN                       0
#define DSC2BB_SM_CTRL2_ACQVGA_TIMEOUT_BITS                        5
#define DSC2BB_SM_CTRL2_ACQVGA_TIMEOUT_SHIFT                       11

/* Dsc2bB :: sm_ctrl2 :: bypass_os_integ_xfer [10:10] */
#define DSC2BB_SM_CTRL2_BYPASS_OS_INTEG_XFER_MASK                  0x0400
#define DSC2BB_SM_CTRL2_BYPASS_OS_INTEG_XFER_ALIGN                 0
#define DSC2BB_SM_CTRL2_BYPASS_OS_INTEG_XFER_BITS                  1
#define DSC2BB_SM_CTRL2_BYPASS_OS_INTEG_XFER_SHIFT                 10

/* Dsc2bB :: sm_ctrl2 :: vga_frzval [09:09] */
#define DSC2BB_SM_CTRL2_VGA_FRZVAL_MASK                            0x0200
#define DSC2BB_SM_CTRL2_VGA_FRZVAL_ALIGN                           0
#define DSC2BB_SM_CTRL2_VGA_FRZVAL_BITS                            1
#define DSC2BB_SM_CTRL2_VGA_FRZVAL_SHIFT                           9

/* Dsc2bB :: sm_ctrl2 :: vga_frcfrz [08:08] */
#define DSC2BB_SM_CTRL2_VGA_FRCFRZ_MASK                            0x0100
#define DSC2BB_SM_CTRL2_VGA_FRCFRZ_ALIGN                           0
#define DSC2BB_SM_CTRL2_VGA_FRCFRZ_BITS                            1
#define DSC2BB_SM_CTRL2_VGA_FRCFRZ_SHIFT                           8

/* Dsc2bB :: sm_ctrl2 :: dfe_frzval [07:07] */
#define DSC2BB_SM_CTRL2_DFE_FRZVAL_MASK                            0x0080
#define DSC2BB_SM_CTRL2_DFE_FRZVAL_ALIGN                           0
#define DSC2BB_SM_CTRL2_DFE_FRZVAL_BITS                            1
#define DSC2BB_SM_CTRL2_DFE_FRZVAL_SHIFT                           7

/* Dsc2bB :: sm_ctrl2 :: dfe_frcfrz [06:06] */
#define DSC2BB_SM_CTRL2_DFE_FRCFRZ_MASK                            0x0040
#define DSC2BB_SM_CTRL2_DFE_FRCFRZ_ALIGN                           0
#define DSC2BB_SM_CTRL2_DFE_FRCFRZ_BITS                            1
#define DSC2BB_SM_CTRL2_DFE_FRCFRZ_SHIFT                           6

/* Dsc2bB :: sm_ctrl2 :: dsc_clr_val [05:05] */
#define DSC2BB_SM_CTRL2_DSC_CLR_VAL_MASK                           0x0020
#define DSC2BB_SM_CTRL2_DSC_CLR_VAL_ALIGN                          0
#define DSC2BB_SM_CTRL2_DSC_CLR_VAL_BITS                           1
#define DSC2BB_SM_CTRL2_DSC_CLR_VAL_SHIFT                          5

/* Dsc2bB :: sm_ctrl2 :: dsc_clr_frc [04:04] */
#define DSC2BB_SM_CTRL2_DSC_CLR_FRC_MASK                           0x0010
#define DSC2BB_SM_CTRL2_DSC_CLR_FRC_ALIGN                          0
#define DSC2BB_SM_CTRL2_DSC_CLR_FRC_BITS                           1
#define DSC2BB_SM_CTRL2_DSC_CLR_FRC_SHIFT                          4

/* Dsc2bB :: sm_ctrl2 :: train2_req [03:03] */
#define DSC2BB_SM_CTRL2_TRAIN2_REQ_MASK                            0x0008
#define DSC2BB_SM_CTRL2_TRAIN2_REQ_ALIGN                           0
#define DSC2BB_SM_CTRL2_TRAIN2_REQ_BITS                            1
#define DSC2BB_SM_CTRL2_TRAIN2_REQ_SHIFT                           3

/* Dsc2bB :: sm_ctrl2 :: train1_req [02:02] */
#define DSC2BB_SM_CTRL2_TRAIN1_REQ_MASK                            0x0004
#define DSC2BB_SM_CTRL2_TRAIN1_REQ_ALIGN                           0
#define DSC2BB_SM_CTRL2_TRAIN1_REQ_BITS                            1
#define DSC2BB_SM_CTRL2_TRAIN1_REQ_SHIFT                           2

/* Dsc2bB :: sm_ctrl2 :: soft_ack [01:01] */
#define DSC2BB_SM_CTRL2_SOFT_ACK_MASK                              0x0002
#define DSC2BB_SM_CTRL2_SOFT_ACK_ALIGN                             0
#define DSC2BB_SM_CTRL2_SOFT_ACK_BITS                              1
#define DSC2BB_SM_CTRL2_SOFT_ACK_SHIFT                             1

/* Dsc2bB :: sm_ctrl2 :: train_mode_en [00:00] */
#define DSC2BB_SM_CTRL2_TRAIN_MODE_EN_MASK                         0x0001
#define DSC2BB_SM_CTRL2_TRAIN_MODE_EN_ALIGN                        0
#define DSC2BB_SM_CTRL2_TRAIN_MODE_EN_BITS                         1
#define DSC2BB_SM_CTRL2_TRAIN_MODE_EN_SHIFT                        0


/****************************************************************************
 * Dsc2bB :: sm_ctrl3
 ***************************************************************************/
/* Dsc2bB :: sm_ctrl3 :: reserved_for_eco0 [15:15] */
#define DSC2BB_SM_CTRL3_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2BB_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2BB_SM_CTRL3_RESERVED_FOR_ECO0_BITS                     1
#define DSC2BB_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2bB :: sm_ctrl3 :: cdrbr_bwsel_prop_acqcdr [14:12] */
#define DSC2BB_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_MASK               0x7000
#define DSC2BB_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_ALIGN              0
#define DSC2BB_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_BITS               3
#define DSC2BB_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_SHIFT              12

/* Dsc2bB :: sm_ctrl3 :: dfe_gain_acq2 [11:10] */
#define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ2_MASK                         0x0c00
#define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN                        0
#define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ2_BITS                         2
#define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT                        10

/* Dsc2bB :: sm_ctrl3 :: dfe_gain_acq1 [09:08] */
#define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ1_MASK                         0x0300
#define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN                        0
#define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ1_BITS                         2
#define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT                        8

/* Dsc2bB :: sm_ctrl3 :: vga_gain_acq2 [07:06] */
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ2_MASK                         0x00c0
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN                        0
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ2_BITS                         2
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT                        6

/* Dsc2bB :: sm_ctrl3 :: vga_gain_acq1 [05:04] */
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ1_MASK                         0x0030
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN                        0
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ1_BITS                         2
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT                        4

/* Dsc2bB :: sm_ctrl3 :: vga_gain_acqcdr [03:02] */
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQCDR_MASK                       0x000c
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN                      0
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQCDR_BITS                       2
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT                      2

/* Dsc2bB :: sm_ctrl3 :: vga_gain_acqvga [01:00] */
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQVGA_MASK                       0x0003
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN                      0
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQVGA_BITS                       2
#define DSC2BB_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT                      0


/****************************************************************************
 * Dsc2bB :: sm_ctrl4
 ***************************************************************************/
/* Dsc2bB :: sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */
#define DSC2BB_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK             0xc000
#define DSC2BB_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN            0
#define DSC2BB_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS             2
#define DSC2BB_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT            14

/* Dsc2bB :: sm_ctrl4 :: cdros45_bwsel_integ_offset [13:12] */
#define DSC2BB_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_MASK            0x3000
#define DSC2BB_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_ALIGN           0
#define DSC2BB_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_BITS            2
#define DSC2BB_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_SHIFT           12

/* Dsc2bB :: sm_ctrl4 :: cdrbr_bwsel_integ_acq2 [11:10] */
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_MASK                0x0c00
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_ALIGN               0
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_BITS                2
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_SHIFT               10

/* Dsc2bB :: sm_ctrl4 :: cdrbr_bwsel_integ_acq1 [09:08] */
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_MASK                0x0300
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_ALIGN               0
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_BITS                2
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_SHIFT               8

/* Dsc2bB :: sm_ctrl4 :: cdrbr_bwsel_integ_acqcdr [07:06] */
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_MASK              0x00c0
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN             0
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_BITS              2
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT             6

/* Dsc2bB :: sm_ctrl4 :: cdrbr_bwsel_prop_acq2 [05:03] */
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_MASK                 0x0038
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_ALIGN                0
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_BITS                 3
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_SHIFT                3

/* Dsc2bB :: sm_ctrl4 :: cdrbr_bwsel_prop_acq1 [02:00] */
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_MASK                 0x0007
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_ALIGN                0
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_BITS                 3
#define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_SHIFT                0


/****************************************************************************
 * Dsc2bB :: sm_ctrl5
 ***************************************************************************/
/* Dsc2bB :: sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [15:12] */
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK              0xf000
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN             0
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS              4
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT             12

/* Dsc2bB :: sm_ctrl5 :: cdros_bwsel_integ_acqcdr [11:08] */
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK              0x0f00
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN             0
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS              4
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT             8

/* Dsc2bB :: sm_ctrl5 :: cdros_bwsel_prop_acq1_2 [07:04] */
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_MASK               0x00f0
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_ALIGN              0
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_BITS               4
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_SHIFT              4

/* Dsc2bB :: sm_ctrl5 :: cdros_bwsel_prop_acqcdr [03:00] */
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_MASK               0x000f
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_ALIGN              0
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_BITS               4
#define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_SHIFT              0


/****************************************************************************
 * Dsc2bB :: sm_ctrl6
 ***************************************************************************/
/* Dsc2bB :: sm_ctrl6 :: reserved_for_eco0 [15:13] */
#define DSC2BB_SM_CTRL6_RESERVED_FOR_ECO0_MASK                     0xe000
#define DSC2BB_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2BB_SM_CTRL6_RESERVED_FOR_ECO0_BITS                     3
#define DSC2BB_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT                    13

/* Dsc2bB :: sm_ctrl6 :: cdrbr_bwsel_integ_acqphase [12:11] */
#define DSC2BB_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_MASK            0x1800
#define DSC2BB_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN           0
#define DSC2BB_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_BITS            2
#define DSC2BB_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT           11

/* Dsc2bB :: sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [10:08] */
#define DSC2BB_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK             0x0700
#define DSC2BB_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN            0
#define DSC2BB_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS             3
#define DSC2BB_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT            8

/* Dsc2bB :: sm_ctrl6 :: cdros_bwsel_integ_acqvga [07:04] */
#define DSC2BB_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_MASK              0x00f0
#define DSC2BB_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_ALIGN             0
#define DSC2BB_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_BITS              4
#define DSC2BB_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_SHIFT             4

/* Dsc2bB :: sm_ctrl6 :: cdros_bwsel_prop_acqvga [03:00] */
#define DSC2BB_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_MASK               0x000f
#define DSC2BB_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_ALIGN              0
#define DSC2BB_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_BITS               4
#define DSC2BB_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_SHIFT              0


/****************************************************************************
 * Dsc2bB :: sm_ctrl7
 ***************************************************************************/
/* Dsc2bB :: sm_ctrl7 :: reserved_for_eco0 [15:15] */
#define DSC2BB_SM_CTRL7_RESERVED_FOR_ECO0_MASK                     0x8000
#define DSC2BB_SM_CTRL7_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2BB_SM_CTRL7_RESERVED_FOR_ECO0_BITS                     1
#define DSC2BB_SM_CTRL7_RESERVED_FOR_ECO0_SHIFT                    15

/* Dsc2bB :: sm_ctrl7 :: pf_ctrl_br_offset [14:12] */
#define DSC2BB_SM_CTRL7_PF_CTRL_BR_OFFSET_MASK                     0x7000
#define DSC2BB_SM_CTRL7_PF_CTRL_BR_OFFSET_ALIGN                    0
#define DSC2BB_SM_CTRL7_PF_CTRL_BR_OFFSET_BITS                     3
#define DSC2BB_SM_CTRL7_PF_CTRL_BR_OFFSET_SHIFT                    12

/* Dsc2bB :: sm_ctrl7 :: pf_ctrl_osx1_offset [11:09] */
#define DSC2BB_SM_CTRL7_PF_CTRL_OSX1_OFFSET_MASK                   0x0e00
#define DSC2BB_SM_CTRL7_PF_CTRL_OSX1_OFFSET_ALIGN                  0
#define DSC2BB_SM_CTRL7_PF_CTRL_OSX1_OFFSET_BITS                   3
#define DSC2BB_SM_CTRL7_PF_CTRL_OSX1_OFFSET_SHIFT                  9

/* Dsc2bB :: sm_ctrl7 :: pf_ctrl_osx2_offset [08:06] */
#define DSC2BB_SM_CTRL7_PF_CTRL_OSX2_OFFSET_MASK                   0x01c0
#define DSC2BB_SM_CTRL7_PF_CTRL_OSX2_OFFSET_ALIGN                  0
#define DSC2BB_SM_CTRL7_PF_CTRL_OSX2_OFFSET_BITS                   3
#define DSC2BB_SM_CTRL7_PF_CTRL_OSX2_OFFSET_SHIFT                  6

/* Dsc2bB :: sm_ctrl7 :: pf_ctrl_br_init [05:03] */
#define DSC2BB_SM_CTRL7_PF_CTRL_BR_INIT_MASK                       0x0038
#define DSC2BB_SM_CTRL7_PF_CTRL_BR_INIT_ALIGN                      0
#define DSC2BB_SM_CTRL7_PF_CTRL_BR_INIT_BITS                       3
#define DSC2BB_SM_CTRL7_PF_CTRL_BR_INIT_SHIFT                      3

/* Dsc2bB :: sm_ctrl7 :: pf_ctrl_os_init [02:00] */
#define DSC2BB_SM_CTRL7_PF_CTRL_OS_INIT_MASK                       0x0007
#define DSC2BB_SM_CTRL7_PF_CTRL_OS_INIT_ALIGN                      0
#define DSC2BB_SM_CTRL7_PF_CTRL_OS_INIT_BITS                       3
#define DSC2BB_SM_CTRL7_PF_CTRL_OS_INIT_SHIFT                      0


/****************************************************************************
 * Dsc2bB :: sm_ctrl8
 ***************************************************************************/
/* Dsc2bB :: sm_ctrl8 :: reserved_for_eco0 [15:10] */
#define DSC2BB_SM_CTRL8_RESERVED_FOR_ECO0_MASK                     0xfc00
#define DSC2BB_SM_CTRL8_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2BB_SM_CTRL8_RESERVED_FOR_ECO0_BITS                     6
#define DSC2BB_SM_CTRL8_RESERVED_FOR_ECO0_SHIFT                    10

/* Dsc2bB :: sm_ctrl8 :: vga_max_val [09:05] */
#define DSC2BB_SM_CTRL8_VGA_MAX_VAL_MASK                           0x03e0
#define DSC2BB_SM_CTRL8_VGA_MAX_VAL_ALIGN                          0
#define DSC2BB_SM_CTRL8_VGA_MAX_VAL_BITS                           5
#define DSC2BB_SM_CTRL8_VGA_MAX_VAL_SHIFT                          5

/* Dsc2bB :: sm_ctrl8 :: vga_min_val [04:00] */
#define DSC2BB_SM_CTRL8_VGA_MIN_VAL_MASK                           0x001f
#define DSC2BB_SM_CTRL8_VGA_MIN_VAL_ALIGN                          0
#define DSC2BB_SM_CTRL8_VGA_MIN_VAL_BITS                           5
#define DSC2BB_SM_CTRL8_VGA_MIN_VAL_SHIFT                          0


/****************************************************************************
 * Dsc2bB :: sm_ctrl9
 ***************************************************************************/
/* Dsc2bB :: sm_ctrl9 :: reserved_for_eco0 [15:12] */
#define DSC2BB_SM_CTRL9_RESERVED_FOR_ECO0_MASK                     0xf000
#define DSC2BB_SM_CTRL9_RESERVED_FOR_ECO0_ALIGN                    0
#define DSC2BB_SM_CTRL9_RESERVED_FOR_ECO0_BITS                     4
#define DSC2BB_SM_CTRL9_RESERVED_FOR_ECO0_SHIFT                    12

/* Dsc2bB :: sm_ctrl9 :: dfe_max_val [11:06] */
#define DSC2BB_SM_CTRL9_DFE_MAX_VAL_MASK                           0x0fc0
#define DSC2BB_SM_CTRL9_DFE_MAX_VAL_ALIGN                          0
#define DSC2BB_SM_CTRL9_DFE_MAX_VAL_BITS                           6
#define DSC2BB_SM_CTRL9_DFE_MAX_VAL_SHIFT                          6

/* Dsc2bB :: sm_ctrl9 :: dfe_min_val [05:00] */
#define DSC2BB_SM_CTRL9_DFE_MIN_VAL_MASK                           0x003f
#define DSC2BB_SM_CTRL9_DFE_MIN_VAL_ALIGN                          0
#define DSC2BB_SM_CTRL9_DFE_MIN_VAL_BITS                           6
#define DSC2BB_SM_CTRL9_DFE_MIN_VAL_SHIFT                          0


/****************************************************************************
 * Dsc2bB :: sm_ctrl10
 ***************************************************************************/
/* Dsc2bB :: sm_ctrl10 :: reserved_for_eco0 [15:14] */
#define DSC2BB_SM_CTRL10_RESERVED_FOR_ECO0_MASK                    0xc000
#define DSC2BB_SM_CTRL10_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2BB_SM_CTRL10_RESERVED_FOR_ECO0_BITS                    2
#define DSC2BB_SM_CTRL10_RESERVED_FOR_ECO0_SHIFT                   14

/* Dsc2bB :: sm_ctrl10 :: br_pf_tap_en [13:07] */
#define DSC2BB_SM_CTRL10_BR_PF_TAP_EN_MASK                         0x3f80
#define DSC2BB_SM_CTRL10_BR_PF_TAP_EN_ALIGN                        0
#define DSC2BB_SM_CTRL10_BR_PF_TAP_EN_BITS                         7
#define DSC2BB_SM_CTRL10_BR_PF_TAP_EN_SHIFT                        7

/* Dsc2bB :: sm_ctrl10 :: osx1_pf_tap_en [06:00] */
#define DSC2BB_SM_CTRL10_OSX1_PF_TAP_EN_MASK                       0x007f
#define DSC2BB_SM_CTRL10_OSX1_PF_TAP_EN_ALIGN                      0
#define DSC2BB_SM_CTRL10_OSX1_PF_TAP_EN_BITS                       7
#define DSC2BB_SM_CTRL10_OSX1_PF_TAP_EN_SHIFT                      0


/****************************************************************************
 * Dsc2bB :: sm_ctrl11
 ***************************************************************************/
/* Dsc2bB :: sm_ctrl11 :: reserved_for_eco0 [15:15] */
#define DSC2BB_SM_CTRL11_RESERVED_FOR_ECO0_MASK                    0x8000
#define DSC2BB_SM_CTRL11_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2BB_SM_CTRL11_RESERVED_FOR_ECO0_BITS                    1
#define DSC2BB_SM_CTRL11_RESERVED_FOR_ECO0_SHIFT                   15

/* Dsc2bB :: sm_ctrl11 :: msr_br_vga_timeout [14:10] */
#define DSC2BB_SM_CTRL11_MSR_BR_VGA_TIMEOUT_MASK                   0x7c00
#define DSC2BB_SM_CTRL11_MSR_BR_VGA_TIMEOUT_ALIGN                  0
#define DSC2BB_SM_CTRL11_MSR_BR_VGA_TIMEOUT_BITS                   5
#define DSC2BB_SM_CTRL11_MSR_BR_VGA_TIMEOUT_SHIFT                  10

/* Dsc2bB :: sm_ctrl11 :: hysteresis_timeout [09:05] */
#define DSC2BB_SM_CTRL11_HYSTERESIS_TIMEOUT_MASK                   0x03e0
#define DSC2BB_SM_CTRL11_HYSTERESIS_TIMEOUT_ALIGN                  0
#define DSC2BB_SM_CTRL11_HYSTERESIS_TIMEOUT_BITS                   5
#define DSC2BB_SM_CTRL11_HYSTERESIS_TIMEOUT_SHIFT                  5

/* Dsc2bB :: sm_ctrl11 :: msr_postc_timeout [04:00] */
#define DSC2BB_SM_CTRL11_MSR_POSTC_TIMEOUT_MASK                    0x001f
#define DSC2BB_SM_CTRL11_MSR_POSTC_TIMEOUT_ALIGN                   0
#define DSC2BB_SM_CTRL11_MSR_POSTC_TIMEOUT_BITS                    5
#define DSC2BB_SM_CTRL11_MSR_POSTC_TIMEOUT_SHIFT                   0


/****************************************************************************
 * Dsc2bB :: sm_ctrl12
 ***************************************************************************/
/* Dsc2bB :: sm_ctrl12 :: reserved_for_eco0 [15:14] */
#define DSC2BB_SM_CTRL12_RESERVED_FOR_ECO0_MASK                    0xc000
#define DSC2BB_SM_CTRL12_RESERVED_FOR_ECO0_ALIGN                   0
#define DSC2BB_SM_CTRL12_RESERVED_FOR_ECO0_BITS                    2
#define DSC2BB_SM_CTRL12_RESERVED_FOR_ECO0_SHIFT                   14

/* Dsc2bB :: sm_ctrl12 :: br_vga_lms_gain [13:12] */
#define DSC2BB_SM_CTRL12_BR_VGA_LMS_GAIN_MASK                      0x3000
#define DSC2BB_SM_CTRL12_BR_VGA_LMS_GAIN_ALIGN                     0
#define DSC2BB_SM_CTRL12_BR_VGA_LMS_GAIN_BITS                      2
#define DSC2BB_SM_CTRL12_BR_VGA_LMS_GAIN_SHIFT                     12

/* Dsc2bB :: sm_ctrl12 :: postc_dfe_lms_gain [11:10] */
#define DSC2BB_SM_CTRL12_POSTC_DFE_LMS_GAIN_MASK                   0x0c00
#define DSC2BB_SM_CTRL12_POSTC_DFE_LMS_GAIN_ALIGN                  0
#define DSC2BB_SM_CTRL12_POSTC_DFE_LMS_GAIN_BITS                   2
#define DSC2BB_SM_CTRL12_POSTC_DFE_LMS_GAIN_SHIFT                  10

/* Dsc2bB :: sm_ctrl12 :: cdr_phase_inversion_timeout [09:05] */
#define DSC2BB_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_MASK          0x03e0
#define DSC2BB_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_ALIGN         0
#define DSC2BB_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_BITS          5
#define DSC2BB_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_SHIFT         5

/* Dsc2bB :: sm_ctrl12 :: msr_pf_timeout [04:00] */
#define DSC2BB_SM_CTRL12_MSR_PF_TIMEOUT_MASK                       0x001f
#define DSC2BB_SM_CTRL12_MSR_PF_TIMEOUT_ALIGN                      0
#define DSC2BB_SM_CTRL12_MSR_PF_TIMEOUT_BITS                       5
#define DSC2BB_SM_CTRL12_MSR_PF_TIMEOUT_SHIFT                      0


/****************************************************************************
 * Dsc2bB :: dsc_diag_ctrl0
 ***************************************************************************/
/* Dsc2bB :: dsc_diag_ctrl0 :: reserved_for_eco0 [15:11] */
#define DSC2BB_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_MASK               0xf800
#define DSC2BB_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC2BB_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_BITS               5
#define DSC2BB_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_SHIFT              11

/* Dsc2bB :: dsc_diag_ctrl0 :: voffset [10:07] */
#define DSC2BB_DSC_DIAG_CTRL0_VOFFSET_MASK                         0x0780
#define DSC2BB_DSC_DIAG_CTRL0_VOFFSET_ALIGN                        0
#define DSC2BB_DSC_DIAG_CTRL0_VOFFSET_BITS                         4
#define DSC2BB_DSC_DIAG_CTRL0_VOFFSET_SHIFT                        7

/* Dsc2bB :: dsc_diag_ctrl0 :: hoffset [06:01] */
#define DSC2BB_DSC_DIAG_CTRL0_HOFFSET_MASK                         0x007e
#define DSC2BB_DSC_DIAG_CTRL0_HOFFSET_ALIGN                        0
#define DSC2BB_DSC_DIAG_CTRL0_HOFFSET_BITS                         6
#define DSC2BB_DSC_DIAG_CTRL0_HOFFSET_SHIFT                        1

/* Dsc2bB :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */
#define DSC2BB_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK                  0x0001
#define DSC2BB_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN                 0
#define DSC2BB_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS                  1
#define DSC2BB_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT                 0


/****************************************************************************
 * Dsc2bB :: dsc_misc_ctrl0
 ***************************************************************************/
/* Dsc2bB :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */
#define DSC2BB_DSC_MISC_CTRL0_RXSEQSTART_MASK                      0x8000
#define DSC2BB_DSC_MISC_CTRL0_RXSEQSTART_ALIGN                     0
#define DSC2BB_DSC_MISC_CTRL0_RXSEQSTART_BITS                      1
#define DSC2BB_DSC_MISC_CTRL0_RXSEQSTART_SHIFT                     15

/* Dsc2bB :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */
#define DSC2BB_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK                  0x4000
#define DSC2BB_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN                 0
#define DSC2BB_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS                  1
#define DSC2BB_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT                 14

/* Dsc2bB :: dsc_misc_ctrl0 :: enable_acor_picw [13:13] */
#define DSC2BB_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_MASK                0x2000
#define DSC2BB_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_ALIGN               0
#define DSC2BB_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_BITS                1
#define DSC2BB_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_SHIFT               13

/* Dsc2bB :: dsc_misc_ctrl0 :: reserved_for_eco0 [12:10] */
#define DSC2BB_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_MASK               0x1c00
#define DSC2BB_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_ALIGN              0
#define DSC2BB_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_BITS               3
#define DSC2BB_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_SHIFT              10

/* Dsc2bB :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */
#define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK                 0x0200
#define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN                0
#define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS                 1
#define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT                9

/* Dsc2bB :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */
#define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK             0x0100
#define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN            0
#define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS             1
#define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT            8

/* Dsc2bB :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */
#define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK                  0x0080
#define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN                 0
#define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS                  1
#define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT                 7

/* Dsc2bB :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */
#define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK              0x0070
#define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN             0
#define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS              3
#define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT             4

/* Dsc2bB :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */
#define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK                    0x000f
#define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN                   0
#define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS                    4
#define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT                   0
#define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_Off                     0
#define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data                1
#define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1             2
#define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1           3
#define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco             4
#define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg                 6
#define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr             7
#define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd           8
#define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe            9
#define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum               10


/****************************************************************************
 * Hypercore_USER_Dsc3b0
 ***************************************************************************/
/****************************************************************************
 * Dsc3b0 :: cdr_status0
 ***************************************************************************/
/* Dsc3b0 :: cdr_status0 :: integ_reg [15:00] */
#define DSC3B0_CDR_STATUS0_INTEG_REG_MASK                          0xffff
#define DSC3B0_CDR_STATUS0_INTEG_REG_ALIGN                         0
#define DSC3B0_CDR_STATUS0_INTEG_REG_BITS                          16
#define DSC3B0_CDR_STATUS0_INTEG_REG_SHIFT                         0


/****************************************************************************
 * Dsc3b0 :: cdr_status1
 ***************************************************************************/
/* Dsc3b0 :: cdr_status1 :: integ_reg_xfer [15:00] */
#define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_MASK                     0xffff
#define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_ALIGN                    0
#define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_BITS                     16
#define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_SHIFT                    0


/****************************************************************************
 * Dsc3b0 :: cdr_status2
 ***************************************************************************/
/* Dsc3b0 :: cdr_status2 :: reserved_for_eco0 [15:11] */
#define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_MASK                  0xf800
#define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_BITS                  5
#define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_SHIFT                 11

/* Dsc3b0 :: cdr_status2 :: sm_br_cdr_enabled [10:10] */
#define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_MASK                  0x0400
#define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_ALIGN                 0
#define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_BITS                  1
#define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_SHIFT                 10

/* Dsc3b0 :: cdr_status2 :: br_cdr_enabled [09:09] */
#define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_MASK                     0x0200
#define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_ALIGN                    0
#define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_BITS                     1
#define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_SHIFT                    9

/* Dsc3b0 :: cdr_status2 :: oscdr_mode [08:06] */
#define DSC3B0_CDR_STATUS2_OSCDR_MODE_MASK                         0x01c0
#define DSC3B0_CDR_STATUS2_OSCDR_MODE_ALIGN                        0
#define DSC3B0_CDR_STATUS2_OSCDR_MODE_BITS                         3
#define DSC3B0_CDR_STATUS2_OSCDR_MODE_SHIFT                        6

/* Dsc3b0 :: cdr_status2 :: phase_err [05:00] */
#define DSC3B0_CDR_STATUS2_PHASE_ERR_MASK                          0x003f
#define DSC3B0_CDR_STATUS2_PHASE_ERR_ALIGN                         0
#define DSC3B0_CDR_STATUS2_PHASE_ERR_BITS                          6
#define DSC3B0_CDR_STATUS2_PHASE_ERR_SHIFT                         0


/****************************************************************************
 * Dsc3b0 :: pi_status0
 ***************************************************************************/
/* Dsc3b0 :: pi_status0 :: invalid_intrp_ctrl0 [15:15] */
#define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL0_MASK                 0x8000
#define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL0_ALIGN                0
#define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL0_BITS                 1
#define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL0_SHIFT                15

/* Dsc3b0 :: pi_status0 :: invalid_intrp_ctrl90 [14:14] */
#define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL90_MASK                0x4000
#define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL90_ALIGN               0
#define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL90_BITS                1
#define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL90_SHIFT               14

/* Dsc3b0 :: pi_status0 :: clk90_phase_offset [13:07] */
#define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_MASK                  0x3f80
#define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN                 0
#define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_BITS                  7
#define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT                 7

/* Dsc3b0 :: pi_status0 :: phase_cntr [06:00] */
#define DSC3B0_PI_STATUS0_PHASE_CNTR_MASK                          0x007f
#define DSC3B0_PI_STATUS0_PHASE_CNTR_ALIGN                         0
#define DSC3B0_PI_STATUS0_PHASE_CNTR_BITS                          7
#define DSC3B0_PI_STATUS0_PHASE_CNTR_SHIFT                         0


/****************************************************************************
 * Dsc3b0 :: pi_status1
 ***************************************************************************/
/* union - case pi_Single0_lsb [15:00] */
/* Dsc3b0 :: pi_status1 :: Single0_lsb [15:00] */
#define DSC3B0_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_MASK          0xffff
#define DSC3B0_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_ALIGN         0
#define DSC3B0_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_BITS          16
#define DSC3B0_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_SHIFT         0


/* union - case pi_Single0_msb [15:00] */
/* Dsc3b0 :: pi_status1 :: Single0_msb [15:00] */
#define DSC3B0_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_MASK          0xffff
#define DSC3B0_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_ALIGN         0
#define DSC3B0_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_BITS          16
#define DSC3B0_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_SHIFT         0


/* union - case pi_Sequence0_lsb [15:00] */
/* Dsc3b0 :: pi_status1 :: Sequence0_lsb [15:00] */
#define DSC3B0_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_MASK      0xffff
#define DSC3B0_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_ALIGN     0
#define DSC3B0_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_BITS      16
#define DSC3B0_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_SHIFT     0


/* union - case pi_Sequence0_msb [15:00] */
/* Dsc3b0 :: pi_status1 :: Sequence0_msb [15:00] */
#define DSC3B0_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_MASK      0xffff
#define DSC3B0_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_ALIGN     0
#define DSC3B0_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_BITS      16
#define DSC3B0_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_SHIFT     0


/* union - case pi_Single90_lsb [15:00] */
/* Dsc3b0 :: pi_status1 :: Single90_lsb [15:00] */
#define DSC3B0_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_MASK        0xffff
#define DSC3B0_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_ALIGN       0
#define DSC3B0_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_BITS        16
#define DSC3B0_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_SHIFT       0


/* union - case pi_Single90_msb [15:00] */
/* Dsc3b0 :: pi_status1 :: Single90_msb [15:00] */
#define DSC3B0_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_MASK        0xffff
#define DSC3B0_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_ALIGN       0
#define DSC3B0_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_BITS        16
#define DSC3B0_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_SHIFT       0


/* union - case pi_Sequence90_lsb [15:00] */
/* Dsc3b0 :: pi_status1 :: Sequence90_lsb [15:00] */
#define DSC3B0_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_MASK    0xffff
#define DSC3B0_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_ALIGN   0
#define DSC3B0_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_BITS    16
#define DSC3B0_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_SHIFT   0


/* union - case pi_Sequence90_msb [15:00] */
/* Dsc3b0 :: pi_status1 :: Sequence90_msb [15:00] */
#define DSC3B0_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_MASK    0xffff
#define DSC3B0_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_ALIGN   0
#define DSC3B0_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_BITS    16
#define DSC3B0_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_SHIFT   0



/****************************************************************************
 * Dsc3b0 :: dfe_vga_status0
 ***************************************************************************/
/* Dsc3b0 :: dfe_vga_status0 :: reserved_for_eco0 [15:11] */
#define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_MASK              0xf800
#define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_ALIGN             0
#define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_BITS              5
#define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_SHIFT             11

/* Dsc3b0 :: dfe_vga_status0 :: vga_sum [10:06] */
#define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_MASK                        0x07c0
#define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_ALIGN                       0
#define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_BITS                        5
#define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_SHIFT                       6

/* Dsc3b0 :: dfe_vga_status0 :: dfe_tap_bin [05:00] */
#define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_BIN_MASK                    0x003f
#define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_BIN_ALIGN                   0
#define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_BIN_BITS                    6
#define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_BIN_SHIFT                   0


/****************************************************************************
 * Dsc3b0 :: dfe_vga_status1
 ***************************************************************************/
/* Dsc3b0 :: dfe_vga_status1 :: reserved_for_eco0 [15:11] */
#define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_MASK              0xf800
#define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_ALIGN             0
#define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_BITS              5
#define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_SHIFT             11

/* Dsc3b0 :: dfe_vga_status1 :: trnsum [10:00] */
#define DSC3B0_DFE_VGA_STATUS1_TRNSUM_MASK                         0x07ff
#define DSC3B0_DFE_VGA_STATUS1_TRNSUM_ALIGN                        0
#define DSC3B0_DFE_VGA_STATUS1_TRNSUM_BITS                         11
#define DSC3B0_DFE_VGA_STATUS1_TRNSUM_SHIFT                        0


/****************************************************************************
 * Dsc3b0 :: sm_status0
 ***************************************************************************/
/* Dsc3b0 :: sm_status0 :: reserved_for_eco0 [15:14] */
#define DSC3B0_SM_STATUS0_RESERVED_FOR_ECO0_MASK                   0xc000
#define DSC3B0_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B0_SM_STATUS0_RESERVED_FOR_ECO0_BITS                   2
#define DSC3B0_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT                  14

/* Dsc3b0 :: sm_status0 :: tuning_done [13:13] */
#define DSC3B0_SM_STATUS0_TUNING_DONE_MASK                         0x2000
#define DSC3B0_SM_STATUS0_TUNING_DONE_ALIGN                        0
#define DSC3B0_SM_STATUS0_TUNING_DONE_BITS                         1
#define DSC3B0_SM_STATUS0_TUNING_DONE_SHIFT                        13

/* Dsc3b0 :: sm_status0 :: srch_state [12:09] */
#define DSC3B0_SM_STATUS0_SRCH_STATE_MASK                          0x1e00
#define DSC3B0_SM_STATUS0_SRCH_STATE_ALIGN                         0
#define DSC3B0_SM_STATUS0_SRCH_STATE_BITS                          4
#define DSC3B0_SM_STATUS0_SRCH_STATE_SHIFT                         9

/* Dsc3b0 :: sm_status0 :: tuning_state [08:04] */
#define DSC3B0_SM_STATUS0_TUNING_STATE_MASK                        0x01f0
#define DSC3B0_SM_STATUS0_TUNING_STATE_ALIGN                       0
#define DSC3B0_SM_STATUS0_TUNING_STATE_BITS                        5
#define DSC3B0_SM_STATUS0_TUNING_STATE_SHIFT                       4

/* Dsc3b0 :: sm_status0 :: dsc_state [03:00] */
#define DSC3B0_SM_STATUS0_DSC_STATE_MASK                           0x000f
#define DSC3B0_SM_STATUS0_DSC_STATE_ALIGN                          0
#define DSC3B0_SM_STATUS0_DSC_STATE_BITS                           4
#define DSC3B0_SM_STATUS0_DSC_STATE_SHIFT                          0


/****************************************************************************
 * Dsc3b0 :: sm_status1
 ***************************************************************************/
/* Dsc3b0 :: sm_status1 :: reserved_for_eco0 [15:11] */
#define DSC3B0_SM_STATUS1_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3B0_SM_STATUS1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B0_SM_STATUS1_RESERVED_FOR_ECO0_BITS                   5
#define DSC3B0_SM_STATUS1_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3b0 :: sm_status1 :: postc_metric [10:00] */
#define DSC3B0_SM_STATUS1_POSTC_METRIC_MASK                        0x07ff
#define DSC3B0_SM_STATUS1_POSTC_METRIC_ALIGN                       0
#define DSC3B0_SM_STATUS1_POSTC_METRIC_BITS                        11
#define DSC3B0_SM_STATUS1_POSTC_METRIC_SHIFT                       0


/****************************************************************************
 * Dsc3b0 :: sm_status2
 ***************************************************************************/
/* Dsc3b0 :: sm_status2 :: reserved_for_eco0 [15:15] */
#define DSC3B0_SM_STATUS2_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC3B0_SM_STATUS2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B0_SM_STATUS2_RESERVED_FOR_ECO0_BITS                   1
#define DSC3B0_SM_STATUS2_RESERVED_FOR_ECO0_SHIFT                  15

/* Dsc3b0 :: sm_status2 :: slicer_offset_po [14:10] */
#define DSC3B0_SM_STATUS2_SLICER_OFFSET_PO_MASK                    0x7c00
#define DSC3B0_SM_STATUS2_SLICER_OFFSET_PO_ALIGN                   0
#define DSC3B0_SM_STATUS2_SLICER_OFFSET_PO_BITS                    5
#define DSC3B0_SM_STATUS2_SLICER_OFFSET_PO_SHIFT                   10

/* Dsc3b0 :: sm_status2 :: slicer_offset_zo [09:05] */
#define DSC3B0_SM_STATUS2_SLICER_OFFSET_ZO_MASK                    0x03e0
#define DSC3B0_SM_STATUS2_SLICER_OFFSET_ZO_ALIGN                   0
#define DSC3B0_SM_STATUS2_SLICER_OFFSET_ZO_BITS                    5
#define DSC3B0_SM_STATUS2_SLICER_OFFSET_ZO_SHIFT                   5

/* Dsc3b0 :: sm_status2 :: slicer_offset_mo [04:00] */
#define DSC3B0_SM_STATUS2_SLICER_OFFSET_MO_MASK                    0x001f
#define DSC3B0_SM_STATUS2_SLICER_OFFSET_MO_ALIGN                   0
#define DSC3B0_SM_STATUS2_SLICER_OFFSET_MO_BITS                    5
#define DSC3B0_SM_STATUS2_SLICER_OFFSET_MO_SHIFT                   0


/****************************************************************************
 * Dsc3b0 :: sm_status3
 ***************************************************************************/
/* Dsc3b0 :: sm_status3 :: reserved_for_eco0 [15:15] */
#define DSC3B0_SM_STATUS3_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC3B0_SM_STATUS3_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B0_SM_STATUS3_RESERVED_FOR_ECO0_BITS                   1
#define DSC3B0_SM_STATUS3_RESERVED_FOR_ECO0_SHIFT                  15

/* Dsc3b0 :: sm_status3 :: slicer_offset_pe [14:10] */
#define DSC3B0_SM_STATUS3_SLICER_OFFSET_PE_MASK                    0x7c00
#define DSC3B0_SM_STATUS3_SLICER_OFFSET_PE_ALIGN                   0
#define DSC3B0_SM_STATUS3_SLICER_OFFSET_PE_BITS                    5
#define DSC3B0_SM_STATUS3_SLICER_OFFSET_PE_SHIFT                   10

/* Dsc3b0 :: sm_status3 :: slicer_offset_ze [09:05] */
#define DSC3B0_SM_STATUS3_SLICER_OFFSET_ZE_MASK                    0x03e0
#define DSC3B0_SM_STATUS3_SLICER_OFFSET_ZE_ALIGN                   0
#define DSC3B0_SM_STATUS3_SLICER_OFFSET_ZE_BITS                    5
#define DSC3B0_SM_STATUS3_SLICER_OFFSET_ZE_SHIFT                   5

/* Dsc3b0 :: sm_status3 :: slicer_offset_me [04:00] */
#define DSC3B0_SM_STATUS3_SLICER_OFFSET_ME_MASK                    0x001f
#define DSC3B0_SM_STATUS3_SLICER_OFFSET_ME_ALIGN                   0
#define DSC3B0_SM_STATUS3_SLICER_OFFSET_ME_BITS                    5
#define DSC3B0_SM_STATUS3_SLICER_OFFSET_ME_SHIFT                   0


/****************************************************************************
 * Dsc3b0 :: sm_status4
 ***************************************************************************/
/* Dsc3b0 :: sm_status4 :: reserved_for_eco0 [15:09] */
#define DSC3B0_SM_STATUS4_RESERVED_FOR_ECO0_MASK                   0xfe00
#define DSC3B0_SM_STATUS4_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B0_SM_STATUS4_RESERVED_FOR_ECO0_BITS                   7
#define DSC3B0_SM_STATUS4_RESERVED_FOR_ECO0_SHIFT                  9

/* Dsc3b0 :: sm_status4 :: dfe_max [08:08] */
#define DSC3B0_SM_STATUS4_DFE_MAX_MASK                             0x0100
#define DSC3B0_SM_STATUS4_DFE_MAX_ALIGN                            0
#define DSC3B0_SM_STATUS4_DFE_MAX_BITS                             1
#define DSC3B0_SM_STATUS4_DFE_MAX_SHIFT                            8

/* Dsc3b0 :: sm_status4 :: dfe_min [07:07] */
#define DSC3B0_SM_STATUS4_DFE_MIN_MASK                             0x0080
#define DSC3B0_SM_STATUS4_DFE_MIN_ALIGN                            0
#define DSC3B0_SM_STATUS4_DFE_MIN_BITS                             1
#define DSC3B0_SM_STATUS4_DFE_MIN_SHIFT                            7

/* Dsc3b0 :: sm_status4 :: vga_max [06:06] */
#define DSC3B0_SM_STATUS4_VGA_MAX_MASK                             0x0040
#define DSC3B0_SM_STATUS4_VGA_MAX_ALIGN                            0
#define DSC3B0_SM_STATUS4_VGA_MAX_BITS                             1
#define DSC3B0_SM_STATUS4_VGA_MAX_SHIFT                            6

/* Dsc3b0 :: sm_status4 :: vga_min [05:05] */
#define DSC3B0_SM_STATUS4_VGA_MIN_MASK                             0x0020
#define DSC3B0_SM_STATUS4_VGA_MIN_ALIGN                            0
#define DSC3B0_SM_STATUS4_VGA_MIN_BITS                             1
#define DSC3B0_SM_STATUS4_VGA_MIN_SHIFT                            5

/* Dsc3b0 :: sm_status4 :: pf_max [04:04] */
#define DSC3B0_SM_STATUS4_PF_MAX_MASK                              0x0010
#define DSC3B0_SM_STATUS4_PF_MAX_ALIGN                             0
#define DSC3B0_SM_STATUS4_PF_MAX_BITS                              1
#define DSC3B0_SM_STATUS4_PF_MAX_SHIFT                             4

/* Dsc3b0 :: sm_status4 :: pf_min [03:03] */
#define DSC3B0_SM_STATUS4_PF_MIN_MASK                              0x0008
#define DSC3B0_SM_STATUS4_PF_MIN_ALIGN                             0
#define DSC3B0_SM_STATUS4_PF_MIN_BITS                              1
#define DSC3B0_SM_STATUS4_PF_MIN_SHIFT                             3

/* Dsc3b0 :: sm_status4 :: pf_ctrl [02:00] */
#define DSC3B0_SM_STATUS4_PF_CTRL_MASK                             0x0007
#define DSC3B0_SM_STATUS4_PF_CTRL_ALIGN                            0
#define DSC3B0_SM_STATUS4_PF_CTRL_BITS                             3
#define DSC3B0_SM_STATUS4_PF_CTRL_SHIFT                            0


/****************************************************************************
 * Dsc3b0 :: ana_status0
 ***************************************************************************/
/* Dsc3b0 :: ana_status0 :: reserved_for_eco0 [15:04] */
#define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_MASK                  0xfff0
#define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_BITS                  12
#define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_SHIFT                 4

/* Dsc3b0 :: ana_status0 :: pd_ch_p1 [03:03] */
#define DSC3B0_ANA_STATUS0_PD_CH_P1_MASK                           0x0008
#define DSC3B0_ANA_STATUS0_PD_CH_P1_ALIGN                          0
#define DSC3B0_ANA_STATUS0_PD_CH_P1_BITS                           1
#define DSC3B0_ANA_STATUS0_PD_CH_P1_SHIFT                          3

/* Dsc3b0 :: ana_status0 :: en_dfe_clk [02:02] */
#define DSC3B0_ANA_STATUS0_EN_DFE_CLK_MASK                         0x0004
#define DSC3B0_ANA_STATUS0_EN_DFE_CLK_ALIGN                        0
#define DSC3B0_ANA_STATUS0_EN_DFE_CLK_BITS                         1
#define DSC3B0_ANA_STATUS0_EN_DFE_CLK_SHIFT                        2

/* Dsc3b0 :: ana_status0 :: en_hgain [01:01] */
#define DSC3B0_ANA_STATUS0_EN_HGAIN_MASK                           0x0002
#define DSC3B0_ANA_STATUS0_EN_HGAIN_ALIGN                          0
#define DSC3B0_ANA_STATUS0_EN_HGAIN_BITS                           1
#define DSC3B0_ANA_STATUS0_EN_HGAIN_SHIFT                          1

/* Dsc3b0 :: ana_status0 :: offset_pd [00:00] */
#define DSC3B0_ANA_STATUS0_OFFSET_PD_MASK                          0x0001
#define DSC3B0_ANA_STATUS0_OFFSET_PD_ALIGN                         0
#define DSC3B0_ANA_STATUS0_OFFSET_PD_BITS                          1
#define DSC3B0_ANA_STATUS0_OFFSET_PD_SHIFT                         0


/****************************************************************************
 * Dsc3b0 :: sm_status5
 ***************************************************************************/
/* Dsc3b0 :: sm_status5 :: reserved_for_eco0 [15:11] */
#define DSC3B0_SM_STATUS5_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3B0_SM_STATUS5_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B0_SM_STATUS5_RESERVED_FOR_ECO0_BITS                   5
#define DSC3B0_SM_STATUS5_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3b0 :: sm_status5 :: trnsum_br_vga [10:00] */
#define DSC3B0_SM_STATUS5_TRNSUM_BR_VGA_MASK                       0x07ff
#define DSC3B0_SM_STATUS5_TRNSUM_BR_VGA_ALIGN                      0
#define DSC3B0_SM_STATUS5_TRNSUM_BR_VGA_BITS                       11
#define DSC3B0_SM_STATUS5_TRNSUM_BR_VGA_SHIFT                      0


/****************************************************************************
 * Dsc3b0 :: sm_status6
 ***************************************************************************/
/* Dsc3b0 :: sm_status6 :: reserved_for_eco0 [15:11] */
#define DSC3B0_SM_STATUS6_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3B0_SM_STATUS6_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B0_SM_STATUS6_RESERVED_FOR_ECO0_BITS                   5
#define DSC3B0_SM_STATUS6_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3b0 :: sm_status6 :: trnsum_pf [10:00] */
#define DSC3B0_SM_STATUS6_TRNSUM_PF_MASK                           0x07ff
#define DSC3B0_SM_STATUS6_TRNSUM_PF_ALIGN                          0
#define DSC3B0_SM_STATUS6_TRNSUM_PF_BITS                           11
#define DSC3B0_SM_STATUS6_TRNSUM_PF_SHIFT                          0


/****************************************************************************
 * Hypercore_USER_Dsc3b1
 ***************************************************************************/
/****************************************************************************
 * Dsc3b1 :: cdr_status0
 ***************************************************************************/
/* Dsc3b1 :: cdr_status0 :: integ_reg [15:00] */
#define DSC3B1_CDR_STATUS0_INTEG_REG_MASK                          0xffff
#define DSC3B1_CDR_STATUS0_INTEG_REG_ALIGN                         0
#define DSC3B1_CDR_STATUS0_INTEG_REG_BITS                          16
#define DSC3B1_CDR_STATUS0_INTEG_REG_SHIFT                         0


/****************************************************************************
 * Dsc3b1 :: cdr_status1
 ***************************************************************************/
/* Dsc3b1 :: cdr_status1 :: integ_reg_xfer [15:00] */
#define DSC3B1_CDR_STATUS1_INTEG_REG_XFER_MASK                     0xffff
#define DSC3B1_CDR_STATUS1_INTEG_REG_XFER_ALIGN                    0
#define DSC3B1_CDR_STATUS1_INTEG_REG_XFER_BITS                     16
#define DSC3B1_CDR_STATUS1_INTEG_REG_XFER_SHIFT                    0


/****************************************************************************
 * Dsc3b1 :: cdr_status2
 ***************************************************************************/
/* Dsc3b1 :: cdr_status2 :: reserved_for_eco0 [15:11] */
#define DSC3B1_CDR_STATUS2_RESERVED_FOR_ECO0_MASK                  0xf800
#define DSC3B1_CDR_STATUS2_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC3B1_CDR_STATUS2_RESERVED_FOR_ECO0_BITS                  5
#define DSC3B1_CDR_STATUS2_RESERVED_FOR_ECO0_SHIFT                 11

/* Dsc3b1 :: cdr_status2 :: sm_br_cdr_enabled [10:10] */
#define DSC3B1_CDR_STATUS2_SM_BR_CDR_ENABLED_MASK                  0x0400
#define DSC3B1_CDR_STATUS2_SM_BR_CDR_ENABLED_ALIGN                 0
#define DSC3B1_CDR_STATUS2_SM_BR_CDR_ENABLED_BITS                  1
#define DSC3B1_CDR_STATUS2_SM_BR_CDR_ENABLED_SHIFT                 10

/* Dsc3b1 :: cdr_status2 :: br_cdr_enabled [09:09] */
#define DSC3B1_CDR_STATUS2_BR_CDR_ENABLED_MASK                     0x0200
#define DSC3B1_CDR_STATUS2_BR_CDR_ENABLED_ALIGN                    0
#define DSC3B1_CDR_STATUS2_BR_CDR_ENABLED_BITS                     1
#define DSC3B1_CDR_STATUS2_BR_CDR_ENABLED_SHIFT                    9

/* Dsc3b1 :: cdr_status2 :: oscdr_mode [08:06] */
#define DSC3B1_CDR_STATUS2_OSCDR_MODE_MASK                         0x01c0
#define DSC3B1_CDR_STATUS2_OSCDR_MODE_ALIGN                        0
#define DSC3B1_CDR_STATUS2_OSCDR_MODE_BITS                         3
#define DSC3B1_CDR_STATUS2_OSCDR_MODE_SHIFT                        6

/* Dsc3b1 :: cdr_status2 :: phase_err [05:00] */
#define DSC3B1_CDR_STATUS2_PHASE_ERR_MASK                          0x003f
#define DSC3B1_CDR_STATUS2_PHASE_ERR_ALIGN                         0
#define DSC3B1_CDR_STATUS2_PHASE_ERR_BITS                          6
#define DSC3B1_CDR_STATUS2_PHASE_ERR_SHIFT                         0


/****************************************************************************
 * Dsc3b1 :: pi_status0
 ***************************************************************************/
/* Dsc3b1 :: pi_status0 :: invalid_intrp_ctrl0 [15:15] */
#define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL0_MASK                 0x8000
#define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL0_ALIGN                0
#define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL0_BITS                 1
#define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL0_SHIFT                15

/* Dsc3b1 :: pi_status0 :: invalid_intrp_ctrl90 [14:14] */
#define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL90_MASK                0x4000
#define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL90_ALIGN               0
#define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL90_BITS                1
#define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL90_SHIFT               14

/* Dsc3b1 :: pi_status0 :: clk90_phase_offset [13:07] */
#define DSC3B1_PI_STATUS0_CLK90_PHASE_OFFSET_MASK                  0x3f80
#define DSC3B1_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN                 0
#define DSC3B1_PI_STATUS0_CLK90_PHASE_OFFSET_BITS                  7
#define DSC3B1_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT                 7

/* Dsc3b1 :: pi_status0 :: phase_cntr [06:00] */
#define DSC3B1_PI_STATUS0_PHASE_CNTR_MASK                          0x007f
#define DSC3B1_PI_STATUS0_PHASE_CNTR_ALIGN                         0
#define DSC3B1_PI_STATUS0_PHASE_CNTR_BITS                          7
#define DSC3B1_PI_STATUS0_PHASE_CNTR_SHIFT                         0


/****************************************************************************
 * Dsc3b1 :: pi_status1
 ***************************************************************************/
/* union - case pi_Single0_lsb [15:00] */
/* Dsc3b1 :: pi_status1 :: Single0_lsb [15:00] */
#define DSC3B1_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_MASK          0xffff
#define DSC3B1_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_ALIGN         0
#define DSC3B1_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_BITS          16
#define DSC3B1_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_SHIFT         0


/* union - case pi_Single0_msb [15:00] */
/* Dsc3b1 :: pi_status1 :: Single0_msb [15:00] */
#define DSC3B1_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_MASK          0xffff
#define DSC3B1_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_ALIGN         0
#define DSC3B1_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_BITS          16
#define DSC3B1_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_SHIFT         0


/* union - case pi_Sequence0_lsb [15:00] */
/* Dsc3b1 :: pi_status1 :: Sequence0_lsb [15:00] */
#define DSC3B1_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_MASK      0xffff
#define DSC3B1_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_ALIGN     0
#define DSC3B1_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_BITS      16
#define DSC3B1_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_SHIFT     0


/* union - case pi_Sequence0_msb [15:00] */
/* Dsc3b1 :: pi_status1 :: Sequence0_msb [15:00] */
#define DSC3B1_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_MASK      0xffff
#define DSC3B1_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_ALIGN     0
#define DSC3B1_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_BITS      16
#define DSC3B1_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_SHIFT     0


/* union - case pi_Single90_lsb [15:00] */
/* Dsc3b1 :: pi_status1 :: Single90_lsb [15:00] */
#define DSC3B1_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_MASK        0xffff
#define DSC3B1_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_ALIGN       0
#define DSC3B1_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_BITS        16
#define DSC3B1_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_SHIFT       0


/* union - case pi_Single90_msb [15:00] */
/* Dsc3b1 :: pi_status1 :: Single90_msb [15:00] */
#define DSC3B1_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_MASK        0xffff
#define DSC3B1_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_ALIGN       0
#define DSC3B1_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_BITS        16
#define DSC3B1_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_SHIFT       0


/* union - case pi_Sequence90_lsb [15:00] */
/* Dsc3b1 :: pi_status1 :: Sequence90_lsb [15:00] */
#define DSC3B1_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_MASK    0xffff
#define DSC3B1_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_ALIGN   0
#define DSC3B1_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_BITS    16
#define DSC3B1_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_SHIFT   0


/* union - case pi_Sequence90_msb [15:00] */
/* Dsc3b1 :: pi_status1 :: Sequence90_msb [15:00] */
#define DSC3B1_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_MASK    0xffff
#define DSC3B1_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_ALIGN   0
#define DSC3B1_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_BITS    16
#define DSC3B1_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_SHIFT   0



/****************************************************************************
 * Dsc3b1 :: dfe_vga_status0
 ***************************************************************************/
/* Dsc3b1 :: dfe_vga_status0 :: reserved_for_eco0 [15:11] */
#define DSC3B1_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_MASK              0xf800
#define DSC3B1_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_ALIGN             0
#define DSC3B1_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_BITS              5
#define DSC3B1_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_SHIFT             11

/* Dsc3b1 :: dfe_vga_status0 :: vga_sum [10:06] */
#define DSC3B1_DFE_VGA_STATUS0_VGA_SUM_MASK                        0x07c0
#define DSC3B1_DFE_VGA_STATUS0_VGA_SUM_ALIGN                       0
#define DSC3B1_DFE_VGA_STATUS0_VGA_SUM_BITS                        5
#define DSC3B1_DFE_VGA_STATUS0_VGA_SUM_SHIFT                       6

/* Dsc3b1 :: dfe_vga_status0 :: dfe_tap_bin [05:00] */
#define DSC3B1_DFE_VGA_STATUS0_DFE_TAP_BIN_MASK                    0x003f
#define DSC3B1_DFE_VGA_STATUS0_DFE_TAP_BIN_ALIGN                   0
#define DSC3B1_DFE_VGA_STATUS0_DFE_TAP_BIN_BITS                    6
#define DSC3B1_DFE_VGA_STATUS0_DFE_TAP_BIN_SHIFT                   0


/****************************************************************************
 * Dsc3b1 :: dfe_vga_status1
 ***************************************************************************/
/* Dsc3b1 :: dfe_vga_status1 :: reserved_for_eco0 [15:11] */
#define DSC3B1_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_MASK              0xf800
#define DSC3B1_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_ALIGN             0
#define DSC3B1_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_BITS              5
#define DSC3B1_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_SHIFT             11

/* Dsc3b1 :: dfe_vga_status1 :: trnsum [10:00] */
#define DSC3B1_DFE_VGA_STATUS1_TRNSUM_MASK                         0x07ff
#define DSC3B1_DFE_VGA_STATUS1_TRNSUM_ALIGN                        0
#define DSC3B1_DFE_VGA_STATUS1_TRNSUM_BITS                         11
#define DSC3B1_DFE_VGA_STATUS1_TRNSUM_SHIFT                        0


/****************************************************************************
 * Dsc3b1 :: sm_status0
 ***************************************************************************/
/* Dsc3b1 :: sm_status0 :: reserved_for_eco0 [15:14] */
#define DSC3B1_SM_STATUS0_RESERVED_FOR_ECO0_MASK                   0xc000
#define DSC3B1_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B1_SM_STATUS0_RESERVED_FOR_ECO0_BITS                   2
#define DSC3B1_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT                  14

/* Dsc3b1 :: sm_status0 :: tuning_done [13:13] */
#define DSC3B1_SM_STATUS0_TUNING_DONE_MASK                         0x2000
#define DSC3B1_SM_STATUS0_TUNING_DONE_ALIGN                        0
#define DSC3B1_SM_STATUS0_TUNING_DONE_BITS                         1
#define DSC3B1_SM_STATUS0_TUNING_DONE_SHIFT                        13

/* Dsc3b1 :: sm_status0 :: srch_state [12:09] */
#define DSC3B1_SM_STATUS0_SRCH_STATE_MASK                          0x1e00
#define DSC3B1_SM_STATUS0_SRCH_STATE_ALIGN                         0
#define DSC3B1_SM_STATUS0_SRCH_STATE_BITS                          4
#define DSC3B1_SM_STATUS0_SRCH_STATE_SHIFT                         9

/* Dsc3b1 :: sm_status0 :: tuning_state [08:04] */
#define DSC3B1_SM_STATUS0_TUNING_STATE_MASK                        0x01f0
#define DSC3B1_SM_STATUS0_TUNING_STATE_ALIGN                       0
#define DSC3B1_SM_STATUS0_TUNING_STATE_BITS                        5
#define DSC3B1_SM_STATUS0_TUNING_STATE_SHIFT                       4

/* Dsc3b1 :: sm_status0 :: dsc_state [03:00] */
#define DSC3B1_SM_STATUS0_DSC_STATE_MASK                           0x000f
#define DSC3B1_SM_STATUS0_DSC_STATE_ALIGN                          0
#define DSC3B1_SM_STATUS0_DSC_STATE_BITS                           4
#define DSC3B1_SM_STATUS0_DSC_STATE_SHIFT                          0


/****************************************************************************
 * Dsc3b1 :: sm_status1
 ***************************************************************************/
/* Dsc3b1 :: sm_status1 :: reserved_for_eco0 [15:11] */
#define DSC3B1_SM_STATUS1_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3B1_SM_STATUS1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B1_SM_STATUS1_RESERVED_FOR_ECO0_BITS                   5
#define DSC3B1_SM_STATUS1_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3b1 :: sm_status1 :: postc_metric [10:00] */
#define DSC3B1_SM_STATUS1_POSTC_METRIC_MASK                        0x07ff
#define DSC3B1_SM_STATUS1_POSTC_METRIC_ALIGN                       0
#define DSC3B1_SM_STATUS1_POSTC_METRIC_BITS                        11
#define DSC3B1_SM_STATUS1_POSTC_METRIC_SHIFT                       0


/****************************************************************************
 * Dsc3b1 :: sm_status2
 ***************************************************************************/
/* Dsc3b1 :: sm_status2 :: reserved_for_eco0 [15:15] */
#define DSC3B1_SM_STATUS2_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC3B1_SM_STATUS2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B1_SM_STATUS2_RESERVED_FOR_ECO0_BITS                   1
#define DSC3B1_SM_STATUS2_RESERVED_FOR_ECO0_SHIFT                  15

/* Dsc3b1 :: sm_status2 :: slicer_offset_po [14:10] */
#define DSC3B1_SM_STATUS2_SLICER_OFFSET_PO_MASK                    0x7c00
#define DSC3B1_SM_STATUS2_SLICER_OFFSET_PO_ALIGN                   0
#define DSC3B1_SM_STATUS2_SLICER_OFFSET_PO_BITS                    5
#define DSC3B1_SM_STATUS2_SLICER_OFFSET_PO_SHIFT                   10

/* Dsc3b1 :: sm_status2 :: slicer_offset_zo [09:05] */
#define DSC3B1_SM_STATUS2_SLICER_OFFSET_ZO_MASK                    0x03e0
#define DSC3B1_SM_STATUS2_SLICER_OFFSET_ZO_ALIGN                   0
#define DSC3B1_SM_STATUS2_SLICER_OFFSET_ZO_BITS                    5
#define DSC3B1_SM_STATUS2_SLICER_OFFSET_ZO_SHIFT                   5

/* Dsc3b1 :: sm_status2 :: slicer_offset_mo [04:00] */
#define DSC3B1_SM_STATUS2_SLICER_OFFSET_MO_MASK                    0x001f
#define DSC3B1_SM_STATUS2_SLICER_OFFSET_MO_ALIGN                   0
#define DSC3B1_SM_STATUS2_SLICER_OFFSET_MO_BITS                    5
#define DSC3B1_SM_STATUS2_SLICER_OFFSET_MO_SHIFT                   0


/****************************************************************************
 * Dsc3b1 :: sm_status3
 ***************************************************************************/
/* Dsc3b1 :: sm_status3 :: reserved_for_eco0 [15:15] */
#define DSC3B1_SM_STATUS3_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC3B1_SM_STATUS3_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B1_SM_STATUS3_RESERVED_FOR_ECO0_BITS                   1
#define DSC3B1_SM_STATUS3_RESERVED_FOR_ECO0_SHIFT                  15

/* Dsc3b1 :: sm_status3 :: slicer_offset_pe [14:10] */
#define DSC3B1_SM_STATUS3_SLICER_OFFSET_PE_MASK                    0x7c00
#define DSC3B1_SM_STATUS3_SLICER_OFFSET_PE_ALIGN                   0
#define DSC3B1_SM_STATUS3_SLICER_OFFSET_PE_BITS                    5
#define DSC3B1_SM_STATUS3_SLICER_OFFSET_PE_SHIFT                   10

/* Dsc3b1 :: sm_status3 :: slicer_offset_ze [09:05] */
#define DSC3B1_SM_STATUS3_SLICER_OFFSET_ZE_MASK                    0x03e0
#define DSC3B1_SM_STATUS3_SLICER_OFFSET_ZE_ALIGN                   0
#define DSC3B1_SM_STATUS3_SLICER_OFFSET_ZE_BITS                    5
#define DSC3B1_SM_STATUS3_SLICER_OFFSET_ZE_SHIFT                   5

/* Dsc3b1 :: sm_status3 :: slicer_offset_me [04:00] */
#define DSC3B1_SM_STATUS3_SLICER_OFFSET_ME_MASK                    0x001f
#define DSC3B1_SM_STATUS3_SLICER_OFFSET_ME_ALIGN                   0
#define DSC3B1_SM_STATUS3_SLICER_OFFSET_ME_BITS                    5
#define DSC3B1_SM_STATUS3_SLICER_OFFSET_ME_SHIFT                   0


/****************************************************************************
 * Dsc3b1 :: sm_status4
 ***************************************************************************/
/* Dsc3b1 :: sm_status4 :: reserved_for_eco0 [15:09] */
#define DSC3B1_SM_STATUS4_RESERVED_FOR_ECO0_MASK                   0xfe00
#define DSC3B1_SM_STATUS4_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B1_SM_STATUS4_RESERVED_FOR_ECO0_BITS                   7
#define DSC3B1_SM_STATUS4_RESERVED_FOR_ECO0_SHIFT                  9

/* Dsc3b1 :: sm_status4 :: dfe_max [08:08] */
#define DSC3B1_SM_STATUS4_DFE_MAX_MASK                             0x0100
#define DSC3B1_SM_STATUS4_DFE_MAX_ALIGN                            0
#define DSC3B1_SM_STATUS4_DFE_MAX_BITS                             1
#define DSC3B1_SM_STATUS4_DFE_MAX_SHIFT                            8

/* Dsc3b1 :: sm_status4 :: dfe_min [07:07] */
#define DSC3B1_SM_STATUS4_DFE_MIN_MASK                             0x0080
#define DSC3B1_SM_STATUS4_DFE_MIN_ALIGN                            0
#define DSC3B1_SM_STATUS4_DFE_MIN_BITS                             1
#define DSC3B1_SM_STATUS4_DFE_MIN_SHIFT                            7

/* Dsc3b1 :: sm_status4 :: vga_max [06:06] */
#define DSC3B1_SM_STATUS4_VGA_MAX_MASK                             0x0040
#define DSC3B1_SM_STATUS4_VGA_MAX_ALIGN                            0
#define DSC3B1_SM_STATUS4_VGA_MAX_BITS                             1
#define DSC3B1_SM_STATUS4_VGA_MAX_SHIFT                            6

/* Dsc3b1 :: sm_status4 :: vga_min [05:05] */
#define DSC3B1_SM_STATUS4_VGA_MIN_MASK                             0x0020
#define DSC3B1_SM_STATUS4_VGA_MIN_ALIGN                            0
#define DSC3B1_SM_STATUS4_VGA_MIN_BITS                             1
#define DSC3B1_SM_STATUS4_VGA_MIN_SHIFT                            5

/* Dsc3b1 :: sm_status4 :: pf_max [04:04] */
#define DSC3B1_SM_STATUS4_PF_MAX_MASK                              0x0010
#define DSC3B1_SM_STATUS4_PF_MAX_ALIGN                             0
#define DSC3B1_SM_STATUS4_PF_MAX_BITS                              1
#define DSC3B1_SM_STATUS4_PF_MAX_SHIFT                             4

/* Dsc3b1 :: sm_status4 :: pf_min [03:03] */
#define DSC3B1_SM_STATUS4_PF_MIN_MASK                              0x0008
#define DSC3B1_SM_STATUS4_PF_MIN_ALIGN                             0
#define DSC3B1_SM_STATUS4_PF_MIN_BITS                              1
#define DSC3B1_SM_STATUS4_PF_MIN_SHIFT                             3

/* Dsc3b1 :: sm_status4 :: pf_ctrl [02:00] */
#define DSC3B1_SM_STATUS4_PF_CTRL_MASK                             0x0007
#define DSC3B1_SM_STATUS4_PF_CTRL_ALIGN                            0
#define DSC3B1_SM_STATUS4_PF_CTRL_BITS                             3
#define DSC3B1_SM_STATUS4_PF_CTRL_SHIFT                            0


/****************************************************************************
 * Dsc3b1 :: ana_status0
 ***************************************************************************/
/* Dsc3b1 :: ana_status0 :: reserved_for_eco0 [15:04] */
#define DSC3B1_ANA_STATUS0_RESERVED_FOR_ECO0_MASK                  0xfff0
#define DSC3B1_ANA_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC3B1_ANA_STATUS0_RESERVED_FOR_ECO0_BITS                  12
#define DSC3B1_ANA_STATUS0_RESERVED_FOR_ECO0_SHIFT                 4

/* Dsc3b1 :: ana_status0 :: pd_ch_p1 [03:03] */
#define DSC3B1_ANA_STATUS0_PD_CH_P1_MASK                           0x0008
#define DSC3B1_ANA_STATUS0_PD_CH_P1_ALIGN                          0
#define DSC3B1_ANA_STATUS0_PD_CH_P1_BITS                           1
#define DSC3B1_ANA_STATUS0_PD_CH_P1_SHIFT                          3

/* Dsc3b1 :: ana_status0 :: en_dfe_clk [02:02] */
#define DSC3B1_ANA_STATUS0_EN_DFE_CLK_MASK                         0x0004
#define DSC3B1_ANA_STATUS0_EN_DFE_CLK_ALIGN                        0
#define DSC3B1_ANA_STATUS0_EN_DFE_CLK_BITS                         1
#define DSC3B1_ANA_STATUS0_EN_DFE_CLK_SHIFT                        2

/* Dsc3b1 :: ana_status0 :: en_hgain [01:01] */
#define DSC3B1_ANA_STATUS0_EN_HGAIN_MASK                           0x0002
#define DSC3B1_ANA_STATUS0_EN_HGAIN_ALIGN                          0
#define DSC3B1_ANA_STATUS0_EN_HGAIN_BITS                           1
#define DSC3B1_ANA_STATUS0_EN_HGAIN_SHIFT                          1

/* Dsc3b1 :: ana_status0 :: offset_pd [00:00] */
#define DSC3B1_ANA_STATUS0_OFFSET_PD_MASK                          0x0001
#define DSC3B1_ANA_STATUS0_OFFSET_PD_ALIGN                         0
#define DSC3B1_ANA_STATUS0_OFFSET_PD_BITS                          1
#define DSC3B1_ANA_STATUS0_OFFSET_PD_SHIFT                         0


/****************************************************************************
 * Dsc3b1 :: sm_status5
 ***************************************************************************/
/* Dsc3b1 :: sm_status5 :: reserved_for_eco0 [15:11] */
#define DSC3B1_SM_STATUS5_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3B1_SM_STATUS5_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B1_SM_STATUS5_RESERVED_FOR_ECO0_BITS                   5
#define DSC3B1_SM_STATUS5_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3b1 :: sm_status5 :: trnsum_br_vga [10:00] */
#define DSC3B1_SM_STATUS5_TRNSUM_BR_VGA_MASK                       0x07ff
#define DSC3B1_SM_STATUS5_TRNSUM_BR_VGA_ALIGN                      0
#define DSC3B1_SM_STATUS5_TRNSUM_BR_VGA_BITS                       11
#define DSC3B1_SM_STATUS5_TRNSUM_BR_VGA_SHIFT                      0


/****************************************************************************
 * Dsc3b1 :: sm_status6
 ***************************************************************************/
/* Dsc3b1 :: sm_status6 :: reserved_for_eco0 [15:11] */
#define DSC3B1_SM_STATUS6_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3B1_SM_STATUS6_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B1_SM_STATUS6_RESERVED_FOR_ECO0_BITS                   5
#define DSC3B1_SM_STATUS6_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3b1 :: sm_status6 :: trnsum_pf [10:00] */
#define DSC3B1_SM_STATUS6_TRNSUM_PF_MASK                           0x07ff
#define DSC3B1_SM_STATUS6_TRNSUM_PF_ALIGN                          0
#define DSC3B1_SM_STATUS6_TRNSUM_PF_BITS                           11
#define DSC3B1_SM_STATUS6_TRNSUM_PF_SHIFT                          0


/****************************************************************************
 * Hypercore_USER_Dsc3b2
 ***************************************************************************/
/****************************************************************************
 * Dsc3b2 :: cdr_status0
 ***************************************************************************/
/* Dsc3b2 :: cdr_status0 :: integ_reg [15:00] */
#define DSC3B2_CDR_STATUS0_INTEG_REG_MASK                          0xffff
#define DSC3B2_CDR_STATUS0_INTEG_REG_ALIGN                         0
#define DSC3B2_CDR_STATUS0_INTEG_REG_BITS                          16
#define DSC3B2_CDR_STATUS0_INTEG_REG_SHIFT                         0


/****************************************************************************
 * Dsc3b2 :: cdr_status1
 ***************************************************************************/
/* Dsc3b2 :: cdr_status1 :: integ_reg_xfer [15:00] */
#define DSC3B2_CDR_STATUS1_INTEG_REG_XFER_MASK                     0xffff
#define DSC3B2_CDR_STATUS1_INTEG_REG_XFER_ALIGN                    0
#define DSC3B2_CDR_STATUS1_INTEG_REG_XFER_BITS                     16
#define DSC3B2_CDR_STATUS1_INTEG_REG_XFER_SHIFT                    0


/****************************************************************************
 * Dsc3b2 :: cdr_status2
 ***************************************************************************/
/* Dsc3b2 :: cdr_status2 :: reserved_for_eco0 [15:11] */
#define DSC3B2_CDR_STATUS2_RESERVED_FOR_ECO0_MASK                  0xf800
#define DSC3B2_CDR_STATUS2_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC3B2_CDR_STATUS2_RESERVED_FOR_ECO0_BITS                  5
#define DSC3B2_CDR_STATUS2_RESERVED_FOR_ECO0_SHIFT                 11

/* Dsc3b2 :: cdr_status2 :: sm_br_cdr_enabled [10:10] */
#define DSC3B2_CDR_STATUS2_SM_BR_CDR_ENABLED_MASK                  0x0400
#define DSC3B2_CDR_STATUS2_SM_BR_CDR_ENABLED_ALIGN                 0
#define DSC3B2_CDR_STATUS2_SM_BR_CDR_ENABLED_BITS                  1
#define DSC3B2_CDR_STATUS2_SM_BR_CDR_ENABLED_SHIFT                 10

/* Dsc3b2 :: cdr_status2 :: br_cdr_enabled [09:09] */
#define DSC3B2_CDR_STATUS2_BR_CDR_ENABLED_MASK                     0x0200
#define DSC3B2_CDR_STATUS2_BR_CDR_ENABLED_ALIGN                    0
#define DSC3B2_CDR_STATUS2_BR_CDR_ENABLED_BITS                     1
#define DSC3B2_CDR_STATUS2_BR_CDR_ENABLED_SHIFT                    9

/* Dsc3b2 :: cdr_status2 :: oscdr_mode [08:06] */
#define DSC3B2_CDR_STATUS2_OSCDR_MODE_MASK                         0x01c0
#define DSC3B2_CDR_STATUS2_OSCDR_MODE_ALIGN                        0
#define DSC3B2_CDR_STATUS2_OSCDR_MODE_BITS                         3
#define DSC3B2_CDR_STATUS2_OSCDR_MODE_SHIFT                        6

/* Dsc3b2 :: cdr_status2 :: phase_err [05:00] */
#define DSC3B2_CDR_STATUS2_PHASE_ERR_MASK                          0x003f
#define DSC3B2_CDR_STATUS2_PHASE_ERR_ALIGN                         0
#define DSC3B2_CDR_STATUS2_PHASE_ERR_BITS                          6
#define DSC3B2_CDR_STATUS2_PHASE_ERR_SHIFT                         0


/****************************************************************************
 * Dsc3b2 :: pi_status0
 ***************************************************************************/
/* Dsc3b2 :: pi_status0 :: invalid_intrp_ctrl0 [15:15] */
#define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL0_MASK                 0x8000
#define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL0_ALIGN                0
#define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL0_BITS                 1
#define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL0_SHIFT                15

/* Dsc3b2 :: pi_status0 :: invalid_intrp_ctrl90 [14:14] */
#define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL90_MASK                0x4000
#define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL90_ALIGN               0
#define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL90_BITS                1
#define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL90_SHIFT               14

/* Dsc3b2 :: pi_status0 :: clk90_phase_offset [13:07] */
#define DSC3B2_PI_STATUS0_CLK90_PHASE_OFFSET_MASK                  0x3f80
#define DSC3B2_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN                 0
#define DSC3B2_PI_STATUS0_CLK90_PHASE_OFFSET_BITS                  7
#define DSC3B2_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT                 7

/* Dsc3b2 :: pi_status0 :: phase_cntr [06:00] */
#define DSC3B2_PI_STATUS0_PHASE_CNTR_MASK                          0x007f
#define DSC3B2_PI_STATUS0_PHASE_CNTR_ALIGN                         0
#define DSC3B2_PI_STATUS0_PHASE_CNTR_BITS                          7
#define DSC3B2_PI_STATUS0_PHASE_CNTR_SHIFT                         0


/****************************************************************************
 * Dsc3b2 :: pi_status1
 ***************************************************************************/
/* union - case pi_Single0_lsb [15:00] */
/* Dsc3b2 :: pi_status1 :: Single0_lsb [15:00] */
#define DSC3B2_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_MASK          0xffff
#define DSC3B2_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_ALIGN         0
#define DSC3B2_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_BITS          16
#define DSC3B2_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_SHIFT         0


/* union - case pi_Single0_msb [15:00] */
/* Dsc3b2 :: pi_status1 :: Single0_msb [15:00] */
#define DSC3B2_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_MASK          0xffff
#define DSC3B2_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_ALIGN         0
#define DSC3B2_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_BITS          16
#define DSC3B2_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_SHIFT         0


/* union - case pi_Sequence0_lsb [15:00] */
/* Dsc3b2 :: pi_status1 :: Sequence0_lsb [15:00] */
#define DSC3B2_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_MASK      0xffff
#define DSC3B2_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_ALIGN     0
#define DSC3B2_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_BITS      16
#define DSC3B2_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_SHIFT     0


/* union - case pi_Sequence0_msb [15:00] */
/* Dsc3b2 :: pi_status1 :: Sequence0_msb [15:00] */
#define DSC3B2_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_MASK      0xffff
#define DSC3B2_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_ALIGN     0
#define DSC3B2_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_BITS      16
#define DSC3B2_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_SHIFT     0


/* union - case pi_Single90_lsb [15:00] */
/* Dsc3b2 :: pi_status1 :: Single90_lsb [15:00] */
#define DSC3B2_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_MASK        0xffff
#define DSC3B2_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_ALIGN       0
#define DSC3B2_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_BITS        16
#define DSC3B2_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_SHIFT       0


/* union - case pi_Single90_msb [15:00] */
/* Dsc3b2 :: pi_status1 :: Single90_msb [15:00] */
#define DSC3B2_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_MASK        0xffff
#define DSC3B2_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_ALIGN       0
#define DSC3B2_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_BITS        16
#define DSC3B2_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_SHIFT       0


/* union - case pi_Sequence90_lsb [15:00] */
/* Dsc3b2 :: pi_status1 :: Sequence90_lsb [15:00] */
#define DSC3B2_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_MASK    0xffff
#define DSC3B2_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_ALIGN   0
#define DSC3B2_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_BITS    16
#define DSC3B2_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_SHIFT   0


/* union - case pi_Sequence90_msb [15:00] */
/* Dsc3b2 :: pi_status1 :: Sequence90_msb [15:00] */
#define DSC3B2_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_MASK    0xffff
#define DSC3B2_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_ALIGN   0
#define DSC3B2_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_BITS    16
#define DSC3B2_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_SHIFT   0



/****************************************************************************
 * Dsc3b2 :: dfe_vga_status0
 ***************************************************************************/
/* Dsc3b2 :: dfe_vga_status0 :: reserved_for_eco0 [15:11] */
#define DSC3B2_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_MASK              0xf800
#define DSC3B2_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_ALIGN             0
#define DSC3B2_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_BITS              5
#define DSC3B2_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_SHIFT             11

/* Dsc3b2 :: dfe_vga_status0 :: vga_sum [10:06] */
#define DSC3B2_DFE_VGA_STATUS0_VGA_SUM_MASK                        0x07c0
#define DSC3B2_DFE_VGA_STATUS0_VGA_SUM_ALIGN                       0
#define DSC3B2_DFE_VGA_STATUS0_VGA_SUM_BITS                        5
#define DSC3B2_DFE_VGA_STATUS0_VGA_SUM_SHIFT                       6

/* Dsc3b2 :: dfe_vga_status0 :: dfe_tap_bin [05:00] */
#define DSC3B2_DFE_VGA_STATUS0_DFE_TAP_BIN_MASK                    0x003f
#define DSC3B2_DFE_VGA_STATUS0_DFE_TAP_BIN_ALIGN                   0
#define DSC3B2_DFE_VGA_STATUS0_DFE_TAP_BIN_BITS                    6
#define DSC3B2_DFE_VGA_STATUS0_DFE_TAP_BIN_SHIFT                   0


/****************************************************************************
 * Dsc3b2 :: dfe_vga_status1
 ***************************************************************************/
/* Dsc3b2 :: dfe_vga_status1 :: reserved_for_eco0 [15:11] */
#define DSC3B2_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_MASK              0xf800
#define DSC3B2_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_ALIGN             0
#define DSC3B2_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_BITS              5
#define DSC3B2_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_SHIFT             11

/* Dsc3b2 :: dfe_vga_status1 :: trnsum [10:00] */
#define DSC3B2_DFE_VGA_STATUS1_TRNSUM_MASK                         0x07ff
#define DSC3B2_DFE_VGA_STATUS1_TRNSUM_ALIGN                        0
#define DSC3B2_DFE_VGA_STATUS1_TRNSUM_BITS                         11
#define DSC3B2_DFE_VGA_STATUS1_TRNSUM_SHIFT                        0


/****************************************************************************
 * Dsc3b2 :: sm_status0
 ***************************************************************************/
/* Dsc3b2 :: sm_status0 :: reserved_for_eco0 [15:14] */
#define DSC3B2_SM_STATUS0_RESERVED_FOR_ECO0_MASK                   0xc000
#define DSC3B2_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B2_SM_STATUS0_RESERVED_FOR_ECO0_BITS                   2
#define DSC3B2_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT                  14

/* Dsc3b2 :: sm_status0 :: tuning_done [13:13] */
#define DSC3B2_SM_STATUS0_TUNING_DONE_MASK                         0x2000
#define DSC3B2_SM_STATUS0_TUNING_DONE_ALIGN                        0
#define DSC3B2_SM_STATUS0_TUNING_DONE_BITS                         1
#define DSC3B2_SM_STATUS0_TUNING_DONE_SHIFT                        13

/* Dsc3b2 :: sm_status0 :: srch_state [12:09] */
#define DSC3B2_SM_STATUS0_SRCH_STATE_MASK                          0x1e00
#define DSC3B2_SM_STATUS0_SRCH_STATE_ALIGN                         0
#define DSC3B2_SM_STATUS0_SRCH_STATE_BITS                          4
#define DSC3B2_SM_STATUS0_SRCH_STATE_SHIFT                         9

/* Dsc3b2 :: sm_status0 :: tuning_state [08:04] */
#define DSC3B2_SM_STATUS0_TUNING_STATE_MASK                        0x01f0
#define DSC3B2_SM_STATUS0_TUNING_STATE_ALIGN                       0
#define DSC3B2_SM_STATUS0_TUNING_STATE_BITS                        5
#define DSC3B2_SM_STATUS0_TUNING_STATE_SHIFT                       4

/* Dsc3b2 :: sm_status0 :: dsc_state [03:00] */
#define DSC3B2_SM_STATUS0_DSC_STATE_MASK                           0x000f
#define DSC3B2_SM_STATUS0_DSC_STATE_ALIGN                          0
#define DSC3B2_SM_STATUS0_DSC_STATE_BITS                           4
#define DSC3B2_SM_STATUS0_DSC_STATE_SHIFT                          0


/****************************************************************************
 * Dsc3b2 :: sm_status1
 ***************************************************************************/
/* Dsc3b2 :: sm_status1 :: reserved_for_eco0 [15:11] */
#define DSC3B2_SM_STATUS1_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3B2_SM_STATUS1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B2_SM_STATUS1_RESERVED_FOR_ECO0_BITS                   5
#define DSC3B2_SM_STATUS1_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3b2 :: sm_status1 :: postc_metric [10:00] */
#define DSC3B2_SM_STATUS1_POSTC_METRIC_MASK                        0x07ff
#define DSC3B2_SM_STATUS1_POSTC_METRIC_ALIGN                       0
#define DSC3B2_SM_STATUS1_POSTC_METRIC_BITS                        11
#define DSC3B2_SM_STATUS1_POSTC_METRIC_SHIFT                       0


/****************************************************************************
 * Dsc3b2 :: sm_status2
 ***************************************************************************/
/* Dsc3b2 :: sm_status2 :: reserved_for_eco0 [15:15] */
#define DSC3B2_SM_STATUS2_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC3B2_SM_STATUS2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B2_SM_STATUS2_RESERVED_FOR_ECO0_BITS                   1
#define DSC3B2_SM_STATUS2_RESERVED_FOR_ECO0_SHIFT                  15

/* Dsc3b2 :: sm_status2 :: slicer_offset_po [14:10] */
#define DSC3B2_SM_STATUS2_SLICER_OFFSET_PO_MASK                    0x7c00
#define DSC3B2_SM_STATUS2_SLICER_OFFSET_PO_ALIGN                   0
#define DSC3B2_SM_STATUS2_SLICER_OFFSET_PO_BITS                    5
#define DSC3B2_SM_STATUS2_SLICER_OFFSET_PO_SHIFT                   10

/* Dsc3b2 :: sm_status2 :: slicer_offset_zo [09:05] */
#define DSC3B2_SM_STATUS2_SLICER_OFFSET_ZO_MASK                    0x03e0
#define DSC3B2_SM_STATUS2_SLICER_OFFSET_ZO_ALIGN                   0
#define DSC3B2_SM_STATUS2_SLICER_OFFSET_ZO_BITS                    5
#define DSC3B2_SM_STATUS2_SLICER_OFFSET_ZO_SHIFT                   5

/* Dsc3b2 :: sm_status2 :: slicer_offset_mo [04:00] */
#define DSC3B2_SM_STATUS2_SLICER_OFFSET_MO_MASK                    0x001f
#define DSC3B2_SM_STATUS2_SLICER_OFFSET_MO_ALIGN                   0
#define DSC3B2_SM_STATUS2_SLICER_OFFSET_MO_BITS                    5
#define DSC3B2_SM_STATUS2_SLICER_OFFSET_MO_SHIFT                   0


/****************************************************************************
 * Dsc3b2 :: sm_status3
 ***************************************************************************/
/* Dsc3b2 :: sm_status3 :: reserved_for_eco0 [15:15] */
#define DSC3B2_SM_STATUS3_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC3B2_SM_STATUS3_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B2_SM_STATUS3_RESERVED_FOR_ECO0_BITS                   1
#define DSC3B2_SM_STATUS3_RESERVED_FOR_ECO0_SHIFT                  15

/* Dsc3b2 :: sm_status3 :: slicer_offset_pe [14:10] */
#define DSC3B2_SM_STATUS3_SLICER_OFFSET_PE_MASK                    0x7c00
#define DSC3B2_SM_STATUS3_SLICER_OFFSET_PE_ALIGN                   0
#define DSC3B2_SM_STATUS3_SLICER_OFFSET_PE_BITS                    5
#define DSC3B2_SM_STATUS3_SLICER_OFFSET_PE_SHIFT                   10

/* Dsc3b2 :: sm_status3 :: slicer_offset_ze [09:05] */
#define DSC3B2_SM_STATUS3_SLICER_OFFSET_ZE_MASK                    0x03e0
#define DSC3B2_SM_STATUS3_SLICER_OFFSET_ZE_ALIGN                   0
#define DSC3B2_SM_STATUS3_SLICER_OFFSET_ZE_BITS                    5
#define DSC3B2_SM_STATUS3_SLICER_OFFSET_ZE_SHIFT                   5

/* Dsc3b2 :: sm_status3 :: slicer_offset_me [04:00] */
#define DSC3B2_SM_STATUS3_SLICER_OFFSET_ME_MASK                    0x001f
#define DSC3B2_SM_STATUS3_SLICER_OFFSET_ME_ALIGN                   0
#define DSC3B2_SM_STATUS3_SLICER_OFFSET_ME_BITS                    5
#define DSC3B2_SM_STATUS3_SLICER_OFFSET_ME_SHIFT                   0


/****************************************************************************
 * Dsc3b2 :: sm_status4
 ***************************************************************************/
/* Dsc3b2 :: sm_status4 :: reserved_for_eco0 [15:09] */
#define DSC3B2_SM_STATUS4_RESERVED_FOR_ECO0_MASK                   0xfe00
#define DSC3B2_SM_STATUS4_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B2_SM_STATUS4_RESERVED_FOR_ECO0_BITS                   7
#define DSC3B2_SM_STATUS4_RESERVED_FOR_ECO0_SHIFT                  9

/* Dsc3b2 :: sm_status4 :: dfe_max [08:08] */
#define DSC3B2_SM_STATUS4_DFE_MAX_MASK                             0x0100
#define DSC3B2_SM_STATUS4_DFE_MAX_ALIGN                            0
#define DSC3B2_SM_STATUS4_DFE_MAX_BITS                             1
#define DSC3B2_SM_STATUS4_DFE_MAX_SHIFT                            8

/* Dsc3b2 :: sm_status4 :: dfe_min [07:07] */
#define DSC3B2_SM_STATUS4_DFE_MIN_MASK                             0x0080
#define DSC3B2_SM_STATUS4_DFE_MIN_ALIGN                            0
#define DSC3B2_SM_STATUS4_DFE_MIN_BITS                             1
#define DSC3B2_SM_STATUS4_DFE_MIN_SHIFT                            7

/* Dsc3b2 :: sm_status4 :: vga_max [06:06] */
#define DSC3B2_SM_STATUS4_VGA_MAX_MASK                             0x0040
#define DSC3B2_SM_STATUS4_VGA_MAX_ALIGN                            0
#define DSC3B2_SM_STATUS4_VGA_MAX_BITS                             1
#define DSC3B2_SM_STATUS4_VGA_MAX_SHIFT                            6

/* Dsc3b2 :: sm_status4 :: vga_min [05:05] */
#define DSC3B2_SM_STATUS4_VGA_MIN_MASK                             0x0020
#define DSC3B2_SM_STATUS4_VGA_MIN_ALIGN                            0
#define DSC3B2_SM_STATUS4_VGA_MIN_BITS                             1
#define DSC3B2_SM_STATUS4_VGA_MIN_SHIFT                            5

/* Dsc3b2 :: sm_status4 :: pf_max [04:04] */
#define DSC3B2_SM_STATUS4_PF_MAX_MASK                              0x0010
#define DSC3B2_SM_STATUS4_PF_MAX_ALIGN                             0
#define DSC3B2_SM_STATUS4_PF_MAX_BITS                              1
#define DSC3B2_SM_STATUS4_PF_MAX_SHIFT                             4

/* Dsc3b2 :: sm_status4 :: pf_min [03:03] */
#define DSC3B2_SM_STATUS4_PF_MIN_MASK                              0x0008
#define DSC3B2_SM_STATUS4_PF_MIN_ALIGN                             0
#define DSC3B2_SM_STATUS4_PF_MIN_BITS                              1
#define DSC3B2_SM_STATUS4_PF_MIN_SHIFT                             3

/* Dsc3b2 :: sm_status4 :: pf_ctrl [02:00] */
#define DSC3B2_SM_STATUS4_PF_CTRL_MASK                             0x0007
#define DSC3B2_SM_STATUS4_PF_CTRL_ALIGN                            0
#define DSC3B2_SM_STATUS4_PF_CTRL_BITS                             3
#define DSC3B2_SM_STATUS4_PF_CTRL_SHIFT                            0


/****************************************************************************
 * Dsc3b2 :: ana_status0
 ***************************************************************************/
/* Dsc3b2 :: ana_status0 :: reserved_for_eco0 [15:04] */
#define DSC3B2_ANA_STATUS0_RESERVED_FOR_ECO0_MASK                  0xfff0
#define DSC3B2_ANA_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC3B2_ANA_STATUS0_RESERVED_FOR_ECO0_BITS                  12
#define DSC3B2_ANA_STATUS0_RESERVED_FOR_ECO0_SHIFT                 4

/* Dsc3b2 :: ana_status0 :: pd_ch_p1 [03:03] */
#define DSC3B2_ANA_STATUS0_PD_CH_P1_MASK                           0x0008
#define DSC3B2_ANA_STATUS0_PD_CH_P1_ALIGN                          0
#define DSC3B2_ANA_STATUS0_PD_CH_P1_BITS                           1
#define DSC3B2_ANA_STATUS0_PD_CH_P1_SHIFT                          3

/* Dsc3b2 :: ana_status0 :: en_dfe_clk [02:02] */
#define DSC3B2_ANA_STATUS0_EN_DFE_CLK_MASK                         0x0004
#define DSC3B2_ANA_STATUS0_EN_DFE_CLK_ALIGN                        0
#define DSC3B2_ANA_STATUS0_EN_DFE_CLK_BITS                         1
#define DSC3B2_ANA_STATUS0_EN_DFE_CLK_SHIFT                        2

/* Dsc3b2 :: ana_status0 :: en_hgain [01:01] */
#define DSC3B2_ANA_STATUS0_EN_HGAIN_MASK                           0x0002
#define DSC3B2_ANA_STATUS0_EN_HGAIN_ALIGN                          0
#define DSC3B2_ANA_STATUS0_EN_HGAIN_BITS                           1
#define DSC3B2_ANA_STATUS0_EN_HGAIN_SHIFT                          1

/* Dsc3b2 :: ana_status0 :: offset_pd [00:00] */
#define DSC3B2_ANA_STATUS0_OFFSET_PD_MASK                          0x0001
#define DSC3B2_ANA_STATUS0_OFFSET_PD_ALIGN                         0
#define DSC3B2_ANA_STATUS0_OFFSET_PD_BITS                          1
#define DSC3B2_ANA_STATUS0_OFFSET_PD_SHIFT                         0


/****************************************************************************
 * Dsc3b2 :: sm_status5
 ***************************************************************************/
/* Dsc3b2 :: sm_status5 :: reserved_for_eco0 [15:11] */
#define DSC3B2_SM_STATUS5_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3B2_SM_STATUS5_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B2_SM_STATUS5_RESERVED_FOR_ECO0_BITS                   5
#define DSC3B2_SM_STATUS5_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3b2 :: sm_status5 :: trnsum_br_vga [10:00] */
#define DSC3B2_SM_STATUS5_TRNSUM_BR_VGA_MASK                       0x07ff
#define DSC3B2_SM_STATUS5_TRNSUM_BR_VGA_ALIGN                      0
#define DSC3B2_SM_STATUS5_TRNSUM_BR_VGA_BITS                       11
#define DSC3B2_SM_STATUS5_TRNSUM_BR_VGA_SHIFT                      0


/****************************************************************************
 * Dsc3b2 :: sm_status6
 ***************************************************************************/
/* Dsc3b2 :: sm_status6 :: reserved_for_eco0 [15:11] */
#define DSC3B2_SM_STATUS6_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3B2_SM_STATUS6_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B2_SM_STATUS6_RESERVED_FOR_ECO0_BITS                   5
#define DSC3B2_SM_STATUS6_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3b2 :: sm_status6 :: trnsum_pf [10:00] */
#define DSC3B2_SM_STATUS6_TRNSUM_PF_MASK                           0x07ff
#define DSC3B2_SM_STATUS6_TRNSUM_PF_ALIGN                          0
#define DSC3B2_SM_STATUS6_TRNSUM_PF_BITS                           11
#define DSC3B2_SM_STATUS6_TRNSUM_PF_SHIFT                          0


/****************************************************************************
 * Hypercore_USER_Dsc3b3
 ***************************************************************************/
/****************************************************************************
 * Dsc3b3 :: cdr_status0
 ***************************************************************************/
/* Dsc3b3 :: cdr_status0 :: integ_reg [15:00] */
#define DSC3B3_CDR_STATUS0_INTEG_REG_MASK                          0xffff
#define DSC3B3_CDR_STATUS0_INTEG_REG_ALIGN                         0
#define DSC3B3_CDR_STATUS0_INTEG_REG_BITS                          16
#define DSC3B3_CDR_STATUS0_INTEG_REG_SHIFT                         0


/****************************************************************************
 * Dsc3b3 :: cdr_status1
 ***************************************************************************/
/* Dsc3b3 :: cdr_status1 :: integ_reg_xfer [15:00] */
#define DSC3B3_CDR_STATUS1_INTEG_REG_XFER_MASK                     0xffff
#define DSC3B3_CDR_STATUS1_INTEG_REG_XFER_ALIGN                    0
#define DSC3B3_CDR_STATUS1_INTEG_REG_XFER_BITS                     16
#define DSC3B3_CDR_STATUS1_INTEG_REG_XFER_SHIFT                    0


/****************************************************************************
 * Dsc3b3 :: cdr_status2
 ***************************************************************************/
/* Dsc3b3 :: cdr_status2 :: reserved_for_eco0 [15:11] */
#define DSC3B3_CDR_STATUS2_RESERVED_FOR_ECO0_MASK                  0xf800
#define DSC3B3_CDR_STATUS2_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC3B3_CDR_STATUS2_RESERVED_FOR_ECO0_BITS                  5
#define DSC3B3_CDR_STATUS2_RESERVED_FOR_ECO0_SHIFT                 11

/* Dsc3b3 :: cdr_status2 :: sm_br_cdr_enabled [10:10] */
#define DSC3B3_CDR_STATUS2_SM_BR_CDR_ENABLED_MASK                  0x0400
#define DSC3B3_CDR_STATUS2_SM_BR_CDR_ENABLED_ALIGN                 0
#define DSC3B3_CDR_STATUS2_SM_BR_CDR_ENABLED_BITS                  1
#define DSC3B3_CDR_STATUS2_SM_BR_CDR_ENABLED_SHIFT                 10

/* Dsc3b3 :: cdr_status2 :: br_cdr_enabled [09:09] */
#define DSC3B3_CDR_STATUS2_BR_CDR_ENABLED_MASK                     0x0200
#define DSC3B3_CDR_STATUS2_BR_CDR_ENABLED_ALIGN                    0
#define DSC3B3_CDR_STATUS2_BR_CDR_ENABLED_BITS                     1
#define DSC3B3_CDR_STATUS2_BR_CDR_ENABLED_SHIFT                    9

/* Dsc3b3 :: cdr_status2 :: oscdr_mode [08:06] */
#define DSC3B3_CDR_STATUS2_OSCDR_MODE_MASK                         0x01c0
#define DSC3B3_CDR_STATUS2_OSCDR_MODE_ALIGN                        0
#define DSC3B3_CDR_STATUS2_OSCDR_MODE_BITS                         3
#define DSC3B3_CDR_STATUS2_OSCDR_MODE_SHIFT                        6

/* Dsc3b3 :: cdr_status2 :: phase_err [05:00] */
#define DSC3B3_CDR_STATUS2_PHASE_ERR_MASK                          0x003f
#define DSC3B3_CDR_STATUS2_PHASE_ERR_ALIGN                         0
#define DSC3B3_CDR_STATUS2_PHASE_ERR_BITS                          6
#define DSC3B3_CDR_STATUS2_PHASE_ERR_SHIFT                         0


/****************************************************************************
 * Dsc3b3 :: pi_status0
 ***************************************************************************/
/* Dsc3b3 :: pi_status0 :: invalid_intrp_ctrl0 [15:15] */
#define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL0_MASK                 0x8000
#define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL0_ALIGN                0
#define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL0_BITS                 1
#define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL0_SHIFT                15

/* Dsc3b3 :: pi_status0 :: invalid_intrp_ctrl90 [14:14] */
#define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL90_MASK                0x4000
#define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL90_ALIGN               0
#define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL90_BITS                1
#define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL90_SHIFT               14

/* Dsc3b3 :: pi_status0 :: clk90_phase_offset [13:07] */
#define DSC3B3_PI_STATUS0_CLK90_PHASE_OFFSET_MASK                  0x3f80
#define DSC3B3_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN                 0
#define DSC3B3_PI_STATUS0_CLK90_PHASE_OFFSET_BITS                  7
#define DSC3B3_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT                 7

/* Dsc3b3 :: pi_status0 :: phase_cntr [06:00] */
#define DSC3B3_PI_STATUS0_PHASE_CNTR_MASK                          0x007f
#define DSC3B3_PI_STATUS0_PHASE_CNTR_ALIGN                         0
#define DSC3B3_PI_STATUS0_PHASE_CNTR_BITS                          7
#define DSC3B3_PI_STATUS0_PHASE_CNTR_SHIFT                         0


/****************************************************************************
 * Dsc3b3 :: pi_status1
 ***************************************************************************/
/* union - case pi_Single0_lsb [15:00] */
/* Dsc3b3 :: pi_status1 :: Single0_lsb [15:00] */
#define DSC3B3_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_MASK          0xffff
#define DSC3B3_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_ALIGN         0
#define DSC3B3_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_BITS          16
#define DSC3B3_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_SHIFT         0


/* union - case pi_Single0_msb [15:00] */
/* Dsc3b3 :: pi_status1 :: Single0_msb [15:00] */
#define DSC3B3_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_MASK          0xffff
#define DSC3B3_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_ALIGN         0
#define DSC3B3_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_BITS          16
#define DSC3B3_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_SHIFT         0


/* union - case pi_Sequence0_lsb [15:00] */
/* Dsc3b3 :: pi_status1 :: Sequence0_lsb [15:00] */
#define DSC3B3_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_MASK      0xffff
#define DSC3B3_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_ALIGN     0
#define DSC3B3_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_BITS      16
#define DSC3B3_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_SHIFT     0


/* union - case pi_Sequence0_msb [15:00] */
/* Dsc3b3 :: pi_status1 :: Sequence0_msb [15:00] */
#define DSC3B3_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_MASK      0xffff
#define DSC3B3_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_ALIGN     0
#define DSC3B3_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_BITS      16
#define DSC3B3_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_SHIFT     0


/* union - case pi_Single90_lsb [15:00] */
/* Dsc3b3 :: pi_status1 :: Single90_lsb [15:00] */
#define DSC3B3_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_MASK        0xffff
#define DSC3B3_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_ALIGN       0
#define DSC3B3_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_BITS        16
#define DSC3B3_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_SHIFT       0


/* union - case pi_Single90_msb [15:00] */
/* Dsc3b3 :: pi_status1 :: Single90_msb [15:00] */
#define DSC3B3_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_MASK        0xffff
#define DSC3B3_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_ALIGN       0
#define DSC3B3_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_BITS        16
#define DSC3B3_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_SHIFT       0


/* union - case pi_Sequence90_lsb [15:00] */
/* Dsc3b3 :: pi_status1 :: Sequence90_lsb [15:00] */
#define DSC3B3_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_MASK    0xffff
#define DSC3B3_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_ALIGN   0
#define DSC3B3_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_BITS    16
#define DSC3B3_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_SHIFT   0


/* union - case pi_Sequence90_msb [15:00] */
/* Dsc3b3 :: pi_status1 :: Sequence90_msb [15:00] */
#define DSC3B3_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_MASK    0xffff
#define DSC3B3_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_ALIGN   0
#define DSC3B3_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_BITS    16
#define DSC3B3_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_SHIFT   0



/****************************************************************************
 * Dsc3b3 :: dfe_vga_status0
 ***************************************************************************/
/* Dsc3b3 :: dfe_vga_status0 :: reserved_for_eco0 [15:11] */
#define DSC3B3_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_MASK              0xf800
#define DSC3B3_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_ALIGN             0
#define DSC3B3_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_BITS              5
#define DSC3B3_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_SHIFT             11

/* Dsc3b3 :: dfe_vga_status0 :: vga_sum [10:06] */
#define DSC3B3_DFE_VGA_STATUS0_VGA_SUM_MASK                        0x07c0
#define DSC3B3_DFE_VGA_STATUS0_VGA_SUM_ALIGN                       0
#define DSC3B3_DFE_VGA_STATUS0_VGA_SUM_BITS                        5
#define DSC3B3_DFE_VGA_STATUS0_VGA_SUM_SHIFT                       6

/* Dsc3b3 :: dfe_vga_status0 :: dfe_tap_bin [05:00] */
#define DSC3B3_DFE_VGA_STATUS0_DFE_TAP_BIN_MASK                    0x003f
#define DSC3B3_DFE_VGA_STATUS0_DFE_TAP_BIN_ALIGN                   0
#define DSC3B3_DFE_VGA_STATUS0_DFE_TAP_BIN_BITS                    6
#define DSC3B3_DFE_VGA_STATUS0_DFE_TAP_BIN_SHIFT                   0


/****************************************************************************
 * Dsc3b3 :: dfe_vga_status1
 ***************************************************************************/
/* Dsc3b3 :: dfe_vga_status1 :: reserved_for_eco0 [15:11] */
#define DSC3B3_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_MASK              0xf800
#define DSC3B3_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_ALIGN             0
#define DSC3B3_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_BITS              5
#define DSC3B3_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_SHIFT             11

/* Dsc3b3 :: dfe_vga_status1 :: trnsum [10:00] */
#define DSC3B3_DFE_VGA_STATUS1_TRNSUM_MASK                         0x07ff
#define DSC3B3_DFE_VGA_STATUS1_TRNSUM_ALIGN                        0
#define DSC3B3_DFE_VGA_STATUS1_TRNSUM_BITS                         11
#define DSC3B3_DFE_VGA_STATUS1_TRNSUM_SHIFT                        0


/****************************************************************************
 * Dsc3b3 :: sm_status0
 ***************************************************************************/
/* Dsc3b3 :: sm_status0 :: reserved_for_eco0 [15:14] */
#define DSC3B3_SM_STATUS0_RESERVED_FOR_ECO0_MASK                   0xc000
#define DSC3B3_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B3_SM_STATUS0_RESERVED_FOR_ECO0_BITS                   2
#define DSC3B3_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT                  14

/* Dsc3b3 :: sm_status0 :: tuning_done [13:13] */
#define DSC3B3_SM_STATUS0_TUNING_DONE_MASK                         0x2000
#define DSC3B3_SM_STATUS0_TUNING_DONE_ALIGN                        0
#define DSC3B3_SM_STATUS0_TUNING_DONE_BITS                         1
#define DSC3B3_SM_STATUS0_TUNING_DONE_SHIFT                        13

/* Dsc3b3 :: sm_status0 :: srch_state [12:09] */
#define DSC3B3_SM_STATUS0_SRCH_STATE_MASK                          0x1e00
#define DSC3B3_SM_STATUS0_SRCH_STATE_ALIGN                         0
#define DSC3B3_SM_STATUS0_SRCH_STATE_BITS                          4
#define DSC3B3_SM_STATUS0_SRCH_STATE_SHIFT                         9

/* Dsc3b3 :: sm_status0 :: tuning_state [08:04] */
#define DSC3B3_SM_STATUS0_TUNING_STATE_MASK                        0x01f0
#define DSC3B3_SM_STATUS0_TUNING_STATE_ALIGN                       0
#define DSC3B3_SM_STATUS0_TUNING_STATE_BITS                        5
#define DSC3B3_SM_STATUS0_TUNING_STATE_SHIFT                       4

/* Dsc3b3 :: sm_status0 :: dsc_state [03:00] */
#define DSC3B3_SM_STATUS0_DSC_STATE_MASK                           0x000f
#define DSC3B3_SM_STATUS0_DSC_STATE_ALIGN                          0
#define DSC3B3_SM_STATUS0_DSC_STATE_BITS                           4
#define DSC3B3_SM_STATUS0_DSC_STATE_SHIFT                          0


/****************************************************************************
 * Dsc3b3 :: sm_status1
 ***************************************************************************/
/* Dsc3b3 :: sm_status1 :: reserved_for_eco0 [15:11] */
#define DSC3B3_SM_STATUS1_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3B3_SM_STATUS1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B3_SM_STATUS1_RESERVED_FOR_ECO0_BITS                   5
#define DSC3B3_SM_STATUS1_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3b3 :: sm_status1 :: postc_metric [10:00] */
#define DSC3B3_SM_STATUS1_POSTC_METRIC_MASK                        0x07ff
#define DSC3B3_SM_STATUS1_POSTC_METRIC_ALIGN                       0
#define DSC3B3_SM_STATUS1_POSTC_METRIC_BITS                        11
#define DSC3B3_SM_STATUS1_POSTC_METRIC_SHIFT                       0


/****************************************************************************
 * Dsc3b3 :: sm_status2
 ***************************************************************************/
/* Dsc3b3 :: sm_status2 :: reserved_for_eco0 [15:15] */
#define DSC3B3_SM_STATUS2_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC3B3_SM_STATUS2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B3_SM_STATUS2_RESERVED_FOR_ECO0_BITS                   1
#define DSC3B3_SM_STATUS2_RESERVED_FOR_ECO0_SHIFT                  15

/* Dsc3b3 :: sm_status2 :: slicer_offset_po [14:10] */
#define DSC3B3_SM_STATUS2_SLICER_OFFSET_PO_MASK                    0x7c00
#define DSC3B3_SM_STATUS2_SLICER_OFFSET_PO_ALIGN                   0
#define DSC3B3_SM_STATUS2_SLICER_OFFSET_PO_BITS                    5
#define DSC3B3_SM_STATUS2_SLICER_OFFSET_PO_SHIFT                   10

/* Dsc3b3 :: sm_status2 :: slicer_offset_zo [09:05] */
#define DSC3B3_SM_STATUS2_SLICER_OFFSET_ZO_MASK                    0x03e0
#define DSC3B3_SM_STATUS2_SLICER_OFFSET_ZO_ALIGN                   0
#define DSC3B3_SM_STATUS2_SLICER_OFFSET_ZO_BITS                    5
#define DSC3B3_SM_STATUS2_SLICER_OFFSET_ZO_SHIFT                   5

/* Dsc3b3 :: sm_status2 :: slicer_offset_mo [04:00] */
#define DSC3B3_SM_STATUS2_SLICER_OFFSET_MO_MASK                    0x001f
#define DSC3B3_SM_STATUS2_SLICER_OFFSET_MO_ALIGN                   0
#define DSC3B3_SM_STATUS2_SLICER_OFFSET_MO_BITS                    5
#define DSC3B3_SM_STATUS2_SLICER_OFFSET_MO_SHIFT                   0


/****************************************************************************
 * Dsc3b3 :: sm_status3
 ***************************************************************************/
/* Dsc3b3 :: sm_status3 :: reserved_for_eco0 [15:15] */
#define DSC3B3_SM_STATUS3_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC3B3_SM_STATUS3_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B3_SM_STATUS3_RESERVED_FOR_ECO0_BITS                   1
#define DSC3B3_SM_STATUS3_RESERVED_FOR_ECO0_SHIFT                  15

/* Dsc3b3 :: sm_status3 :: slicer_offset_pe [14:10] */
#define DSC3B3_SM_STATUS3_SLICER_OFFSET_PE_MASK                    0x7c00
#define DSC3B3_SM_STATUS3_SLICER_OFFSET_PE_ALIGN                   0
#define DSC3B3_SM_STATUS3_SLICER_OFFSET_PE_BITS                    5
#define DSC3B3_SM_STATUS3_SLICER_OFFSET_PE_SHIFT                   10

/* Dsc3b3 :: sm_status3 :: slicer_offset_ze [09:05] */
#define DSC3B3_SM_STATUS3_SLICER_OFFSET_ZE_MASK                    0x03e0
#define DSC3B3_SM_STATUS3_SLICER_OFFSET_ZE_ALIGN                   0
#define DSC3B3_SM_STATUS3_SLICER_OFFSET_ZE_BITS                    5
#define DSC3B3_SM_STATUS3_SLICER_OFFSET_ZE_SHIFT                   5

/* Dsc3b3 :: sm_status3 :: slicer_offset_me [04:00] */
#define DSC3B3_SM_STATUS3_SLICER_OFFSET_ME_MASK                    0x001f
#define DSC3B3_SM_STATUS3_SLICER_OFFSET_ME_ALIGN                   0
#define DSC3B3_SM_STATUS3_SLICER_OFFSET_ME_BITS                    5
#define DSC3B3_SM_STATUS3_SLICER_OFFSET_ME_SHIFT                   0


/****************************************************************************
 * Dsc3b3 :: sm_status4
 ***************************************************************************/
/* Dsc3b3 :: sm_status4 :: reserved_for_eco0 [15:09] */
#define DSC3B3_SM_STATUS4_RESERVED_FOR_ECO0_MASK                   0xfe00
#define DSC3B3_SM_STATUS4_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B3_SM_STATUS4_RESERVED_FOR_ECO0_BITS                   7
#define DSC3B3_SM_STATUS4_RESERVED_FOR_ECO0_SHIFT                  9

/* Dsc3b3 :: sm_status4 :: dfe_max [08:08] */
#define DSC3B3_SM_STATUS4_DFE_MAX_MASK                             0x0100
#define DSC3B3_SM_STATUS4_DFE_MAX_ALIGN                            0
#define DSC3B3_SM_STATUS4_DFE_MAX_BITS                             1
#define DSC3B3_SM_STATUS4_DFE_MAX_SHIFT                            8

/* Dsc3b3 :: sm_status4 :: dfe_min [07:07] */
#define DSC3B3_SM_STATUS4_DFE_MIN_MASK                             0x0080
#define DSC3B3_SM_STATUS4_DFE_MIN_ALIGN                            0
#define DSC3B3_SM_STATUS4_DFE_MIN_BITS                             1
#define DSC3B3_SM_STATUS4_DFE_MIN_SHIFT                            7

/* Dsc3b3 :: sm_status4 :: vga_max [06:06] */
#define DSC3B3_SM_STATUS4_VGA_MAX_MASK                             0x0040
#define DSC3B3_SM_STATUS4_VGA_MAX_ALIGN                            0
#define DSC3B3_SM_STATUS4_VGA_MAX_BITS                             1
#define DSC3B3_SM_STATUS4_VGA_MAX_SHIFT                            6

/* Dsc3b3 :: sm_status4 :: vga_min [05:05] */
#define DSC3B3_SM_STATUS4_VGA_MIN_MASK                             0x0020
#define DSC3B3_SM_STATUS4_VGA_MIN_ALIGN                            0
#define DSC3B3_SM_STATUS4_VGA_MIN_BITS                             1
#define DSC3B3_SM_STATUS4_VGA_MIN_SHIFT                            5

/* Dsc3b3 :: sm_status4 :: pf_max [04:04] */
#define DSC3B3_SM_STATUS4_PF_MAX_MASK                              0x0010
#define DSC3B3_SM_STATUS4_PF_MAX_ALIGN                             0
#define DSC3B3_SM_STATUS4_PF_MAX_BITS                              1
#define DSC3B3_SM_STATUS4_PF_MAX_SHIFT                             4

/* Dsc3b3 :: sm_status4 :: pf_min [03:03] */
#define DSC3B3_SM_STATUS4_PF_MIN_MASK                              0x0008
#define DSC3B3_SM_STATUS4_PF_MIN_ALIGN                             0
#define DSC3B3_SM_STATUS4_PF_MIN_BITS                              1
#define DSC3B3_SM_STATUS4_PF_MIN_SHIFT                             3

/* Dsc3b3 :: sm_status4 :: pf_ctrl [02:00] */
#define DSC3B3_SM_STATUS4_PF_CTRL_MASK                             0x0007
#define DSC3B3_SM_STATUS4_PF_CTRL_ALIGN                            0
#define DSC3B3_SM_STATUS4_PF_CTRL_BITS                             3
#define DSC3B3_SM_STATUS4_PF_CTRL_SHIFT                            0


/****************************************************************************
 * Dsc3b3 :: ana_status0
 ***************************************************************************/
/* Dsc3b3 :: ana_status0 :: reserved_for_eco0 [15:04] */
#define DSC3B3_ANA_STATUS0_RESERVED_FOR_ECO0_MASK                  0xfff0
#define DSC3B3_ANA_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC3B3_ANA_STATUS0_RESERVED_FOR_ECO0_BITS                  12
#define DSC3B3_ANA_STATUS0_RESERVED_FOR_ECO0_SHIFT                 4

/* Dsc3b3 :: ana_status0 :: pd_ch_p1 [03:03] */
#define DSC3B3_ANA_STATUS0_PD_CH_P1_MASK                           0x0008
#define DSC3B3_ANA_STATUS0_PD_CH_P1_ALIGN                          0
#define DSC3B3_ANA_STATUS0_PD_CH_P1_BITS                           1
#define DSC3B3_ANA_STATUS0_PD_CH_P1_SHIFT                          3

/* Dsc3b3 :: ana_status0 :: en_dfe_clk [02:02] */
#define DSC3B3_ANA_STATUS0_EN_DFE_CLK_MASK                         0x0004
#define DSC3B3_ANA_STATUS0_EN_DFE_CLK_ALIGN                        0
#define DSC3B3_ANA_STATUS0_EN_DFE_CLK_BITS                         1
#define DSC3B3_ANA_STATUS0_EN_DFE_CLK_SHIFT                        2

/* Dsc3b3 :: ana_status0 :: en_hgain [01:01] */
#define DSC3B3_ANA_STATUS0_EN_HGAIN_MASK                           0x0002
#define DSC3B3_ANA_STATUS0_EN_HGAIN_ALIGN                          0
#define DSC3B3_ANA_STATUS0_EN_HGAIN_BITS                           1
#define DSC3B3_ANA_STATUS0_EN_HGAIN_SHIFT                          1

/* Dsc3b3 :: ana_status0 :: offset_pd [00:00] */
#define DSC3B3_ANA_STATUS0_OFFSET_PD_MASK                          0x0001
#define DSC3B3_ANA_STATUS0_OFFSET_PD_ALIGN                         0
#define DSC3B3_ANA_STATUS0_OFFSET_PD_BITS                          1
#define DSC3B3_ANA_STATUS0_OFFSET_PD_SHIFT                         0


/****************************************************************************
 * Dsc3b3 :: sm_status5
 ***************************************************************************/
/* Dsc3b3 :: sm_status5 :: reserved_for_eco0 [15:11] */
#define DSC3B3_SM_STATUS5_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3B3_SM_STATUS5_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B3_SM_STATUS5_RESERVED_FOR_ECO0_BITS                   5
#define DSC3B3_SM_STATUS5_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3b3 :: sm_status5 :: trnsum_br_vga [10:00] */
#define DSC3B3_SM_STATUS5_TRNSUM_BR_VGA_MASK                       0x07ff
#define DSC3B3_SM_STATUS5_TRNSUM_BR_VGA_ALIGN                      0
#define DSC3B3_SM_STATUS5_TRNSUM_BR_VGA_BITS                       11
#define DSC3B3_SM_STATUS5_TRNSUM_BR_VGA_SHIFT                      0


/****************************************************************************
 * Dsc3b3 :: sm_status6
 ***************************************************************************/
/* Dsc3b3 :: sm_status6 :: reserved_for_eco0 [15:11] */
#define DSC3B3_SM_STATUS6_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3B3_SM_STATUS6_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3B3_SM_STATUS6_RESERVED_FOR_ECO0_BITS                   5
#define DSC3B3_SM_STATUS6_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3b3 :: sm_status6 :: trnsum_pf [10:00] */
#define DSC3B3_SM_STATUS6_TRNSUM_PF_MASK                           0x07ff
#define DSC3B3_SM_STATUS6_TRNSUM_PF_ALIGN                          0
#define DSC3B3_SM_STATUS6_TRNSUM_PF_BITS                           11
#define DSC3B3_SM_STATUS6_TRNSUM_PF_SHIFT                          0


/****************************************************************************
 * Hypercore_USER_Dsc3bB
 ***************************************************************************/
/****************************************************************************
 * Dsc3bB :: cdr_status0
 ***************************************************************************/
/* Dsc3bB :: cdr_status0 :: integ_reg [15:00] */
#define DSC3BB_CDR_STATUS0_INTEG_REG_MASK                          0xffff
#define DSC3BB_CDR_STATUS0_INTEG_REG_ALIGN                         0
#define DSC3BB_CDR_STATUS0_INTEG_REG_BITS                          16
#define DSC3BB_CDR_STATUS0_INTEG_REG_SHIFT                         0


/****************************************************************************
 * Dsc3bB :: cdr_status1
 ***************************************************************************/
/* Dsc3bB :: cdr_status1 :: integ_reg_xfer [15:00] */
#define DSC3BB_CDR_STATUS1_INTEG_REG_XFER_MASK                     0xffff
#define DSC3BB_CDR_STATUS1_INTEG_REG_XFER_ALIGN                    0
#define DSC3BB_CDR_STATUS1_INTEG_REG_XFER_BITS                     16
#define DSC3BB_CDR_STATUS1_INTEG_REG_XFER_SHIFT                    0


/****************************************************************************
 * Dsc3bB :: cdr_status2
 ***************************************************************************/
/* Dsc3bB :: cdr_status2 :: reserved_for_eco0 [15:11] */
#define DSC3BB_CDR_STATUS2_RESERVED_FOR_ECO0_MASK                  0xf800
#define DSC3BB_CDR_STATUS2_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC3BB_CDR_STATUS2_RESERVED_FOR_ECO0_BITS                  5
#define DSC3BB_CDR_STATUS2_RESERVED_FOR_ECO0_SHIFT                 11

/* Dsc3bB :: cdr_status2 :: sm_br_cdr_enabled [10:10] */
#define DSC3BB_CDR_STATUS2_SM_BR_CDR_ENABLED_MASK                  0x0400
#define DSC3BB_CDR_STATUS2_SM_BR_CDR_ENABLED_ALIGN                 0
#define DSC3BB_CDR_STATUS2_SM_BR_CDR_ENABLED_BITS                  1
#define DSC3BB_CDR_STATUS2_SM_BR_CDR_ENABLED_SHIFT                 10

/* Dsc3bB :: cdr_status2 :: br_cdr_enabled [09:09] */
#define DSC3BB_CDR_STATUS2_BR_CDR_ENABLED_MASK                     0x0200
#define DSC3BB_CDR_STATUS2_BR_CDR_ENABLED_ALIGN                    0
#define DSC3BB_CDR_STATUS2_BR_CDR_ENABLED_BITS                     1
#define DSC3BB_CDR_STATUS2_BR_CDR_ENABLED_SHIFT                    9

/* Dsc3bB :: cdr_status2 :: oscdr_mode [08:06] */
#define DSC3BB_CDR_STATUS2_OSCDR_MODE_MASK                         0x01c0
#define DSC3BB_CDR_STATUS2_OSCDR_MODE_ALIGN                        0
#define DSC3BB_CDR_STATUS2_OSCDR_MODE_BITS                         3
#define DSC3BB_CDR_STATUS2_OSCDR_MODE_SHIFT                        6

/* Dsc3bB :: cdr_status2 :: phase_err [05:00] */
#define DSC3BB_CDR_STATUS2_PHASE_ERR_MASK                          0x003f
#define DSC3BB_CDR_STATUS2_PHASE_ERR_ALIGN                         0
#define DSC3BB_CDR_STATUS2_PHASE_ERR_BITS                          6
#define DSC3BB_CDR_STATUS2_PHASE_ERR_SHIFT                         0


/****************************************************************************
 * Dsc3bB :: pi_status0
 ***************************************************************************/
/* Dsc3bB :: pi_status0 :: invalid_intrp_ctrl0 [15:15] */
#define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL0_MASK                 0x8000
#define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL0_ALIGN                0
#define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL0_BITS                 1
#define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL0_SHIFT                15

/* Dsc3bB :: pi_status0 :: invalid_intrp_ctrl90 [14:14] */
#define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL90_MASK                0x4000
#define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL90_ALIGN               0
#define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL90_BITS                1
#define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL90_SHIFT               14

/* Dsc3bB :: pi_status0 :: clk90_phase_offset [13:07] */
#define DSC3BB_PI_STATUS0_CLK90_PHASE_OFFSET_MASK                  0x3f80
#define DSC3BB_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN                 0
#define DSC3BB_PI_STATUS0_CLK90_PHASE_OFFSET_BITS                  7
#define DSC3BB_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT                 7

/* Dsc3bB :: pi_status0 :: phase_cntr [06:00] */
#define DSC3BB_PI_STATUS0_PHASE_CNTR_MASK                          0x007f
#define DSC3BB_PI_STATUS0_PHASE_CNTR_ALIGN                         0
#define DSC3BB_PI_STATUS0_PHASE_CNTR_BITS                          7
#define DSC3BB_PI_STATUS0_PHASE_CNTR_SHIFT                         0


/****************************************************************************
 * Dsc3bB :: pi_status1
 ***************************************************************************/
/* union - case pi_Single0_lsb [15:00] */
/* Dsc3bB :: pi_status1 :: Single0_lsb [15:00] */
#define DSC3BB_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_MASK          0xffff
#define DSC3BB_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_ALIGN         0
#define DSC3BB_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_BITS          16
#define DSC3BB_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_SHIFT         0


/* union - case pi_Single0_msb [15:00] */
/* Dsc3bB :: pi_status1 :: Single0_msb [15:00] */
#define DSC3BB_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_MASK          0xffff
#define DSC3BB_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_ALIGN         0
#define DSC3BB_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_BITS          16
#define DSC3BB_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_SHIFT         0


/* union - case pi_Sequence0_lsb [15:00] */
/* Dsc3bB :: pi_status1 :: Sequence0_lsb [15:00] */
#define DSC3BB_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_MASK      0xffff
#define DSC3BB_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_ALIGN     0
#define DSC3BB_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_BITS      16
#define DSC3BB_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_SHIFT     0


/* union - case pi_Sequence0_msb [15:00] */
/* Dsc3bB :: pi_status1 :: Sequence0_msb [15:00] */
#define DSC3BB_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_MASK      0xffff
#define DSC3BB_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_ALIGN     0
#define DSC3BB_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_BITS      16
#define DSC3BB_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_SHIFT     0


/* union - case pi_Single90_lsb [15:00] */
/* Dsc3bB :: pi_status1 :: Single90_lsb [15:00] */
#define DSC3BB_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_MASK        0xffff
#define DSC3BB_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_ALIGN       0
#define DSC3BB_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_BITS        16
#define DSC3BB_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_SHIFT       0


/* union - case pi_Single90_msb [15:00] */
/* Dsc3bB :: pi_status1 :: Single90_msb [15:00] */
#define DSC3BB_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_MASK        0xffff
#define DSC3BB_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_ALIGN       0
#define DSC3BB_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_BITS        16
#define DSC3BB_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_SHIFT       0


/* union - case pi_Sequence90_lsb [15:00] */
/* Dsc3bB :: pi_status1 :: Sequence90_lsb [15:00] */
#define DSC3BB_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_MASK    0xffff
#define DSC3BB_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_ALIGN   0
#define DSC3BB_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_BITS    16
#define DSC3BB_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_SHIFT   0


/* union - case pi_Sequence90_msb [15:00] */
/* Dsc3bB :: pi_status1 :: Sequence90_msb [15:00] */
#define DSC3BB_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_MASK    0xffff
#define DSC3BB_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_ALIGN   0
#define DSC3BB_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_BITS    16
#define DSC3BB_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_SHIFT   0



/****************************************************************************
 * Dsc3bB :: dfe_vga_status0
 ***************************************************************************/
/* Dsc3bB :: dfe_vga_status0 :: reserved_for_eco0 [15:11] */
#define DSC3BB_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_MASK              0xf800
#define DSC3BB_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_ALIGN             0
#define DSC3BB_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_BITS              5
#define DSC3BB_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_SHIFT             11

/* Dsc3bB :: dfe_vga_status0 :: vga_sum [10:06] */
#define DSC3BB_DFE_VGA_STATUS0_VGA_SUM_MASK                        0x07c0
#define DSC3BB_DFE_VGA_STATUS0_VGA_SUM_ALIGN                       0
#define DSC3BB_DFE_VGA_STATUS0_VGA_SUM_BITS                        5
#define DSC3BB_DFE_VGA_STATUS0_VGA_SUM_SHIFT                       6

/* Dsc3bB :: dfe_vga_status0 :: dfe_tap_bin [05:00] */
#define DSC3BB_DFE_VGA_STATUS0_DFE_TAP_BIN_MASK                    0x003f
#define DSC3BB_DFE_VGA_STATUS0_DFE_TAP_BIN_ALIGN                   0
#define DSC3BB_DFE_VGA_STATUS0_DFE_TAP_BIN_BITS                    6
#define DSC3BB_DFE_VGA_STATUS0_DFE_TAP_BIN_SHIFT                   0


/****************************************************************************
 * Dsc3bB :: dfe_vga_status1
 ***************************************************************************/
/* Dsc3bB :: dfe_vga_status1 :: reserved_for_eco0 [15:11] */
#define DSC3BB_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_MASK              0xf800
#define DSC3BB_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_ALIGN             0
#define DSC3BB_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_BITS              5
#define DSC3BB_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_SHIFT             11

/* Dsc3bB :: dfe_vga_status1 :: trnsum [10:00] */
#define DSC3BB_DFE_VGA_STATUS1_TRNSUM_MASK                         0x07ff
#define DSC3BB_DFE_VGA_STATUS1_TRNSUM_ALIGN                        0
#define DSC3BB_DFE_VGA_STATUS1_TRNSUM_BITS                         11
#define DSC3BB_DFE_VGA_STATUS1_TRNSUM_SHIFT                        0


/****************************************************************************
 * Dsc3bB :: sm_status0
 ***************************************************************************/
/* Dsc3bB :: sm_status0 :: reserved_for_eco0 [15:14] */
#define DSC3BB_SM_STATUS0_RESERVED_FOR_ECO0_MASK                   0xc000
#define DSC3BB_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3BB_SM_STATUS0_RESERVED_FOR_ECO0_BITS                   2
#define DSC3BB_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT                  14

/* Dsc3bB :: sm_status0 :: tuning_done [13:13] */
#define DSC3BB_SM_STATUS0_TUNING_DONE_MASK                         0x2000
#define DSC3BB_SM_STATUS0_TUNING_DONE_ALIGN                        0
#define DSC3BB_SM_STATUS0_TUNING_DONE_BITS                         1
#define DSC3BB_SM_STATUS0_TUNING_DONE_SHIFT                        13

/* Dsc3bB :: sm_status0 :: srch_state [12:09] */
#define DSC3BB_SM_STATUS0_SRCH_STATE_MASK                          0x1e00
#define DSC3BB_SM_STATUS0_SRCH_STATE_ALIGN                         0
#define DSC3BB_SM_STATUS0_SRCH_STATE_BITS                          4
#define DSC3BB_SM_STATUS0_SRCH_STATE_SHIFT                         9

/* Dsc3bB :: sm_status0 :: tuning_state [08:04] */
#define DSC3BB_SM_STATUS0_TUNING_STATE_MASK                        0x01f0
#define DSC3BB_SM_STATUS0_TUNING_STATE_ALIGN                       0
#define DSC3BB_SM_STATUS0_TUNING_STATE_BITS                        5
#define DSC3BB_SM_STATUS0_TUNING_STATE_SHIFT                       4

/* Dsc3bB :: sm_status0 :: dsc_state [03:00] */
#define DSC3BB_SM_STATUS0_DSC_STATE_MASK                           0x000f
#define DSC3BB_SM_STATUS0_DSC_STATE_ALIGN                          0
#define DSC3BB_SM_STATUS0_DSC_STATE_BITS                           4
#define DSC3BB_SM_STATUS0_DSC_STATE_SHIFT                          0


/****************************************************************************
 * Dsc3bB :: sm_status1
 ***************************************************************************/
/* Dsc3bB :: sm_status1 :: reserved_for_eco0 [15:11] */
#define DSC3BB_SM_STATUS1_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3BB_SM_STATUS1_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3BB_SM_STATUS1_RESERVED_FOR_ECO0_BITS                   5
#define DSC3BB_SM_STATUS1_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3bB :: sm_status1 :: postc_metric [10:00] */
#define DSC3BB_SM_STATUS1_POSTC_METRIC_MASK                        0x07ff
#define DSC3BB_SM_STATUS1_POSTC_METRIC_ALIGN                       0
#define DSC3BB_SM_STATUS1_POSTC_METRIC_BITS                        11
#define DSC3BB_SM_STATUS1_POSTC_METRIC_SHIFT                       0


/****************************************************************************
 * Dsc3bB :: sm_status2
 ***************************************************************************/
/* Dsc3bB :: sm_status2 :: reserved_for_eco0 [15:15] */
#define DSC3BB_SM_STATUS2_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC3BB_SM_STATUS2_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3BB_SM_STATUS2_RESERVED_FOR_ECO0_BITS                   1
#define DSC3BB_SM_STATUS2_RESERVED_FOR_ECO0_SHIFT                  15

/* Dsc3bB :: sm_status2 :: slicer_offset_po [14:10] */
#define DSC3BB_SM_STATUS2_SLICER_OFFSET_PO_MASK                    0x7c00
#define DSC3BB_SM_STATUS2_SLICER_OFFSET_PO_ALIGN                   0
#define DSC3BB_SM_STATUS2_SLICER_OFFSET_PO_BITS                    5
#define DSC3BB_SM_STATUS2_SLICER_OFFSET_PO_SHIFT                   10

/* Dsc3bB :: sm_status2 :: slicer_offset_zo [09:05] */
#define DSC3BB_SM_STATUS2_SLICER_OFFSET_ZO_MASK                    0x03e0
#define DSC3BB_SM_STATUS2_SLICER_OFFSET_ZO_ALIGN                   0
#define DSC3BB_SM_STATUS2_SLICER_OFFSET_ZO_BITS                    5
#define DSC3BB_SM_STATUS2_SLICER_OFFSET_ZO_SHIFT                   5

/* Dsc3bB :: sm_status2 :: slicer_offset_mo [04:00] */
#define DSC3BB_SM_STATUS2_SLICER_OFFSET_MO_MASK                    0x001f
#define DSC3BB_SM_STATUS2_SLICER_OFFSET_MO_ALIGN                   0
#define DSC3BB_SM_STATUS2_SLICER_OFFSET_MO_BITS                    5
#define DSC3BB_SM_STATUS2_SLICER_OFFSET_MO_SHIFT                   0


/****************************************************************************
 * Dsc3bB :: sm_status3
 ***************************************************************************/
/* Dsc3bB :: sm_status3 :: reserved_for_eco0 [15:15] */
#define DSC3BB_SM_STATUS3_RESERVED_FOR_ECO0_MASK                   0x8000
#define DSC3BB_SM_STATUS3_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3BB_SM_STATUS3_RESERVED_FOR_ECO0_BITS                   1
#define DSC3BB_SM_STATUS3_RESERVED_FOR_ECO0_SHIFT                  15

/* Dsc3bB :: sm_status3 :: slicer_offset_pe [14:10] */
#define DSC3BB_SM_STATUS3_SLICER_OFFSET_PE_MASK                    0x7c00
#define DSC3BB_SM_STATUS3_SLICER_OFFSET_PE_ALIGN                   0
#define DSC3BB_SM_STATUS3_SLICER_OFFSET_PE_BITS                    5
#define DSC3BB_SM_STATUS3_SLICER_OFFSET_PE_SHIFT                   10

/* Dsc3bB :: sm_status3 :: slicer_offset_ze [09:05] */
#define DSC3BB_SM_STATUS3_SLICER_OFFSET_ZE_MASK                    0x03e0
#define DSC3BB_SM_STATUS3_SLICER_OFFSET_ZE_ALIGN                   0
#define DSC3BB_SM_STATUS3_SLICER_OFFSET_ZE_BITS                    5
#define DSC3BB_SM_STATUS3_SLICER_OFFSET_ZE_SHIFT                   5

/* Dsc3bB :: sm_status3 :: slicer_offset_me [04:00] */
#define DSC3BB_SM_STATUS3_SLICER_OFFSET_ME_MASK                    0x001f
#define DSC3BB_SM_STATUS3_SLICER_OFFSET_ME_ALIGN                   0
#define DSC3BB_SM_STATUS3_SLICER_OFFSET_ME_BITS                    5
#define DSC3BB_SM_STATUS3_SLICER_OFFSET_ME_SHIFT                   0


/****************************************************************************
 * Dsc3bB :: sm_status4
 ***************************************************************************/
/* Dsc3bB :: sm_status4 :: reserved_for_eco0 [15:09] */
#define DSC3BB_SM_STATUS4_RESERVED_FOR_ECO0_MASK                   0xfe00
#define DSC3BB_SM_STATUS4_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3BB_SM_STATUS4_RESERVED_FOR_ECO0_BITS                   7
#define DSC3BB_SM_STATUS4_RESERVED_FOR_ECO0_SHIFT                  9

/* Dsc3bB :: sm_status4 :: dfe_max [08:08] */
#define DSC3BB_SM_STATUS4_DFE_MAX_MASK                             0x0100
#define DSC3BB_SM_STATUS4_DFE_MAX_ALIGN                            0
#define DSC3BB_SM_STATUS4_DFE_MAX_BITS                             1
#define DSC3BB_SM_STATUS4_DFE_MAX_SHIFT                            8

/* Dsc3bB :: sm_status4 :: dfe_min [07:07] */
#define DSC3BB_SM_STATUS4_DFE_MIN_MASK                             0x0080
#define DSC3BB_SM_STATUS4_DFE_MIN_ALIGN                            0
#define DSC3BB_SM_STATUS4_DFE_MIN_BITS                             1
#define DSC3BB_SM_STATUS4_DFE_MIN_SHIFT                            7

/* Dsc3bB :: sm_status4 :: vga_max [06:06] */
#define DSC3BB_SM_STATUS4_VGA_MAX_MASK                             0x0040
#define DSC3BB_SM_STATUS4_VGA_MAX_ALIGN                            0
#define DSC3BB_SM_STATUS4_VGA_MAX_BITS                             1
#define DSC3BB_SM_STATUS4_VGA_MAX_SHIFT                            6

/* Dsc3bB :: sm_status4 :: vga_min [05:05] */
#define DSC3BB_SM_STATUS4_VGA_MIN_MASK                             0x0020
#define DSC3BB_SM_STATUS4_VGA_MIN_ALIGN                            0
#define DSC3BB_SM_STATUS4_VGA_MIN_BITS                             1
#define DSC3BB_SM_STATUS4_VGA_MIN_SHIFT                            5

/* Dsc3bB :: sm_status4 :: pf_max [04:04] */
#define DSC3BB_SM_STATUS4_PF_MAX_MASK                              0x0010
#define DSC3BB_SM_STATUS4_PF_MAX_ALIGN                             0
#define DSC3BB_SM_STATUS4_PF_MAX_BITS                              1
#define DSC3BB_SM_STATUS4_PF_MAX_SHIFT                             4

/* Dsc3bB :: sm_status4 :: pf_min [03:03] */
#define DSC3BB_SM_STATUS4_PF_MIN_MASK                              0x0008
#define DSC3BB_SM_STATUS4_PF_MIN_ALIGN                             0
#define DSC3BB_SM_STATUS4_PF_MIN_BITS                              1
#define DSC3BB_SM_STATUS4_PF_MIN_SHIFT                             3

/* Dsc3bB :: sm_status4 :: pf_ctrl [02:00] */
#define DSC3BB_SM_STATUS4_PF_CTRL_MASK                             0x0007
#define DSC3BB_SM_STATUS4_PF_CTRL_ALIGN                            0
#define DSC3BB_SM_STATUS4_PF_CTRL_BITS                             3
#define DSC3BB_SM_STATUS4_PF_CTRL_SHIFT                            0


/****************************************************************************
 * Dsc3bB :: ana_status0
 ***************************************************************************/
/* Dsc3bB :: ana_status0 :: reserved_for_eco0 [15:04] */
#define DSC3BB_ANA_STATUS0_RESERVED_FOR_ECO0_MASK                  0xfff0
#define DSC3BB_ANA_STATUS0_RESERVED_FOR_ECO0_ALIGN                 0
#define DSC3BB_ANA_STATUS0_RESERVED_FOR_ECO0_BITS                  12
#define DSC3BB_ANA_STATUS0_RESERVED_FOR_ECO0_SHIFT                 4

/* Dsc3bB :: ana_status0 :: pd_ch_p1 [03:03] */
#define DSC3BB_ANA_STATUS0_PD_CH_P1_MASK                           0x0008
#define DSC3BB_ANA_STATUS0_PD_CH_P1_ALIGN                          0
#define DSC3BB_ANA_STATUS0_PD_CH_P1_BITS                           1
#define DSC3BB_ANA_STATUS0_PD_CH_P1_SHIFT                          3

/* Dsc3bB :: ana_status0 :: en_dfe_clk [02:02] */
#define DSC3BB_ANA_STATUS0_EN_DFE_CLK_MASK                         0x0004
#define DSC3BB_ANA_STATUS0_EN_DFE_CLK_ALIGN                        0
#define DSC3BB_ANA_STATUS0_EN_DFE_CLK_BITS                         1
#define DSC3BB_ANA_STATUS0_EN_DFE_CLK_SHIFT                        2

/* Dsc3bB :: ana_status0 :: en_hgain [01:01] */
#define DSC3BB_ANA_STATUS0_EN_HGAIN_MASK                           0x0002
#define DSC3BB_ANA_STATUS0_EN_HGAIN_ALIGN                          0
#define DSC3BB_ANA_STATUS0_EN_HGAIN_BITS                           1
#define DSC3BB_ANA_STATUS0_EN_HGAIN_SHIFT                          1

/* Dsc3bB :: ana_status0 :: offset_pd [00:00] */
#define DSC3BB_ANA_STATUS0_OFFSET_PD_MASK                          0x0001
#define DSC3BB_ANA_STATUS0_OFFSET_PD_ALIGN                         0
#define DSC3BB_ANA_STATUS0_OFFSET_PD_BITS                          1
#define DSC3BB_ANA_STATUS0_OFFSET_PD_SHIFT                         0


/****************************************************************************
 * Dsc3bB :: sm_status5
 ***************************************************************************/
/* Dsc3bB :: sm_status5 :: reserved_for_eco0 [15:11] */
#define DSC3BB_SM_STATUS5_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3BB_SM_STATUS5_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3BB_SM_STATUS5_RESERVED_FOR_ECO0_BITS                   5
#define DSC3BB_SM_STATUS5_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3bB :: sm_status5 :: trnsum_br_vga [10:00] */
#define DSC3BB_SM_STATUS5_TRNSUM_BR_VGA_MASK                       0x07ff
#define DSC3BB_SM_STATUS5_TRNSUM_BR_VGA_ALIGN                      0
#define DSC3BB_SM_STATUS5_TRNSUM_BR_VGA_BITS                       11
#define DSC3BB_SM_STATUS5_TRNSUM_BR_VGA_SHIFT                      0


/****************************************************************************
 * Dsc3bB :: sm_status6
 ***************************************************************************/
/* Dsc3bB :: sm_status6 :: reserved_for_eco0 [15:11] */
#define DSC3BB_SM_STATUS6_RESERVED_FOR_ECO0_MASK                   0xf800
#define DSC3BB_SM_STATUS6_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC3BB_SM_STATUS6_RESERVED_FOR_ECO0_BITS                   5
#define DSC3BB_SM_STATUS6_RESERVED_FOR_ECO0_SHIFT                  11

/* Dsc3bB :: sm_status6 :: trnsum_pf [10:00] */
#define DSC3BB_SM_STATUS6_TRNSUM_PF_MASK                           0x07ff
#define DSC3BB_SM_STATUS6_TRNSUM_PF_ALIGN                          0
#define DSC3BB_SM_STATUS6_TRNSUM_PF_BITS                           11
#define DSC3BB_SM_STATUS6_TRNSUM_PF_SHIFT                          0


/****************************************************************************
 * Hypercore_USER_Digital
 ***************************************************************************/
/****************************************************************************
 * Digital :: Control1000X1
 ***************************************************************************/
/* Digital :: Control1000X1 :: reserved0 [15:15] */
#define DIGITAL_CONTROL1000X1_RESERVED0_MASK                       0x8000
#define DIGITAL_CONTROL1000X1_RESERVED0_ALIGN                      0
#define DIGITAL_CONTROL1000X1_RESERVED0_BITS                       1
#define DIGITAL_CONTROL1000X1_RESERVED0_SHIFT                      15

/* Digital :: Control1000X1 :: disable_signal_detect_filter [14:14] */
#define DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_MASK    0x4000
#define DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_ALIGN   0
#define DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_BITS    1
#define DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_SHIFT   14

/* Digital :: Control1000X1 :: reserved1 [13:12] */
#define DIGITAL_CONTROL1000X1_RESERVED1_MASK                       0x3000
#define DIGITAL_CONTROL1000X1_RESERVED1_ALIGN                      0
#define DIGITAL_CONTROL1000X1_RESERVED1_BITS                       2
#define DIGITAL_CONTROL1000X1_RESERVED1_SHIFT                      12

/* Digital :: Control1000X1 :: sel_rx_pkts_for_cntr [11:11] */
#define DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_MASK            0x0800
#define DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_ALIGN           0
#define DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_BITS            1
#define DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_SHIFT           11

/* Digital :: Control1000X1 :: remote_loopback [10:10] */
#define DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_MASK                 0x0400
#define DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_ALIGN                0
#define DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_BITS                 1
#define DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_SHIFT                10

/* Digital :: Control1000X1 :: zero_comma_detector_phase [09:09] */
#define DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_MASK       0x0200
#define DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_ALIGN      0
#define DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_BITS       1
#define DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_SHIFT      9

/* Digital :: Control1000X1 :: comma_det_en [08:08] */
#define DIGITAL_CONTROL1000X1_COMMA_DET_EN_MASK                    0x0100
#define DIGITAL_CONTROL1000X1_COMMA_DET_EN_ALIGN                   0
#define DIGITAL_CONTROL1000X1_COMMA_DET_EN_BITS                    1
#define DIGITAL_CONTROL1000X1_COMMA_DET_EN_SHIFT                   8

/* Digital :: Control1000X1 :: crc_checker_disable [07:07] */
#define DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_MASK             0x0080
#define DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_ALIGN            0
#define DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_BITS             1
#define DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_SHIFT            7

/* Digital :: Control1000X1 :: disable_pll_pwrdwn [06:06] */
#define DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_MASK              0x0040
#define DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_ALIGN             0
#define DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_BITS              1
#define DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_SHIFT             6

/* Digital :: Control1000X1 :: sgmii_master_mode [05:05] */
#define DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_MASK               0x0020
#define DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_ALIGN              0
#define DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_BITS               1
#define DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_SHIFT              5

/* Digital :: Control1000X1 :: autodet_en [04:04] */
#define DIGITAL_CONTROL1000X1_AUTODET_EN_MASK                      0x0010
#define DIGITAL_CONTROL1000X1_AUTODET_EN_ALIGN                     0
#define DIGITAL_CONTROL1000X1_AUTODET_EN_BITS                      1
#define DIGITAL_CONTROL1000X1_AUTODET_EN_SHIFT                     4

/* Digital :: Control1000X1 :: invert_signal_detect [03:03] */
#define DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_MASK            0x0008
#define DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_ALIGN           0
#define DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_BITS            1
#define DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_SHIFT           3

/* Digital :: Control1000X1 :: signal_detect_en [02:02] */
#define DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_MASK                0x0004
#define DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_ALIGN               0
#define DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_BITS                1
#define DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_SHIFT               2

/* Digital :: Control1000X1 :: tbi_interface [01:01] */
#define DIGITAL_CONTROL1000X1_TBI_INTERFACE_MASK                   0x0002
#define DIGITAL_CONTROL1000X1_TBI_INTERFACE_ALIGN                  0
#define DIGITAL_CONTROL1000X1_TBI_INTERFACE_BITS                   1
#define DIGITAL_CONTROL1000X1_TBI_INTERFACE_SHIFT                  1

/* Digital :: Control1000X1 :: fiber_mode_1000X [00:00] */
#define DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_MASK                0x0001
#define DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_ALIGN               0
#define DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_BITS                1
#define DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_SHIFT               0


/****************************************************************************
 * Digital :: Control1000X2
 ***************************************************************************/
/* Digital :: Control1000X2 :: disable_extend_fdx_only [15:15] */
#define DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_MASK         0x8000
#define DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_ALIGN        0
#define DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_BITS         1
#define DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_SHIFT        15

/* Digital :: Control1000X2 :: clear_ber_counter [14:14] */
#define DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_MASK               0x4000
#define DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_ALIGN              0
#define DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_BITS               1
#define DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_SHIFT              14

/* Digital :: Control1000X2 :: transmit_idlejam_seq_test [13:13] */
#define DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_MASK       0x2000
#define DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_ALIGN      0
#define DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_BITS       1
#define DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_SHIFT      13

/* Digital :: Control1000X2 :: transmit_packet_seq_test [12:12] */
#define DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_MASK        0x1000
#define DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_ALIGN       0
#define DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_BITS        1
#define DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_SHIFT       12

/* Digital :: Control1000X2 :: test_cntr [11:11] */
#define DIGITAL_CONTROL1000X2_TEST_CNTR_MASK                       0x0800
#define DIGITAL_CONTROL1000X2_TEST_CNTR_ALIGN                      0
#define DIGITAL_CONTROL1000X2_TEST_CNTR_BITS                       1
#define DIGITAL_CONTROL1000X2_TEST_CNTR_SHIFT                      11

/* Digital :: Control1000X2 :: bypass_pcs_tx [10:10] */
#define DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_MASK                   0x0400
#define DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_ALIGN                  0
#define DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_BITS                   1
#define DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_SHIFT                  10

/* Digital :: Control1000X2 :: bypass_pcs_rx [09:09] */
#define DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_MASK                   0x0200
#define DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_ALIGN                  0
#define DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_BITS                   1
#define DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_SHIFT                  9

/* Digital :: Control1000X2 :: disable_TRRR_generation [08:08] */
#define DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_MASK         0x0100
#define DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_ALIGN        0
#define DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_BITS         1
#define DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_SHIFT        8

/* Digital :: Control1000X2 :: disable_carrier_extend [07:07] */
#define DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_MASK          0x0080
#define DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_ALIGN         0
#define DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_BITS          1
#define DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_SHIFT         7

/* Digital :: Control1000X2 :: autoneg_fast_timers [06:06] */
#define DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_MASK             0x0040
#define DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_ALIGN            0
#define DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_BITS             1
#define DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_SHIFT            6

/* Digital :: Control1000X2 :: force_xmit_data_on_txside [05:05] */
#define DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_MASK       0x0020
#define DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_ALIGN      0
#define DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_BITS       1
#define DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_SHIFT      5

/* Digital :: Control1000X2 :: disable_remote_fault_sensing [04:04] */
#define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_MASK    0x0010
#define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_ALIGN   0
#define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_BITS    1
#define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_SHIFT   4

/* Digital :: Control1000X2 :: enable_autoneg_err_timer [03:03] */
#define DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_MASK        0x0008
#define DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_ALIGN       0
#define DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_BITS        1
#define DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_SHIFT       3

/* Digital :: Control1000X2 :: filter_force_link [02:02] */
#define DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_MASK               0x0004
#define DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_ALIGN              0
#define DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_BITS               1
#define DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_SHIFT              2

/* Digital :: Control1000X2 :: disable_false_link [01:01] */
#define DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_MASK              0x0002
#define DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_ALIGN             0
#define DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_BITS              1
#define DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_SHIFT             1

/* Digital :: Control1000X2 :: enable_parallel_detection [00:00] */
#define DIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_MASK       0x0001
#define DIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_ALIGN      0
#define DIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_BITS       1
#define DIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_SHIFT      0


/****************************************************************************
 * Digital :: Control1000X3
 ***************************************************************************/
/* Digital :: Control1000X3 :: disable_packet_misalign [15:15] */
#define DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_MASK         0x8000
#define DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_ALIGN        0
#define DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_BITS         1
#define DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_SHIFT        15

/* Digital :: Control1000X3 :: rxfifo_gmii_reset [14:14] */
#define DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_MASK               0x4000
#define DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_ALIGN              0
#define DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_BITS               1
#define DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_SHIFT              14

/* Digital :: Control1000X3 :: disable_tx_crs [13:13] */
#define DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_MASK                  0x2000
#define DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_ALIGN                 0
#define DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_BITS                  1
#define DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_SHIFT                 13

/* Digital :: Control1000X3 :: invert_ext_phy_crs [12:12] */
#define DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_MASK              0x1000
#define DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_ALIGN             0
#define DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_BITS              1
#define DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_SHIFT             12

/* Digital :: Control1000X3 :: ext_phy_crs_mode [11:11] */
#define DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_MASK                0x0800
#define DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_ALIGN               0
#define DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_BITS                1
#define DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_SHIFT               11

/* Digital :: Control1000X3 :: jam_false_carrier_mode [10:10] */
#define DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_MASK          0x0400
#define DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_ALIGN         0
#define DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_BITS          1
#define DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_SHIFT         10

/* Digital :: Control1000X3 :: block_txen_mode [09:09] */
#define DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_MASK                 0x0200
#define DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_ALIGN                0
#define DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_BITS                 1
#define DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_SHIFT                9

/* Digital :: Control1000X3 :: force_txfifo_on [08:08] */
#define DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_MASK                 0x0100
#define DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_ALIGN                0
#define DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_BITS                 1
#define DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_SHIFT                8

/* Digital :: Control1000X3 :: bypass_txfifo1000 [07:07] */
#define DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_MASK               0x0080
#define DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_ALIGN              0
#define DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_BITS               1
#define DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_SHIFT              7

/* Digital :: Control1000X3 :: freq_lock_elasticity_tx [06:06] */
#define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_MASK         0x0040
#define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_ALIGN        0
#define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_BITS         1
#define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_SHIFT        6

/* Digital :: Control1000X3 :: freq_lock_elasticity_rx [05:05] */
#define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_MASK         0x0020
#define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_ALIGN        0
#define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_BITS         1
#define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_SHIFT        5

/* Digital :: Control1000X3 :: early_preamble_rx [04:04] */
#define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_MASK               0x0010
#define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_ALIGN              0
#define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_BITS               1
#define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_SHIFT              4

/* Digital :: Control1000X3 :: early_preamble_tx [03:03] */
#define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_MASK               0x0008
#define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_ALIGN              0
#define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_BITS               1
#define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_SHIFT              3

/* Digital :: Control1000X3 :: fifo_elasicity_tx_rx [02:01] */
#define DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_MASK            0x0006
#define DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_ALIGN           0
#define DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_BITS            2
#define DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_SHIFT           1

/* Digital :: Control1000X3 :: tx_fifo_rst [00:00] */
#define DIGITAL_CONTROL1000X3_TX_FIFO_RST_MASK                     0x0001
#define DIGITAL_CONTROL1000X3_TX_FIFO_RST_ALIGN                    0
#define DIGITAL_CONTROL1000X3_TX_FIFO_RST_BITS                     1
#define DIGITAL_CONTROL1000X3_TX_FIFO_RST_SHIFT                    0


/****************************************************************************
 * Digital :: Control1000X4
 ***************************************************************************/
/* Digital :: Control1000X4 :: reserved0 [15:14] */
#define DIGITAL_CONTROL1000X4_RESERVED0_MASK                       0xc000
#define DIGITAL_CONTROL1000X4_RESERVED0_ALIGN                      0
#define DIGITAL_CONTROL1000X4_RESERVED0_BITS                       2
#define DIGITAL_CONTROL1000X4_RESERVED0_SHIFT                      14

/* Digital :: Control1000X4 :: disable_resolution_err_restart [13:13] */
#define DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_MASK  0x2000
#define DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_ALIGN 0
#define DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_BITS  1
#define DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_SHIFT 13

/* Digital :: Control1000X4 :: enable_last_resolution_err [12:12] */
#define DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_MASK      0x1000
#define DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_ALIGN     0
#define DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_BITS      1
#define DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_SHIFT     12

/* Digital :: Control1000X4 :: tx_config_reg_sel [11:11] */
#define DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_MASK               0x0800
#define DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_ALIGN              0
#define DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_BITS               1
#define DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_SHIFT              11

/* Digital :: Control1000X4 :: zero_rxdgmii [10:10] */
#define DIGITAL_CONTROL1000X4_ZERO_RXDGMII_MASK                    0x0400
#define DIGITAL_CONTROL1000X4_ZERO_RXDGMII_ALIGN                   0
#define DIGITAL_CONTROL1000X4_ZERO_RXDGMII_BITS                    1
#define DIGITAL_CONTROL1000X4_ZERO_RXDGMII_SHIFT                   10

/* Digital :: Control1000X4 :: clear_linkdown [09:09] */
#define DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_MASK                  0x0200
#define DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_ALIGN                 0
#define DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_BITS                  1
#define DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_SHIFT                 9

/* Digital :: Control1000X4 :: latch_linkdown_enable [08:08] */
#define DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_MASK           0x0100
#define DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_ALIGN          0
#define DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_BITS           1
#define DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_SHIFT          8

/* Digital :: Control1000X4 :: link_force [07:07] */
#define DIGITAL_CONTROL1000X4_LINK_FORCE_MASK                      0x0080
#define DIGITAL_CONTROL1000X4_LINK_FORCE_ALIGN                     0
#define DIGITAL_CONTROL1000X4_LINK_FORCE_BITS                      1
#define DIGITAL_CONTROL1000X4_LINK_FORCE_SHIFT                     7

/* Digital :: Control1000X4 :: reserved1 [06:06] */
#define DIGITAL_CONTROL1000X4_RESERVED1_MASK                       0x0040
#define DIGITAL_CONTROL1000X4_RESERVED1_ALIGN                      0
#define DIGITAL_CONTROL1000X4_RESERVED1_BITS                       1
#define DIGITAL_CONTROL1000X4_RESERVED1_SHIFT                      6

/* Digital :: Control1000X4 :: lp_next_page_sel [05:05] */
#define DIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_MASK                0x0020
#define DIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_ALIGN               0
#define DIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_BITS                1
#define DIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_SHIFT               5

/* Digital :: Control1000X4 :: np_count_ClrnBp [04:04] */
#define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_MASK                 0x0010
#define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_ALIGN                0
#define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_BITS                 1
#define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_SHIFT                4

/* Digital :: Control1000X4 :: np_count_ClrnRd [03:03] */
#define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_MASK                 0x0008
#define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_ALIGN                0
#define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_BITS                 1
#define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_SHIFT                3

/* Digital :: Control1000X4 :: MiscRxStatus_sel [02:00] */
#define DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_MASK                0x0007
#define DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_ALIGN               0
#define DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_BITS                3
#define DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_SHIFT               0


/****************************************************************************
 * Digital :: Status1000X1
 ***************************************************************************/
/* Digital :: Status1000X1 :: txfifo_err_detected [15:15] */
#define DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK              0x8000
#define DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN             0
#define DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS              1
#define DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT             15

/* Digital :: Status1000X1 :: rxfifo_err_detected [14:14] */
#define DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK              0x4000
#define DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN             0
#define DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS              1
#define DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT             14

/* Digital :: Status1000X1 :: false_carrier_detected [13:13] */
#define DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK           0x2000
#define DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN          0
#define DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS           1
#define DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT          13

/* Digital :: Status1000X1 :: crc_err_detected [12:12] */
#define DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_MASK                 0x1000
#define DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_ALIGN                0
#define DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_BITS                 1
#define DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_SHIFT                12

/* Digital :: Status1000X1 :: tx_err_detected [11:11] */
#define DIGITAL_STATUS1000X1_TX_ERR_DETECTED_MASK                  0x0800
#define DIGITAL_STATUS1000X1_TX_ERR_DETECTED_ALIGN                 0
#define DIGITAL_STATUS1000X1_TX_ERR_DETECTED_BITS                  1
#define DIGITAL_STATUS1000X1_TX_ERR_DETECTED_SHIFT                 11

/* Digital :: Status1000X1 :: rx_err_detected [10:10] */
#define DIGITAL_STATUS1000X1_RX_ERR_DETECTED_MASK                  0x0400
#define DIGITAL_STATUS1000X1_RX_ERR_DETECTED_ALIGN                 0
#define DIGITAL_STATUS1000X1_RX_ERR_DETECTED_BITS                  1
#define DIGITAL_STATUS1000X1_RX_ERR_DETECTED_SHIFT                 10

/* Digital :: Status1000X1 :: carrier_extend_err_detected [09:09] */
#define DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK      0x0200
#define DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN     0
#define DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS      1
#define DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT     9

/* Digital :: Status1000X1 :: early_end_extension_detected [08:08] */
#define DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK     0x0100
#define DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN    0
#define DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS     1
#define DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT    8

/* Digital :: Status1000X1 :: link_status_change [07:07] */
#define DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_MASK               0x0080
#define DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN              0
#define DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_BITS               1
#define DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT              7

/* Digital :: Status1000X1 :: pause_resolution_rxside [06:06] */
#define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK          0x0040
#define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN         0
#define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS          1
#define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT         6

/* Digital :: Status1000X1 :: pause_resolution_txside [05:05] */
#define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK          0x0020
#define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN         0
#define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS          1
#define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT         5

/* Digital :: Status1000X1 :: speed_status [04:03] */
#define DIGITAL_STATUS1000X1_SPEED_STATUS_MASK                     0x0018
#define DIGITAL_STATUS1000X1_SPEED_STATUS_ALIGN                    0
#define DIGITAL_STATUS1000X1_SPEED_STATUS_BITS                     2
#define DIGITAL_STATUS1000X1_SPEED_STATUS_SHIFT                    3

/* Digital :: Status1000X1 :: duplex_status [02:02] */
#define DIGITAL_STATUS1000X1_DUPLEX_STATUS_MASK                    0x0004
#define DIGITAL_STATUS1000X1_DUPLEX_STATUS_ALIGN                   0
#define DIGITAL_STATUS1000X1_DUPLEX_STATUS_BITS                    1
#define DIGITAL_STATUS1000X1_DUPLEX_STATUS_SHIFT                   2

/* Digital :: Status1000X1 :: link_status [01:01] */
#define DIGITAL_STATUS1000X1_LINK_STATUS_MASK                      0x0002
#define DIGITAL_STATUS1000X1_LINK_STATUS_ALIGN                     0
#define DIGITAL_STATUS1000X1_LINK_STATUS_BITS                      1
#define DIGITAL_STATUS1000X1_LINK_STATUS_SHIFT                     1

/* Digital :: Status1000X1 :: sgmii_mode [00:00] */
#define DIGITAL_STATUS1000X1_SGMII_MODE_MASK                       0x0001
#define DIGITAL_STATUS1000X1_SGMII_MODE_ALIGN                      0
#define DIGITAL_STATUS1000X1_SGMII_MODE_BITS                       1
#define DIGITAL_STATUS1000X1_SGMII_MODE_SHIFT                      0


/****************************************************************************
 * Digital :: Status1000X2
 ***************************************************************************/
/* Digital :: Status1000X2 :: sgmii_mode_change [15:15] */
#define DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_MASK                0x8000
#define DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN               0
#define DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_BITS                1
#define DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT               15

/* Digital :: Status1000X2 :: consistency_mismatch [14:14] */
#define DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_MASK             0x4000
#define DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN            0
#define DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_BITS             1
#define DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT            14

/* Digital :: Status1000X2 :: autoneg_resolution_err [13:13] */
#define DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK           0x2000
#define DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN          0
#define DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS           1
#define DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT          13

/* Digital :: Status1000X2 :: sgmii_selector_mismatch [12:12] */
#define DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK          0x1000
#define DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN         0
#define DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS          1
#define DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT         12

/* Digital :: Status1000X2 :: sync_status_fail [11:11] */
#define DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_MASK                 0x0800
#define DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN                0
#define DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_BITS                 1
#define DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT                11

/* Digital :: Status1000X2 :: sync_status_ok [10:10] */
#define DIGITAL_STATUS1000X2_SYNC_STATUS_OK_MASK                   0x0400
#define DIGITAL_STATUS1000X2_SYNC_STATUS_OK_ALIGN                  0
#define DIGITAL_STATUS1000X2_SYNC_STATUS_OK_BITS                   1
#define DIGITAL_STATUS1000X2_SYNC_STATUS_OK_SHIFT                  10

/* Digital :: Status1000X2 :: rudi_c [09:09] */
#define DIGITAL_STATUS1000X2_RUDI_C_MASK                           0x0200
#define DIGITAL_STATUS1000X2_RUDI_C_ALIGN                          0
#define DIGITAL_STATUS1000X2_RUDI_C_BITS                           1
#define DIGITAL_STATUS1000X2_RUDI_C_SHIFT                          9

/* Digital :: Status1000X2 :: rudi_I [08:08] */
#define DIGITAL_STATUS1000X2_RUDI_I_MASK                           0x0100
#define DIGITAL_STATUS1000X2_RUDI_I_ALIGN                          0
#define DIGITAL_STATUS1000X2_RUDI_I_BITS                           1
#define DIGITAL_STATUS1000X2_RUDI_I_SHIFT                          8

/* Digital :: Status1000X2 :: rudi_invalid [07:07] */
#define DIGITAL_STATUS1000X2_RUDI_INVALID_MASK                     0x0080
#define DIGITAL_STATUS1000X2_RUDI_INVALID_ALIGN                    0
#define DIGITAL_STATUS1000X2_RUDI_INVALID_BITS                     1
#define DIGITAL_STATUS1000X2_RUDI_INVALID_SHIFT                    7

/* Digital :: Status1000X2 :: linkDown_syncLoss [06:06] */
#define DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK                0x0040
#define DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN               0
#define DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS                1
#define DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT               6

/* Digital :: Status1000X2 :: idle_detect_state [05:05] */
#define DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_MASK                0x0020
#define DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_ALIGN               0
#define DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_BITS                1
#define DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_SHIFT               5

/* Digital :: Status1000X2 :: complete_acknowledge_state [04:04] */
#define DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK       0x0010
#define DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN      0
#define DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS       1
#define DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT      4

/* Digital :: Status1000X2 :: acknowledge_detect_state [03:03] */
#define DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK         0x0008
#define DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN        0
#define DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS         1
#define DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT        3

/* Digital :: Status1000X2 :: ability_detect_state [02:02] */
#define DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_MASK             0x0004
#define DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN            0
#define DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_BITS             1
#define DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT            2

/* union - case anError [01:01] */
/* Digital :: Status1000X2 :: an_error_state [01:01] */
#define DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK           0x0002
#define DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN          0
#define DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS           1
#define DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT          1


/* union - case anDisableLink [01:01] */
/* Digital :: Status1000X2 :: an_disable_link_ok_state [01:01] */
#define DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002
#define DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0
#define DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1
#define DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1


/* Digital :: Status1000X2 :: an_enable_state [00:00] */
#define DIGITAL_STATUS1000X2_AN_ENABLE_STATE_MASK                  0x0001
#define DIGITAL_STATUS1000X2_AN_ENABLE_STATE_ALIGN                 0
#define DIGITAL_STATUS1000X2_AN_ENABLE_STATE_BITS                  1
#define DIGITAL_STATUS1000X2_AN_ENABLE_STATE_SHIFT                 0


/****************************************************************************
 * Digital :: Status1000X3
 ***************************************************************************/
/* Digital :: Status1000X3 :: reserved0 [15:13] */
#define DIGITAL_STATUS1000X3_RESERVED0_MASK                        0xe000
#define DIGITAL_STATUS1000X3_RESERVED0_ALIGN                       0
#define DIGITAL_STATUS1000X3_RESERVED0_BITS                        3
#define DIGITAL_STATUS1000X3_RESERVED0_SHIFT                       13

/* Digital :: Status1000X3 :: pd_park_an [12:12] */
#define DIGITAL_STATUS1000X3_PD_PARK_AN_MASK                       0x1000
#define DIGITAL_STATUS1000X3_PD_PARK_AN_ALIGN                      0
#define DIGITAL_STATUS1000X3_PD_PARK_AN_BITS                       1
#define DIGITAL_STATUS1000X3_PD_PARK_AN_SHIFT                      12

/* Digital :: Status1000X3 :: remotePhy_autosel [11:11] */
#define DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK                0x0800
#define DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN               0
#define DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS                1
#define DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT               11

/* Digital :: Status1000X3 :: latch_linkdown [10:10] */
#define DIGITAL_STATUS1000X3_LATCH_LINKDOWN_MASK                   0x0400
#define DIGITAL_STATUS1000X3_LATCH_LINKDOWN_ALIGN                  0
#define DIGITAL_STATUS1000X3_LATCH_LINKDOWN_BITS                   1
#define DIGITAL_STATUS1000X3_LATCH_LINKDOWN_SHIFT                  10

/* Digital :: Status1000X3 :: sd_filter [09:09] */
#define DIGITAL_STATUS1000X3_SD_FILTER_MASK                        0x0200
#define DIGITAL_STATUS1000X3_SD_FILTER_ALIGN                       0
#define DIGITAL_STATUS1000X3_SD_FILTER_BITS                        1
#define DIGITAL_STATUS1000X3_SD_FILTER_SHIFT                       9

/* Digital :: Status1000X3 :: sd_mux [08:08] */
#define DIGITAL_STATUS1000X3_SD_MUX_MASK                           0x0100
#define DIGITAL_STATUS1000X3_SD_MUX_ALIGN                          0
#define DIGITAL_STATUS1000X3_SD_MUX_BITS                           1
#define DIGITAL_STATUS1000X3_SD_MUX_SHIFT                          8

/* Digital :: Status1000X3 :: sd_filter_chg [07:07] */
#define DIGITAL_STATUS1000X3_SD_FILTER_CHG_MASK                    0x0080
#define DIGITAL_STATUS1000X3_SD_FILTER_CHG_ALIGN                   0
#define DIGITAL_STATUS1000X3_SD_FILTER_CHG_BITS                    1
#define DIGITAL_STATUS1000X3_SD_FILTER_CHG_SHIFT                   7

/* Digital :: Status1000X3 :: reserved1 [06:00] */
#define DIGITAL_STATUS1000X3_RESERVED1_MASK                        0x007f
#define DIGITAL_STATUS1000X3_RESERVED1_ALIGN                       0
#define DIGITAL_STATUS1000X3_RESERVED1_BITS                        7
#define DIGITAL_STATUS1000X3_RESERVED1_SHIFT                       0


/****************************************************************************
 * Digital :: BadCodeGroup
 ***************************************************************************/
/* Digital :: BadCodeGroup :: badCodeGroups [15:08] */
#define DIGITAL_BADCODEGROUP_BADCODEGROUPS_MASK                    0xff00
#define DIGITAL_BADCODEGROUP_BADCODEGROUPS_ALIGN                   0
#define DIGITAL_BADCODEGROUP_BADCODEGROUPS_BITS                    8
#define DIGITAL_BADCODEGROUP_BADCODEGROUPS_SHIFT                   8

/* Digital :: BadCodeGroup :: reserved0 [07:00] */
#define DIGITAL_BADCODEGROUP_RESERVED0_MASK                        0x00ff
#define DIGITAL_BADCODEGROUP_RESERVED0_ALIGN                       0
#define DIGITAL_BADCODEGROUP_RESERVED0_BITS                        8
#define DIGITAL_BADCODEGROUP_RESERVED0_SHIFT                       0


/****************************************************************************
 * Digital :: Misc1
 ***************************************************************************/
/* Digital :: Misc1 :: refclk_sel [15:13] */
#define DIGITAL_MISC1_REFCLK_SEL_MASK                              0xe000
#define DIGITAL_MISC1_REFCLK_SEL_ALIGN                             0
#define DIGITAL_MISC1_REFCLK_SEL_BITS                              3
#define DIGITAL_MISC1_REFCLK_SEL_SHIFT                             13
#define DIGITAL_MISC1_REFCLK_SEL_clk_25MHz                         0
#define DIGITAL_MISC1_REFCLK_SEL_clk_100MHz                        1
#define DIGITAL_MISC1_REFCLK_SEL_clk_125MHz                        2
#define DIGITAL_MISC1_REFCLK_SEL_clk_156p25MHz                     3
#define DIGITAL_MISC1_REFCLK_SEL_clk_187p5MHz                      4

/* Digital :: Misc1 :: force_pll_mode_afe_sel [12:12] */
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_MASK                  0x1000
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_ALIGN                 0
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_BITS                  1
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_SHIFT                 12

/* Digital :: Misc1 :: force_pll_mode_afe [11:08] */
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_MASK                      0x0f00
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_ALIGN                     0
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_BITS                      4
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_SHIFT                     8
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div16                     0
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div20                     1
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div24                     2
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div26                     3
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div30                     4
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div32                     5
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div36                     6
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div40                     7
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div42                     8
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div48                     9
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div50                     10
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div52                     11
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div60                     12
#define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div64                     13

/* Digital :: Misc1 :: force_tick0_sw2 [07:07] */
#define DIGITAL_MISC1_FORCE_TICK0_SW2_MASK                         0x0080
#define DIGITAL_MISC1_FORCE_TICK0_SW2_ALIGN                        0
#define DIGITAL_MISC1_FORCE_TICK0_SW2_BITS                         1
#define DIGITAL_MISC1_FORCE_TICK0_SW2_SHIFT                        7

/* Digital :: Misc1 :: tx_underrun_1000_dis [06:06] */
#define DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_MASK                    0x0040
#define DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_ALIGN                   0
#define DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_BITS                    1
#define DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_SHIFT                   6

/* Digital :: Misc1 :: force_ln_mode [05:05] */
#define DIGITAL_MISC1_FORCE_LN_MODE_MASK                           0x0020
#define DIGITAL_MISC1_FORCE_LN_MODE_ALIGN                          0
#define DIGITAL_MISC1_FORCE_LN_MODE_BITS                           1
#define DIGITAL_MISC1_FORCE_LN_MODE_SHIFT                          5

/* Digital :: Misc1 :: force_speed [04:00] */
#define DIGITAL_MISC1_FORCE_SPEED_MASK                             0x001f
#define DIGITAL_MISC1_FORCE_SPEED_ALIGN                            0
#define DIGITAL_MISC1_FORCE_SPEED_BITS                             5
#define DIGITAL_MISC1_FORCE_SPEED_SHIFT                            0
#define DIGITAL_MISC1_FORCE_SPEED_dr_2500BRCM_X1                   16
#define DIGITAL_MISC1_FORCE_SPEED_dr_5000BRCM_X4                   17
#define DIGITAL_MISC1_FORCE_SPEED_dr_6000BRCM_X4                   18
#define DIGITAL_MISC1_FORCE_SPEED_dr_10GHiGig_X4                   19
#define DIGITAL_MISC1_FORCE_SPEED_dr_10GBASE_CX4                   20
#define DIGITAL_MISC1_FORCE_SPEED_dr_12GHiGig_X4                   21
#define DIGITAL_MISC1_FORCE_SPEED_dr_12p5GHiGig_X4                 22
#define DIGITAL_MISC1_FORCE_SPEED_dr_13GHiGig_X4                   23
#define DIGITAL_MISC1_FORCE_SPEED_dr_15GHiGig_X4                   24
#define DIGITAL_MISC1_FORCE_SPEED_dr_16GHiGig_X4                   25
#define DIGITAL_MISC1_FORCE_SPEED_dr_5000BRCM_X1                   26
#define DIGITAL_MISC1_FORCE_SPEED_dr_6363BRCM_X1                   27
#define DIGITAL_MISC1_FORCE_SPEED_dr_20GHiGig_X4                   28
#define DIGITAL_MISC1_FORCE_SPEED_dr_21GHiGig_X4                   29
#define DIGITAL_MISC1_FORCE_SPEED_dr_25p45GHiGig_X4                30


/****************************************************************************
 * Digital :: Misc2
 ***************************************************************************/
/* Digital :: Misc2 :: rxckpl_sel_combo [15:15] */
#define DIGITAL_MISC2_RXCKPL_SEL_COMBO_MASK                        0x8000
#define DIGITAL_MISC2_RXCKPL_SEL_COMBO_ALIGN                       0
#define DIGITAL_MISC2_RXCKPL_SEL_COMBO_BITS                        1
#define DIGITAL_MISC2_RXCKPL_SEL_COMBO_SHIFT                       15

/* Digital :: Misc2 :: rxck_mii_gen_sel_force [14:14] */
#define DIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_MASK                  0x4000
#define DIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_ALIGN                 0
#define DIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_BITS                  1
#define DIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_SHIFT                 14

/* Digital :: Misc2 :: rxck_mii_gen_sel_val [13:13] */
#define DIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_MASK                    0x2000
#define DIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_ALIGN                   0
#define DIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_BITS                    1
#define DIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_SHIFT                   13

/* Digital :: Misc2 :: rlpbk_sw_force [12:12] */
#define DIGITAL_MISC2_RLPBK_SW_FORCE_MASK                          0x1000
#define DIGITAL_MISC2_RLPBK_SW_FORCE_ALIGN                         0
#define DIGITAL_MISC2_RLPBK_SW_FORCE_BITS                          1
#define DIGITAL_MISC2_RLPBK_SW_FORCE_SHIFT                         12

/* Digital :: Misc2 :: rlpbk_RxRst_en [11:11] */
#define DIGITAL_MISC2_RLPBK_RXRST_EN_MASK                          0x0800
#define DIGITAL_MISC2_RLPBK_RXRST_EN_ALIGN                         0
#define DIGITAL_MISC2_RLPBK_RXRST_EN_BITS                          1
#define DIGITAL_MISC2_RLPBK_RXRST_EN_SHIFT                         11

/* Digital :: Misc2 :: clkSigdet_bypass [10:10] */
#define DIGITAL_MISC2_CLKSIGDET_BYPASS_MASK                        0x0400
#define DIGITAL_MISC2_CLKSIGDET_BYPASS_ALIGN                       0
#define DIGITAL_MISC2_CLKSIGDET_BYPASS_BITS                        1
#define DIGITAL_MISC2_CLKSIGDET_BYPASS_SHIFT                       10

/* Digital :: Misc2 :: clk41_bypass [09:09] */
#define DIGITAL_MISC2_CLK41_BYPASS_MASK                            0x0200
#define DIGITAL_MISC2_CLK41_BYPASS_ALIGN                           0
#define DIGITAL_MISC2_CLK41_BYPASS_BITS                            1
#define DIGITAL_MISC2_CLK41_BYPASS_SHIFT                           9

/* Digital :: Misc2 :: miiGmiiDly_en [08:08] */
#define DIGITAL_MISC2_MIIGMIIDLY_EN_MASK                           0x0100
#define DIGITAL_MISC2_MIIGMIIDLY_EN_ALIGN                          0
#define DIGITAL_MISC2_MIIGMIIDLY_EN_BITS                           1
#define DIGITAL_MISC2_MIIGMIIDLY_EN_SHIFT                          8

/* Digital :: Misc2 :: miiGmiiMux_en [07:07] */
#define DIGITAL_MISC2_MIIGMIIMUX_EN_MASK                           0x0080
#define DIGITAL_MISC2_MIIGMIIMUX_EN_ALIGN                          0
#define DIGITAL_MISC2_MIIGMIIMUX_EN_BITS                           1
#define DIGITAL_MISC2_MIIGMIIMUX_EN_SHIFT                          7

/* Digital :: Misc2 :: KX_cl73_an_en [06:06] */
#define DIGITAL_MISC2_KX_CL73_AN_EN_MASK                           0x0040
#define DIGITAL_MISC2_KX_CL73_AN_EN_ALIGN                          0
#define DIGITAL_MISC2_KX_CL73_AN_EN_BITS                           1
#define DIGITAL_MISC2_KX_CL73_AN_EN_SHIFT                          6

/* Digital :: Misc2 :: pma_pmd_forced_speed_enc_en [05:05] */
#define DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_MASK             0x0020
#define DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_ALIGN            0
#define DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_BITS             1
#define DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_SHIFT            5

/* Digital :: Misc2 :: fifo_err_cya [04:04] */
#define DIGITAL_MISC2_FIFO_ERR_CYA_MASK                            0x0010
#define DIGITAL_MISC2_FIFO_ERR_CYA_ALIGN                           0
#define DIGITAL_MISC2_FIFO_ERR_CYA_BITS                            1
#define DIGITAL_MISC2_FIFO_ERR_CYA_SHIFT                           4

/* Digital :: Misc2 :: an_txdisablePhase [03:03] */
#define DIGITAL_MISC2_AN_TXDISABLEPHASE_MASK                       0x0008
#define DIGITAL_MISC2_AN_TXDISABLEPHASE_ALIGN                      0
#define DIGITAL_MISC2_AN_TXDISABLEPHASE_BITS                       1
#define DIGITAL_MISC2_AN_TXDISABLEPHASE_SHIFT                      3

/* Digital :: Misc2 :: an_rxSeqStartDis [02:02] */
#define DIGITAL_MISC2_AN_RXSEQSTARTDIS_MASK                        0x0004
#define DIGITAL_MISC2_AN_RXSEQSTARTDIS_ALIGN                       0
#define DIGITAL_MISC2_AN_RXSEQSTARTDIS_BITS                        1
#define DIGITAL_MISC2_AN_RXSEQSTARTDIS_SHIFT                       2

/* Digital :: Misc2 :: an_txdisable_ln [01:01] */
#define DIGITAL_MISC2_AN_TXDISABLE_LN_MASK                         0x0002
#define DIGITAL_MISC2_AN_TXDISABLE_LN_ALIGN                        0
#define DIGITAL_MISC2_AN_TXDISABLE_LN_BITS                         1
#define DIGITAL_MISC2_AN_TXDISABLE_LN_SHIFT                        1

/* Digital :: Misc2 :: an_deadTrap [00:00] */
#define DIGITAL_MISC2_AN_DEADTRAP_MASK                             0x0001
#define DIGITAL_MISC2_AN_DEADTRAP_ALIGN                            0
#define DIGITAL_MISC2_AN_DEADTRAP_BITS                             1
#define DIGITAL_MISC2_AN_DEADTRAP_SHIFT                            0


/****************************************************************************
 * Digital :: PatGenCtrl
 ***************************************************************************/
/* Digital :: PatGenCtrl :: reserved0 [15:15] */
#define DIGITAL_PATGENCTRL_RESERVED0_MASK                          0x8000
#define DIGITAL_PATGENCTRL_RESERVED0_ALIGN                         0
#define DIGITAL_PATGENCTRL_RESERVED0_BITS                          1
#define DIGITAL_PATGENCTRL_RESERVED0_SHIFT                         15

/* Digital :: PatGenCtrl :: tx_err [14:14] */
#define DIGITAL_PATGENCTRL_TX_ERR_MASK                             0x4000
#define DIGITAL_PATGENCTRL_TX_ERR_ALIGN                            0
#define DIGITAL_PATGENCTRL_TX_ERR_BITS                             1
#define DIGITAL_PATGENCTRL_TX_ERR_SHIFT                            14

/* Digital :: PatGenCtrl :: skip_crc [13:13] */
#define DIGITAL_PATGENCTRL_SKIP_CRC_MASK                           0x2000
#define DIGITAL_PATGENCTRL_SKIP_CRC_ALIGN                          0
#define DIGITAL_PATGENCTRL_SKIP_CRC_BITS                           1
#define DIGITAL_PATGENCTRL_SKIP_CRC_SHIFT                          13

/* Digital :: PatGenCtrl :: en_crc_checker_fragment_err_det [12:12] */
#define DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_MASK    0x1000
#define DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_ALIGN   0
#define DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_BITS    1
#define DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_SHIFT   12

/* Digital :: PatGenCtrl :: ipg_select [11:09] */
#define DIGITAL_PATGENCTRL_IPG_SELECT_MASK                         0x0e00
#define DIGITAL_PATGENCTRL_IPG_SELECT_ALIGN                        0
#define DIGITAL_PATGENCTRL_IPG_SELECT_BITS                         3
#define DIGITAL_PATGENCTRL_IPG_SELECT_SHIFT                        9

/* Digital :: PatGenCtrl :: pkt_size [08:03] */
#define DIGITAL_PATGENCTRL_PKT_SIZE_MASK                           0x01f8
#define DIGITAL_PATGENCTRL_PKT_SIZE_ALIGN                          0
#define DIGITAL_PATGENCTRL_PKT_SIZE_BITS                           6
#define DIGITAL_PATGENCTRL_PKT_SIZE_SHIFT                          3

/* Digital :: PatGenCtrl :: single_pass_mode [02:02] */
#define DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_MASK                   0x0004
#define DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_ALIGN                  0
#define DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_BITS                   1
#define DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_SHIFT                  2

/* Digital :: PatGenCtrl :: run_pattern_gen [01:01] */
#define DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_MASK                    0x0002
#define DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_ALIGN                   0
#define DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_BITS                    1
#define DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_SHIFT                   1

/* Digital :: PatGenCtrl :: sel_pattern_gen_data [00:00] */
#define DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_MASK               0x0001
#define DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_ALIGN              0
#define DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_BITS               1
#define DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_SHIFT              0


/****************************************************************************
 * Digital :: PatGenStat
 ***************************************************************************/
/* Digital :: PatGenStat :: reserved0 [15:04] */
#define DIGITAL_PATGENSTAT_RESERVED0_MASK                          0xfff0
#define DIGITAL_PATGENSTAT_RESERVED0_ALIGN                         0
#define DIGITAL_PATGENSTAT_RESERVED0_BITS                          12
#define DIGITAL_PATGENSTAT_RESERVED0_SHIFT                         4

/* Digital :: PatGenStat :: pattern_gen_active [03:03] */
#define DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_MASK                 0x0008
#define DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_ALIGN                0
#define DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_BITS                 1
#define DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_SHIFT                3

/* Digital :: PatGenStat :: pattern_gen_fsm [02:00] */
#define DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_MASK                    0x0007
#define DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_ALIGN                   0
#define DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_BITS                    3
#define DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_SHIFT                   0


/****************************************************************************
 * Digital :: TestMode
 ***************************************************************************/
/* Digital :: TestMode :: disable_reset_cnt [15:15] */
#define DIGITAL_TESTMODE_DISABLE_RESET_CNT_MASK                    0x8000
#define DIGITAL_TESTMODE_DISABLE_RESET_CNT_ALIGN                   0
#define DIGITAL_TESTMODE_DISABLE_RESET_CNT_BITS                    1
#define DIGITAL_TESTMODE_DISABLE_RESET_CNT_SHIFT                   15

/* Digital :: TestMode :: clear_packet_counters [14:14] */
#define DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_MASK                0x4000
#define DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_ALIGN               0
#define DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_BITS                1
#define DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_SHIFT               14

/* Digital :: TestMode :: reserved0 [13:12] */
#define DIGITAL_TESTMODE_RESERVED0_MASK                            0x3000
#define DIGITAL_TESTMODE_RESERVED0_ALIGN                           0
#define DIGITAL_TESTMODE_RESERVED0_BITS                            2
#define DIGITAL_TESTMODE_RESERVED0_SHIFT                           12

/* Digital :: TestMode :: test_monitor_mode2 [11:06] */
#define DIGITAL_TESTMODE_TEST_MONITOR_MODE2_MASK                   0x0fc0
#define DIGITAL_TESTMODE_TEST_MONITOR_MODE2_ALIGN                  0
#define DIGITAL_TESTMODE_TEST_MONITOR_MODE2_BITS                   6
#define DIGITAL_TESTMODE_TEST_MONITOR_MODE2_SHIFT                  6

/* Digital :: TestMode :: test_monitor_mode1 [05:00] */
#define DIGITAL_TESTMODE_TEST_MONITOR_MODE1_MASK                   0x003f
#define DIGITAL_TESTMODE_TEST_MONITOR_MODE1_ALIGN                  0
#define DIGITAL_TESTMODE_TEST_MONITOR_MODE1_BITS                   6
#define DIGITAL_TESTMODE_TEST_MONITOR_MODE1_SHIFT                  0


/****************************************************************************
 * Digital :: TxPktCnt
 ***************************************************************************/
/* Digital :: TxPktCnt :: TxPktCnt [15:00] */
#define DIGITAL_TXPKTCNT_TXPKTCNT_MASK                             0xffff
#define DIGITAL_TXPKTCNT_TXPKTCNT_ALIGN                            0
#define DIGITAL_TXPKTCNT_TXPKTCNT_BITS                             16
#define DIGITAL_TXPKTCNT_TXPKTCNT_SHIFT                            0


/****************************************************************************
 * Digital :: RxPktCnt
 ***************************************************************************/
/* Digital :: RxPktCnt :: RxPktCnt [15:00] */
#define DIGITAL_RXPKTCNT_RXPKTCNT_MASK                             0xffff
#define DIGITAL_RXPKTCNT_RXPKTCNT_ALIGN                            0
#define DIGITAL_RXPKTCNT_RXPKTCNT_BITS                             16
#define DIGITAL_RXPKTCNT_RXPKTCNT_SHIFT                            0


/****************************************************************************
 * Hypercore_USER_Test
 ***************************************************************************/
/****************************************************************************
 * Test :: serdesID0
 ***************************************************************************/
/* Test :: serdesID0 :: rev_letter [15:14] */
#define TEST_SERDESID0_REV_LETTER_MASK                             0xc000
#define TEST_SERDESID0_REV_LETTER_ALIGN                            0
#define TEST_SERDESID0_REV_LETTER_BITS                             2
#define TEST_SERDESID0_REV_LETTER_SHIFT                            14

/* Test :: serdesID0 :: rev_number [13:11] */
#define TEST_SERDESID0_REV_NUMBER_MASK                             0x3800
#define TEST_SERDESID0_REV_NUMBER_ALIGN                            0
#define TEST_SERDESID0_REV_NUMBER_BITS                             3
#define TEST_SERDESID0_REV_NUMBER_SHIFT                            11

/* Test :: serdesID0 :: bonding [10:09] */
#define TEST_SERDESID0_BONDING_MASK                                0x0600
#define TEST_SERDESID0_BONDING_ALIGN                               0
#define TEST_SERDESID0_BONDING_BITS                                2
#define TEST_SERDESID0_BONDING_SHIFT                               9

/* Test :: serdesID0 :: tech_proc [08:06] */
#define TEST_SERDESID0_TECH_PROC_MASK                              0x01c0
#define TEST_SERDESID0_TECH_PROC_ALIGN                             0
#define TEST_SERDESID0_TECH_PROC_BITS                              3
#define TEST_SERDESID0_TECH_PROC_SHIFT                             6

/* Test :: serdesID0 :: model_number [05:00] */
#define TEST_SERDESID0_MODEL_NUMBER_MASK                           0x003f
#define TEST_SERDESID0_MODEL_NUMBER_ALIGN                          0
#define TEST_SERDESID0_MODEL_NUMBER_BITS                           6
#define TEST_SERDESID0_MODEL_NUMBER_SHIFT                          0


/****************************************************************************
 * Test :: serdesID1
 ***************************************************************************/
/* Test :: serdesID1 :: multiplicity [15:12] */
#define TEST_SERDESID1_MULTIPLICITY_MASK                           0xf000
#define TEST_SERDESID1_MULTIPLICITY_ALIGN                          0
#define TEST_SERDESID1_MULTIPLICITY_BITS                           4
#define TEST_SERDESID1_MULTIPLICITY_SHIFT                          12

/* Test :: serdesID1 :: CL37 [11:11] */
#define TEST_SERDESID1_CL37_MASK                                   0x0800
#define TEST_SERDESID1_CL37_ALIGN                                  0
#define TEST_SERDESID1_CL37_BITS                                   1
#define TEST_SERDESID1_CL37_SHIFT                                  11

/* Test :: serdesID1 :: CL73 [10:10] */
#define TEST_SERDESID1_CL73_MASK                                   0x0400
#define TEST_SERDESID1_CL73_ALIGN                                  0
#define TEST_SERDESID1_CL73_BITS                                   1
#define TEST_SERDESID1_CL73_SHIFT                                  10

/* Test :: serdesID1 :: CL36 [09:09] */
#define TEST_SERDESID1_CL36_MASK                                   0x0200
#define TEST_SERDESID1_CL36_ALIGN                                  0
#define TEST_SERDESID1_CL36_BITS                                   1
#define TEST_SERDESID1_CL36_SHIFT                                  9

/* Test :: serdesID1 :: CL48 [08:08] */
#define TEST_SERDESID1_CL48_MASK                                   0x0100
#define TEST_SERDESID1_CL48_ALIGN                                  0
#define TEST_SERDESID1_CL48_BITS                                   1
#define TEST_SERDESID1_CL48_SHIFT                                  8

/* Test :: serdesID1 :: HiGig [07:07] */
#define TEST_SERDESID1_HIGIG_MASK                                  0x0080
#define TEST_SERDESID1_HIGIG_ALIGN                                 0
#define TEST_SERDESID1_HIGIG_BITS                                  1
#define TEST_SERDESID1_HIGIG_SHIFT                                 7

/* Test :: serdesID1 :: HiGigII [06:06] */
#define TEST_SERDESID1_HIGIGII_MASK                                0x0040
#define TEST_SERDESID1_HIGIGII_ALIGN                               0
#define TEST_SERDESID1_HIGIGII_BITS                                1
#define TEST_SERDESID1_HIGIGII_SHIFT                               6

/* Test :: serdesID1 :: PCIE [05:05] */
#define TEST_SERDESID1_PCIE_MASK                                   0x0020
#define TEST_SERDESID1_PCIE_ALIGN                                  0
#define TEST_SERDESID1_PCIE_BITS                                   1
#define TEST_SERDESID1_PCIE_SHIFT                                  5

/* Test :: serdesID1 :: PCIE_II [04:04] */
#define TEST_SERDESID1_PCIE_II_MASK                                0x0010
#define TEST_SERDESID1_PCIE_II_ALIGN                               0
#define TEST_SERDESID1_PCIE_II_BITS                                1
#define TEST_SERDESID1_PCIE_II_SHIFT                               4

/* Test :: serdesID1 :: brcm_64B66B [03:03] */
#define TEST_SERDESID1_BRCM_64B66B_MASK                            0x0008
#define TEST_SERDESID1_BRCM_64B66B_ALIGN                           0
#define TEST_SERDESID1_BRCM_64B66B_BITS                            1
#define TEST_SERDESID1_BRCM_64B66B_SHIFT                           3

/* Test :: serdesID1 :: Scrambler [02:02] */
#define TEST_SERDESID1_SCRAMBLER_MASK                              0x0004
#define TEST_SERDESID1_SCRAMBLER_ALIGN                             0
#define TEST_SERDESID1_SCRAMBLER_BITS                              1
#define TEST_SERDESID1_SCRAMBLER_SHIFT                             2

/* Test :: serdesID1 :: reserved0 [01:00] */
#define TEST_SERDESID1_RESERVED0_MASK                              0x0003
#define TEST_SERDESID1_RESERVED0_ALIGN                             0
#define TEST_SERDESID1_RESERVED0_BITS                              2
#define TEST_SERDESID1_RESERVED0_SHIFT                             0


/****************************************************************************
 * Test :: serdesID2
 ***************************************************************************/
/* Test :: serdesID2 :: ID3present [15:15] */
#define TEST_SERDESID2_ID3PRESENT_MASK                             0x8000
#define TEST_SERDESID2_ID3PRESENT_ALIGN                            0
#define TEST_SERDESID2_ID3PRESENT_BITS                             1
#define TEST_SERDESID2_ID3PRESENT_SHIFT                            15

/* Test :: serdesID2 :: dr_25G_4L [14:14] */
#define TEST_SERDESID2_DR_25G_4L_MASK                              0x4000
#define TEST_SERDESID2_DR_25G_4L_ALIGN                             0
#define TEST_SERDESID2_DR_25G_4L_BITS                              1
#define TEST_SERDESID2_DR_25G_4L_SHIFT                             14

/* Test :: serdesID2 :: dr_21G_4L [13:13] */
#define TEST_SERDESID2_DR_21G_4L_MASK                              0x2000
#define TEST_SERDESID2_DR_21G_4L_ALIGN                             0
#define TEST_SERDESID2_DR_21G_4L_BITS                              1
#define TEST_SERDESID2_DR_21G_4L_SHIFT                             13

/* Test :: serdesID2 :: dr_20G_4L [12:12] */
#define TEST_SERDESID2_DR_20G_4L_MASK                              0x1000
#define TEST_SERDESID2_DR_20G_4L_ALIGN                             0
#define TEST_SERDESID2_DR_20G_4L_BITS                              1
#define TEST_SERDESID2_DR_20G_4L_SHIFT                             12

/* Test :: serdesID2 :: dr_16G_4L [11:11] */
#define TEST_SERDESID2_DR_16G_4L_MASK                              0x0800
#define TEST_SERDESID2_DR_16G_4L_ALIGN                             0
#define TEST_SERDESID2_DR_16G_4L_BITS                              1
#define TEST_SERDESID2_DR_16G_4L_SHIFT                             11

/* Test :: serdesID2 :: dr_15G_4L [10:10] */
#define TEST_SERDESID2_DR_15G_4L_MASK                              0x0400
#define TEST_SERDESID2_DR_15G_4L_ALIGN                             0
#define TEST_SERDESID2_DR_15G_4L_BITS                              1
#define TEST_SERDESID2_DR_15G_4L_SHIFT                             10

/* Test :: serdesID2 :: dr_13G_4L [09:09] */
#define TEST_SERDESID2_DR_13G_4L_MASK                              0x0200
#define TEST_SERDESID2_DR_13G_4L_ALIGN                             0
#define TEST_SERDESID2_DR_13G_4L_BITS                              1
#define TEST_SERDESID2_DR_13G_4L_SHIFT                             9

/* Test :: serdesID2 :: dr_12_5G_4L [08:08] */
#define TEST_SERDESID2_DR_12_5G_4L_MASK                            0x0100
#define TEST_SERDESID2_DR_12_5G_4L_ALIGN                           0
#define TEST_SERDESID2_DR_12_5G_4L_BITS                            1
#define TEST_SERDESID2_DR_12_5G_4L_SHIFT                           8

/* Test :: serdesID2 :: dr_12G_4L [07:07] */
#define TEST_SERDESID2_DR_12G_4L_MASK                              0x0080
#define TEST_SERDESID2_DR_12G_4L_ALIGN                             0
#define TEST_SERDESID2_DR_12G_4L_BITS                              1
#define TEST_SERDESID2_DR_12G_4L_SHIFT                             7

/* Test :: serdesID2 :: dr_10G_4L [06:06] */
#define TEST_SERDESID2_DR_10G_4L_MASK                              0x0040
#define TEST_SERDESID2_DR_10G_4L_ALIGN                             0
#define TEST_SERDESID2_DR_10G_4L_BITS                              1
#define TEST_SERDESID2_DR_10G_4L_SHIFT                             6

/* Test :: serdesID2 :: dr_6G_4L [05:05] */
#define TEST_SERDESID2_DR_6G_4L_MASK                               0x0020
#define TEST_SERDESID2_DR_6G_4L_ALIGN                              0
#define TEST_SERDESID2_DR_6G_4L_BITS                               1
#define TEST_SERDESID2_DR_6G_4L_SHIFT                              5

/* Test :: serdesID2 :: dr_5G_4L [04:04] */
#define TEST_SERDESID2_DR_5G_4L_MASK                               0x0010
#define TEST_SERDESID2_DR_5G_4L_ALIGN                              0
#define TEST_SERDESID2_DR_5G_4L_BITS                               1
#define TEST_SERDESID2_DR_5G_4L_SHIFT                              4

/* Test :: serdesID2 :: dr_2p5G_SL [03:03] */
#define TEST_SERDESID2_DR_2P5G_SL_MASK                             0x0008
#define TEST_SERDESID2_DR_2P5G_SL_ALIGN                            0
#define TEST_SERDESID2_DR_2P5G_SL_BITS                             1
#define TEST_SERDESID2_DR_2P5G_SL_SHIFT                            3

/* Test :: serdesID2 :: dr_1G_SL [02:02] */
#define TEST_SERDESID2_DR_1G_SL_MASK                               0x0004
#define TEST_SERDESID2_DR_1G_SL_ALIGN                              0
#define TEST_SERDESID2_DR_1G_SL_BITS                               1
#define TEST_SERDESID2_DR_1G_SL_SHIFT                              2

/* Test :: serdesID2 :: dr_100M_SL [01:01] */
#define TEST_SERDESID2_DR_100M_SL_MASK                             0x0002
#define TEST_SERDESID2_DR_100M_SL_ALIGN                            0
#define TEST_SERDESID2_DR_100M_SL_BITS                             1
#define TEST_SERDESID2_DR_100M_SL_SHIFT                            1

/* Test :: serdesID2 :: dr_10M_SL [00:00] */
#define TEST_SERDESID2_DR_10M_SL_MASK                              0x0001
#define TEST_SERDESID2_DR_10M_SL_ALIGN                             0
#define TEST_SERDESID2_DR_10M_SL_BITS                              1
#define TEST_SERDESID2_DR_10M_SL_SHIFT                             0


/****************************************************************************
 * Test :: serdesID3
 ***************************************************************************/
/* Test :: serdesID3 :: reserved0 [15:05] */
#define TEST_SERDESID3_RESERVED0_MASK                              0xffe0
#define TEST_SERDESID3_RESERVED0_ALIGN                             0
#define TEST_SERDESID3_RESERVED0_BITS                              11
#define TEST_SERDESID3_RESERVED0_SHIFT                             5

/* Test :: serdesID3 :: dr_6400_SL [04:04] */
#define TEST_SERDESID3_DR_6400_SL_MASK                             0x0010
#define TEST_SERDESID3_DR_6400_SL_ALIGN                            0
#define TEST_SERDESID3_DR_6400_SL_BITS                             1
#define TEST_SERDESID3_DR_6400_SL_SHIFT                            4

/* Test :: serdesID3 :: dr_5000_SL [03:03] */
#define TEST_SERDESID3_DR_5000_SL_MASK                             0x0008
#define TEST_SERDESID3_DR_5000_SL_ALIGN                            0
#define TEST_SERDESID3_DR_5000_SL_BITS                             1
#define TEST_SERDESID3_DR_5000_SL_SHIFT                            3

/* Test :: serdesID3 :: dr_4000_SL [02:02] */
#define TEST_SERDESID3_DR_4000_SL_MASK                             0x0004
#define TEST_SERDESID3_DR_4000_SL_ALIGN                            0
#define TEST_SERDESID3_DR_4000_SL_BITS                             1
#define TEST_SERDESID3_DR_4000_SL_SHIFT                            2

/* Test :: serdesID3 :: dr_2000_SL [01:01] */
#define TEST_SERDESID3_DR_2000_SL_MASK                             0x0002
#define TEST_SERDESID3_DR_2000_SL_ALIGN                            0
#define TEST_SERDESID3_DR_2000_SL_BITS                             1
#define TEST_SERDESID3_DR_2000_SL_SHIFT                            1

/* Test :: serdesID3 :: dr_100FX [00:00] */
#define TEST_SERDESID3_DR_100FX_MASK                               0x0001
#define TEST_SERDESID3_DR_100FX_ALIGN                              0
#define TEST_SERDESID3_DR_100FX_BITS                               1
#define TEST_SERDESID3_DR_100FX_SHIFT                              0


/****************************************************************************
 * Hypercore_USER_Digital3
 ***************************************************************************/
/****************************************************************************
 * Digital3 :: digctl_3_0
 ***************************************************************************/
/* Digital3 :: digctl_3_0 :: an_lostLink_cnt [15:00] */
#define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_MASK                   0xffff
#define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_ALIGN                  0
#define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_BITS                   16
#define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_SHIFT                  0


/****************************************************************************
 * Digital3 :: digctl_3_1
 ***************************************************************************/
/* Digital3 :: digctl_3_1 :: an_switch_cnt [15:00] */
#define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_MASK                     0xffff
#define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_ALIGN                    0
#define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_BITS                     16
#define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_SHIFT                    0


/****************************************************************************
 * Digital3 :: digctl_3_2
 ***************************************************************************/
/* Digital3 :: digctl_3_2 :: an_link_cnt [15:00] */
#define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_MASK                       0xffff
#define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_ALIGN                      0
#define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_BITS                       16
#define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_SHIFT                      0


/****************************************************************************
 * Digital3 :: digctl_3_3
 ***************************************************************************/
/* Digital3 :: digctl_3_3 :: an_switch_cnt2 [15:08] */
#define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_MASK                    0xff00
#define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_ALIGN                   0
#define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_BITS                    8
#define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_SHIFT                   8

/* Digital3 :: digctl_3_3 :: an_link_cnt2 [07:00] */
#define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_MASK                      0x00ff
#define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_ALIGN                     0
#define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_BITS                      8
#define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_SHIFT                     0


/****************************************************************************
 * Digital3 :: digctl_3_4
 ***************************************************************************/
/* Digital3 :: digctl_3_4 :: mp_number [15:05] */
#define DIGITAL3_DIGCTL_3_4_MP_NUMBER_MASK                         0xffe0
#define DIGITAL3_DIGCTL_3_4_MP_NUMBER_ALIGN                        0
#define DIGITAL3_DIGCTL_3_4_MP_NUMBER_BITS                         11
#define DIGITAL3_DIGCTL_3_4_MP_NUMBER_SHIFT                        5

/* Digital3 :: digctl_3_4 :: no_fail_cnt [04:04] */
#define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_MASK                       0x0010
#define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_ALIGN                      0
#define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_BITS                       1
#define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_SHIFT                      4

/* Digital3 :: digctl_3_4 :: an_fail_cnt [03:00] */
#define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_MASK                       0x000f
#define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_ALIGN                      0
#define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_BITS                       4
#define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_SHIFT                      0


/****************************************************************************
 * Digital3 :: digctl_3_5
 ***************************************************************************/
/* Digital3 :: digctl_3_5 :: an_ignoreLink_cnt [15:00] */
#define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_MASK                 0xffff
#define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_ALIGN                0
#define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_BITS                 16
#define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_SHIFT                0


/****************************************************************************
 * Digital3 :: digctl_3_6
 ***************************************************************************/
/* Digital3 :: digctl_3_6 :: an_lostLink_cnt2 [15:08] */
#define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_MASK                  0xff00
#define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_ALIGN                 0
#define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_BITS                  8
#define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_SHIFT                 8

/* Digital3 :: digctl_3_6 :: an_ingoreLink_cnt2 [07:00] */
#define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_MASK                0x00ff
#define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_ALIGN               0
#define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_BITS                8
#define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_SHIFT               0


/****************************************************************************
 * Digital3 :: TPOUT_1
 ***************************************************************************/
/* Digital3 :: TPOUT_1 :: tpout1 [15:00] */
#define DIGITAL3_TPOUT_1_TPOUT1_MASK                               0xffff
#define DIGITAL3_TPOUT_1_TPOUT1_ALIGN                              0
#define DIGITAL3_TPOUT_1_TPOUT1_BITS                               16
#define DIGITAL3_TPOUT_1_TPOUT1_SHIFT                              0


/****************************************************************************
 * Digital3 :: TPOUT_2
 ***************************************************************************/
/* Digital3 :: TPOUT_2 :: tpout2 [15:00] */
#define DIGITAL3_TPOUT_2_TPOUT2_MASK                               0xffff
#define DIGITAL3_TPOUT_2_TPOUT2_ALIGN                              0
#define DIGITAL3_TPOUT_2_TPOUT2_BITS                               16
#define DIGITAL3_TPOUT_2_TPOUT2_SHIFT                              0


/****************************************************************************
 * Digital3 :: UP1
 ***************************************************************************/
/* Digital3 :: UP1 :: reserved0 [15:11] */
#define DIGITAL3_UP1_RESERVED0_MASK                                0xf800
#define DIGITAL3_UP1_RESERVED0_ALIGN                               0
#define DIGITAL3_UP1_RESERVED0_BITS                                5
#define DIGITAL3_UP1_RESERVED0_SHIFT                               11

/* Digital3 :: UP1 :: dataRate_20GX4 [10:10] */
#define DIGITAL3_UP1_DATARATE_20GX4_MASK                           0x0400
#define DIGITAL3_UP1_DATARATE_20GX4_ALIGN                          0
#define DIGITAL3_UP1_DATARATE_20GX4_BITS                           1
#define DIGITAL3_UP1_DATARATE_20GX4_SHIFT                          10

/* Digital3 :: UP1 :: dataRate_16GX4 [09:09] */
#define DIGITAL3_UP1_DATARATE_16GX4_MASK                           0x0200
#define DIGITAL3_UP1_DATARATE_16GX4_ALIGN                          0
#define DIGITAL3_UP1_DATARATE_16GX4_BITS                           1
#define DIGITAL3_UP1_DATARATE_16GX4_SHIFT                          9

/* Digital3 :: UP1 :: dataRate_15GX4 [08:08] */
#define DIGITAL3_UP1_DATARATE_15GX4_MASK                           0x0100
#define DIGITAL3_UP1_DATARATE_15GX4_ALIGN                          0
#define DIGITAL3_UP1_DATARATE_15GX4_BITS                           1
#define DIGITAL3_UP1_DATARATE_15GX4_SHIFT                          8

/* Digital3 :: UP1 :: dataRate_13GX4 [07:07] */
#define DIGITAL3_UP1_DATARATE_13GX4_MASK                           0x0080
#define DIGITAL3_UP1_DATARATE_13GX4_ALIGN                          0
#define DIGITAL3_UP1_DATARATE_13GX4_BITS                           1
#define DIGITAL3_UP1_DATARATE_13GX4_SHIFT                          7

/* Digital3 :: UP1 :: dataRate_12p5GX4 [06:06] */
#define DIGITAL3_UP1_DATARATE_12P5GX4_MASK                         0x0040
#define DIGITAL3_UP1_DATARATE_12P5GX4_ALIGN                        0
#define DIGITAL3_UP1_DATARATE_12P5GX4_BITS                         1
#define DIGITAL3_UP1_DATARATE_12P5GX4_SHIFT                        6

/* Digital3 :: UP1 :: dataRate_12GX4 [05:05] */
#define DIGITAL3_UP1_DATARATE_12GX4_MASK                           0x0020
#define DIGITAL3_UP1_DATARATE_12GX4_ALIGN                          0
#define DIGITAL3_UP1_DATARATE_12GX4_BITS                           1
#define DIGITAL3_UP1_DATARATE_12GX4_SHIFT                          5

/* Digital3 :: UP1 :: dataRate_10GCX4 [04:04] */
#define DIGITAL3_UP1_DATARATE_10GCX4_MASK                          0x0010
#define DIGITAL3_UP1_DATARATE_10GCX4_ALIGN                         0
#define DIGITAL3_UP1_DATARATE_10GCX4_BITS                          1
#define DIGITAL3_UP1_DATARATE_10GCX4_SHIFT                         4

/* Digital3 :: UP1 :: dataRate_10GX4 [03:03] */
#define DIGITAL3_UP1_DATARATE_10GX4_MASK                           0x0008
#define DIGITAL3_UP1_DATARATE_10GX4_ALIGN                          0
#define DIGITAL3_UP1_DATARATE_10GX4_BITS                           1
#define DIGITAL3_UP1_DATARATE_10GX4_SHIFT                          3

/* Digital3 :: UP1 :: dataRate_6GX4 [02:02] */
#define DIGITAL3_UP1_DATARATE_6GX4_MASK                            0x0004
#define DIGITAL3_UP1_DATARATE_6GX4_ALIGN                           0
#define DIGITAL3_UP1_DATARATE_6GX4_BITS                            1
#define DIGITAL3_UP1_DATARATE_6GX4_SHIFT                           2

/* Digital3 :: UP1 :: dataRate_5GX4 [01:01] */
#define DIGITAL3_UP1_DATARATE_5GX4_MASK                            0x0002
#define DIGITAL3_UP1_DATARATE_5GX4_ALIGN                           0
#define DIGITAL3_UP1_DATARATE_5GX4_BITS                            1
#define DIGITAL3_UP1_DATARATE_5GX4_SHIFT                           1

/* Digital3 :: UP1 :: dataRate_2p5GX1 [00:00] */
#define DIGITAL3_UP1_DATARATE_2P5GX1_MASK                          0x0001
#define DIGITAL3_UP1_DATARATE_2P5GX1_ALIGN                         0
#define DIGITAL3_UP1_DATARATE_2P5GX1_BITS                          1
#define DIGITAL3_UP1_DATARATE_2P5GX1_SHIFT                         0


/****************************************************************************
 * Digital3 :: UP2
 ***************************************************************************/
/* Digital3 :: UP2 :: reserved0 [15:11] */
#define DIGITAL3_UP2_RESERVED0_MASK                                0xf800
#define DIGITAL3_UP2_RESERVED0_ALIGN                               0
#define DIGITAL3_UP2_RESERVED0_BITS                                5
#define DIGITAL3_UP2_RESERVED0_SHIFT                               11

/* Digital3 :: UP2 :: valid [10:10] */
#define DIGITAL3_UP2_VALID_MASK                                    0x0400
#define DIGITAL3_UP2_VALID_ALIGN                                   0
#define DIGITAL3_UP2_VALID_BITS                                    1
#define DIGITAL3_UP2_VALID_SHIFT                                   10

/* Digital3 :: UP2 :: preemphasis [09:06] */
#define DIGITAL3_UP2_PREEMPHASIS_MASK                              0x03c0
#define DIGITAL3_UP2_PREEMPHASIS_ALIGN                             0
#define DIGITAL3_UP2_PREEMPHASIS_BITS                              4
#define DIGITAL3_UP2_PREEMPHASIS_SHIFT                             6

/* Digital3 :: UP2 :: idriver [05:03] */
#define DIGITAL3_UP2_IDRIVER_MASK                                  0x0038
#define DIGITAL3_UP2_IDRIVER_ALIGN                                 0
#define DIGITAL3_UP2_IDRIVER_BITS                                  3
#define DIGITAL3_UP2_IDRIVER_SHIFT                                 3

/* Digital3 :: UP2 :: ipredriver [02:00] */
#define DIGITAL3_UP2_IPREDRIVER_MASK                               0x0007
#define DIGITAL3_UP2_IPREDRIVER_ALIGN                              0
#define DIGITAL3_UP2_IPREDRIVER_BITS                               3
#define DIGITAL3_UP2_IPREDRIVER_SHIFT                              0


/****************************************************************************
 * Digital3 :: UP3
 ***************************************************************************/
/* Digital3 :: UP3 :: reserved0 [15:11] */
#define DIGITAL3_UP3_RESERVED0_MASK                                0xf800
#define DIGITAL3_UP3_RESERVED0_ALIGN                               0
#define DIGITAL3_UP3_RESERVED0_BITS                                5
#define DIGITAL3_UP3_RESERVED0_SHIFT                               11

/* Digital3 :: UP3 :: last [10:10] */
#define DIGITAL3_UP3_LAST_MASK                                     0x0400
#define DIGITAL3_UP3_LAST_ALIGN                                    0
#define DIGITAL3_UP3_LAST_BITS                                     1
#define DIGITAL3_UP3_LAST_SHIFT                                    10

/* Digital3 :: UP3 :: dataRate_21GX4 [09:09] */
#define DIGITAL3_UP3_DATARATE_21GX4_MASK                           0x0200
#define DIGITAL3_UP3_DATARATE_21GX4_ALIGN                          0
#define DIGITAL3_UP3_DATARATE_21GX4_BITS                           1
#define DIGITAL3_UP3_DATARATE_21GX4_SHIFT                          9

/* Digital3 :: UP3 :: dataRate_25p45GX4 [08:08] */
#define DIGITAL3_UP3_DATARATE_25P45GX4_MASK                        0x0100
#define DIGITAL3_UP3_DATARATE_25P45GX4_ALIGN                       0
#define DIGITAL3_UP3_DATARATE_25P45GX4_BITS                        1
#define DIGITAL3_UP3_DATARATE_25P45GX4_SHIFT                       8

/* Digital3 :: UP3 :: reserved1 [07:02] */
#define DIGITAL3_UP3_RESERVED1_MASK                                0x00fc
#define DIGITAL3_UP3_RESERVED1_ALIGN                               0
#define DIGITAL3_UP3_RESERVED1_BITS                                6
#define DIGITAL3_UP3_RESERVED1_SHIFT                               2

/* Digital3 :: UP3 :: scramble_8B10B [01:01] */
#define DIGITAL3_UP3_SCRAMBLE_8B10B_MASK                           0x0002
#define DIGITAL3_UP3_SCRAMBLE_8B10B_ALIGN                          0
#define DIGITAL3_UP3_SCRAMBLE_8B10B_BITS                           1
#define DIGITAL3_UP3_SCRAMBLE_8B10B_SHIFT                          1

/* Digital3 :: UP3 :: HiGig2 [00:00] */
#define DIGITAL3_UP3_HIGIG2_MASK                                   0x0001
#define DIGITAL3_UP3_HIGIG2_ALIGN                                  0
#define DIGITAL3_UP3_HIGIG2_BITS                                   1
#define DIGITAL3_UP3_HIGIG2_SHIFT                                  0


/****************************************************************************
 * Digital3 :: LP_UP1
 ***************************************************************************/
/* Digital3 :: LP_UP1 :: reserved0 [15:11] */
#define DIGITAL3_LP_UP1_RESERVED0_MASK                             0xf800
#define DIGITAL3_LP_UP1_RESERVED0_ALIGN                            0
#define DIGITAL3_LP_UP1_RESERVED0_BITS                             5
#define DIGITAL3_LP_UP1_RESERVED0_SHIFT                            11

/* Digital3 :: LP_UP1 :: dataRate_20GX4 [10:10] */
#define DIGITAL3_LP_UP1_DATARATE_20GX4_MASK                        0x0400
#define DIGITAL3_LP_UP1_DATARATE_20GX4_ALIGN                       0
#define DIGITAL3_LP_UP1_DATARATE_20GX4_BITS                        1
#define DIGITAL3_LP_UP1_DATARATE_20GX4_SHIFT                       10

/* Digital3 :: LP_UP1 :: dataRate_16GX4 [09:09] */
#define DIGITAL3_LP_UP1_DATARATE_16GX4_MASK                        0x0200
#define DIGITAL3_LP_UP1_DATARATE_16GX4_ALIGN                       0
#define DIGITAL3_LP_UP1_DATARATE_16GX4_BITS                        1
#define DIGITAL3_LP_UP1_DATARATE_16GX4_SHIFT                       9

/* Digital3 :: LP_UP1 :: dataRate_15GX4 [08:08] */
#define DIGITAL3_LP_UP1_DATARATE_15GX4_MASK                        0x0100
#define DIGITAL3_LP_UP1_DATARATE_15GX4_ALIGN                       0
#define DIGITAL3_LP_UP1_DATARATE_15GX4_BITS                        1
#define DIGITAL3_LP_UP1_DATARATE_15GX4_SHIFT                       8

/* Digital3 :: LP_UP1 :: dataRate_13GX4 [07:07] */
#define DIGITAL3_LP_UP1_DATARATE_13GX4_MASK                        0x0080
#define DIGITAL3_LP_UP1_DATARATE_13GX4_ALIGN                       0
#define DIGITAL3_LP_UP1_DATARATE_13GX4_BITS                        1
#define DIGITAL3_LP_UP1_DATARATE_13GX4_SHIFT                       7

/* Digital3 :: LP_UP1 :: dataRate_12p5GX4 [06:06] */
#define DIGITAL3_LP_UP1_DATARATE_12P5GX4_MASK                      0x0040
#define DIGITAL3_LP_UP1_DATARATE_12P5GX4_ALIGN                     0
#define DIGITAL3_LP_UP1_DATARATE_12P5GX4_BITS                      1
#define DIGITAL3_LP_UP1_DATARATE_12P5GX4_SHIFT                     6

/* Digital3 :: LP_UP1 :: dataRate_12GX4 [05:05] */
#define DIGITAL3_LP_UP1_DATARATE_12GX4_MASK                        0x0020
#define DIGITAL3_LP_UP1_DATARATE_12GX4_ALIGN                       0
#define DIGITAL3_LP_UP1_DATARATE_12GX4_BITS                        1
#define DIGITAL3_LP_UP1_DATARATE_12GX4_SHIFT                       5

/* Digital3 :: LP_UP1 :: dataRate_10GCX4 [04:04] */
#define DIGITAL3_LP_UP1_DATARATE_10GCX4_MASK                       0x0010
#define DIGITAL3_LP_UP1_DATARATE_10GCX4_ALIGN                      0
#define DIGITAL3_LP_UP1_DATARATE_10GCX4_BITS                       1
#define DIGITAL3_LP_UP1_DATARATE_10GCX4_SHIFT                      4

/* Digital3 :: LP_UP1 :: dataRate_10GX4 [03:03] */
#define DIGITAL3_LP_UP1_DATARATE_10GX4_MASK                        0x0008
#define DIGITAL3_LP_UP1_DATARATE_10GX4_ALIGN                       0
#define DIGITAL3_LP_UP1_DATARATE_10GX4_BITS                        1
#define DIGITAL3_LP_UP1_DATARATE_10GX4_SHIFT                       3

/* Digital3 :: LP_UP1 :: dataRate_6GX4 [02:02] */
#define DIGITAL3_LP_UP1_DATARATE_6GX4_MASK                         0x0004
#define DIGITAL3_LP_UP1_DATARATE_6GX4_ALIGN                        0
#define DIGITAL3_LP_UP1_DATARATE_6GX4_BITS                         1
#define DIGITAL3_LP_UP1_DATARATE_6GX4_SHIFT                        2

/* Digital3 :: LP_UP1 :: dataRate_5GX4 [01:01] */
#define DIGITAL3_LP_UP1_DATARATE_5GX4_MASK                         0x0002
#define DIGITAL3_LP_UP1_DATARATE_5GX4_ALIGN                        0
#define DIGITAL3_LP_UP1_DATARATE_5GX4_BITS                         1
#define DIGITAL3_LP_UP1_DATARATE_5GX4_SHIFT                        1

/* Digital3 :: LP_UP1 :: dataRate_2p5GX1 [00:00] */
#define DIGITAL3_LP_UP1_DATARATE_2P5GX1_MASK                       0x0001
#define DIGITAL3_LP_UP1_DATARATE_2P5GX1_ALIGN                      0
#define DIGITAL3_LP_UP1_DATARATE_2P5GX1_BITS                       1
#define DIGITAL3_LP_UP1_DATARATE_2P5GX1_SHIFT                      0


/****************************************************************************
 * Digital3 :: LP_UP2
 ***************************************************************************/
/* Digital3 :: LP_UP2 :: reserved0 [15:11] */
#define DIGITAL3_LP_UP2_RESERVED0_MASK                             0xf800
#define DIGITAL3_LP_UP2_RESERVED0_ALIGN                            0
#define DIGITAL3_LP_UP2_RESERVED0_BITS                             5
#define DIGITAL3_LP_UP2_RESERVED0_SHIFT                            11

/* Digital3 :: LP_UP2 :: valid [10:10] */
#define DIGITAL3_LP_UP2_VALID_MASK                                 0x0400
#define DIGITAL3_LP_UP2_VALID_ALIGN                                0
#define DIGITAL3_LP_UP2_VALID_BITS                                 1
#define DIGITAL3_LP_UP2_VALID_SHIFT                                10

/* Digital3 :: LP_UP2 :: preemphasis [09:06] */
#define DIGITAL3_LP_UP2_PREEMPHASIS_MASK                           0x03c0
#define DIGITAL3_LP_UP2_PREEMPHASIS_ALIGN                          0
#define DIGITAL3_LP_UP2_PREEMPHASIS_BITS                           4
#define DIGITAL3_LP_UP2_PREEMPHASIS_SHIFT                          6

/* Digital3 :: LP_UP2 :: idriver [05:03] */
#define DIGITAL3_LP_UP2_IDRIVER_MASK                               0x0038
#define DIGITAL3_LP_UP2_IDRIVER_ALIGN                              0
#define DIGITAL3_LP_UP2_IDRIVER_BITS                               3
#define DIGITAL3_LP_UP2_IDRIVER_SHIFT                              3

/* Digital3 :: LP_UP2 :: ipredriver [02:00] */
#define DIGITAL3_LP_UP2_IPREDRIVER_MASK                            0x0007
#define DIGITAL3_LP_UP2_IPREDRIVER_ALIGN                           0
#define DIGITAL3_LP_UP2_IPREDRIVER_BITS                            3
#define DIGITAL3_LP_UP2_IPREDRIVER_SHIFT                           0


/****************************************************************************
 * Digital3 :: LP_UP3
 ***************************************************************************/
/* Digital3 :: LP_UP3 :: reserved0 [15:11] */
#define DIGITAL3_LP_UP3_RESERVED0_MASK                             0xf800
#define DIGITAL3_LP_UP3_RESERVED0_ALIGN                            0
#define DIGITAL3_LP_UP3_RESERVED0_BITS                             5
#define DIGITAL3_LP_UP3_RESERVED0_SHIFT                            11

/* Digital3 :: LP_UP3 :: last [10:10] */
#define DIGITAL3_LP_UP3_LAST_MASK                                  0x0400
#define DIGITAL3_LP_UP3_LAST_ALIGN                                 0
#define DIGITAL3_LP_UP3_LAST_BITS                                  1
#define DIGITAL3_LP_UP3_LAST_SHIFT                                 10

/* Digital3 :: LP_UP3 :: dataRate_21GX4 [09:09] */
#define DIGITAL3_LP_UP3_DATARATE_21GX4_MASK                        0x0200
#define DIGITAL3_LP_UP3_DATARATE_21GX4_ALIGN                       0
#define DIGITAL3_LP_UP3_DATARATE_21GX4_BITS                        1
#define DIGITAL3_LP_UP3_DATARATE_21GX4_SHIFT                       9

/* Digital3 :: LP_UP3 :: dataRate_25p45GX4 [08:08] */
#define DIGITAL3_LP_UP3_DATARATE_25P45GX4_MASK                     0x0100
#define DIGITAL3_LP_UP3_DATARATE_25P45GX4_ALIGN                    0
#define DIGITAL3_LP_UP3_DATARATE_25P45GX4_BITS                     1
#define DIGITAL3_LP_UP3_DATARATE_25P45GX4_SHIFT                    8

/* Digital3 :: LP_UP3 :: reserved1 [07:02] */
#define DIGITAL3_LP_UP3_RESERVED1_MASK                             0x00fc
#define DIGITAL3_LP_UP3_RESERVED1_ALIGN                            0
#define DIGITAL3_LP_UP3_RESERVED1_BITS                             6
#define DIGITAL3_LP_UP3_RESERVED1_SHIFT                            2

/* Digital3 :: LP_UP3 :: scramble_8B10B [01:01] */
#define DIGITAL3_LP_UP3_SCRAMBLE_8B10B_MASK                        0x0002
#define DIGITAL3_LP_UP3_SCRAMBLE_8B10B_ALIGN                       0
#define DIGITAL3_LP_UP3_SCRAMBLE_8B10B_BITS                        1
#define DIGITAL3_LP_UP3_SCRAMBLE_8B10B_SHIFT                       1

/* Digital3 :: LP_UP3 :: HiGig2 [00:00] */
#define DIGITAL3_LP_UP3_HIGIG2_MASK                                0x0001
#define DIGITAL3_LP_UP3_HIGIG2_ALIGN                               0
#define DIGITAL3_LP_UP3_HIGIG2_BITS                                1
#define DIGITAL3_LP_UP3_HIGIG2_SHIFT                               0


/****************************************************************************
 * Hypercore_USER_Digital4
 ***************************************************************************/
/****************************************************************************
 * Digital4 :: MiscRxStatus
 ***************************************************************************/
/* union - case statusSelect0 [15:00] */
/* Digital4 :: MiscRxStatus :: capture_NP_lh [15:15] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_MASK     0x8000
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_ALIGN    0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_BITS     1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_SHIFT    15

/* Digital4 :: MiscRxStatus :: teton_brk_link_lh [14:14] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_MASK 0x4000
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_ALIGN 0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_BITS 1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_SHIFT 14

/* Digital4 :: MiscRxStatus :: UP3_lh [13:13] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_MASK            0x2000
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_ALIGN           0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_BITS            1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_SHIFT           13

/* Digital4 :: MiscRxStatus :: MP5_lh [12:12] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_MASK            0x1000
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_ALIGN           0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_BITS            1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_SHIFT           12

/* Digital4 :: MiscRxStatus :: nonMatchingOUI_lh [11:11] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_MASK 0x0800
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_ALIGN 0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_BITS 1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_SHIFT 11

/* Digital4 :: MiscRxStatus :: matchingOUI_msb_lh [10:10] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_MASK 0x0400
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_ALIGN 0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_BITS 1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_SHIFT 10

/* Digital4 :: MiscRxStatus :: matchingOUI_lsb_lh [09:09] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_MASK 0x0200
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_ALIGN 0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_BITS 1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_SHIFT 9

/* Digital4 :: MiscRxStatus :: invalidSeq_lh [08:08] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_MASK     0x0100
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_ALIGN    0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_BITS     1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_SHIFT    8

/* Digital4 :: MiscRxStatus :: nullMP_lh [07:07] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_MASK         0x0080
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_ALIGN        0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_BITS         1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_SHIFT        7

/* Digital4 :: MiscRxStatus :: remotePhyMP_lh [06:06] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_MASK    0x0040
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_ALIGN   0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_BITS    1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_SHIFT   6

/* Digital4 :: MiscRxStatus :: nonMatchingMP_lh [05:05] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_MASK  0x0020
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_ALIGN 0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_BITS  1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_SHIFT 5

/* Digital4 :: MiscRxStatus :: over1gMP_lh [04:04] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_MASK       0x0010
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_ALIGN      0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_BITS       1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_SHIFT      4

/* Digital4 :: MiscRxStatus :: rx_config_is_0_lh [03:03] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_MASK 0x0008
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_ALIGN 0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_BITS 1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_SHIFT 3

/* Digital4 :: MiscRxStatus :: np_toggle_err_lh [02:02] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_MASK  0x0004
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_ALIGN 0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_BITS  1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_SHIFT 2

/* Digital4 :: MiscRxStatus :: mr_np_lh [01:01] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_MASK          0x0002
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_ALIGN         0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_BITS          1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_SHIFT         1

/* Digital4 :: MiscRxStatus :: mr_bp_lh [00:00] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_MASK          0x0001
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_ALIGN         0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_BITS          1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_SHIFT         0


/* union - case statusSelect1 [15:00] */
/* Digital4 :: MiscRxStatus :: reserved0 [15:04] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_MASK         0xfff0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_ALIGN        0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_BITS         12
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_SHIFT        4

/* Digital4 :: MiscRxStatus :: np_count [03:00] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_MASK          0x000f
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_ALIGN         0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_BITS          4
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_SHIFT         0


/* union - case statusSelect2 [15:00] */
/* Digital4 :: MiscRxStatus :: reserved0 [15:06] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_MASK         0xffc0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_ALIGN        0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_BITS         10
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_SHIFT        6

/* Digital4 :: MiscRxStatus :: remote_phy_enable [05:05] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_MASK 0x0020
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_ALIGN 0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_BITS 1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_SHIFT 5

/* Digital4 :: MiscRxStatus :: det_teton_mode [04:04] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_MASK    0x0010
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_ALIGN   0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_BITS    1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_SHIFT   4

/* Digital4 :: MiscRxStatus :: cu_linkdown [03:03] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_MASK       0x0008
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_ALIGN      0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_BITS       1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_SHIFT      3

/* Digital4 :: MiscRxStatus :: cu_resolution_error [02:02] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_MASK 0x0004
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_ALIGN 0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_BITS 1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_SHIFT 2

/* Digital4 :: MiscRxStatus :: remotePhy_autosel [01:01] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_MASK 0x0002
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_ALIGN 0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_BITS 1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_SHIFT 1

/* Digital4 :: MiscRxStatus :: rx_config_isNot_0_lh [00:00] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_MASK 0x0001
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_ALIGN 0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_BITS 1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_SHIFT 0


/* union - case statusSelect3 [15:00] */
/* Digital4 :: MiscRxStatus :: reserved0 [15:06] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_MASK         0xffc0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_ALIGN        0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_BITS         10
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_SHIFT        6

/* Digital4 :: MiscRxStatus :: sgmii_selector_mismatch [05:05] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_MASK 0x0020
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_ALIGN 0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_BITS 1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_SHIFT 5

/* Digital4 :: MiscRxStatus :: autoneg_enable_ov [04:04] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_MASK 0x0010
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_ALIGN 0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_BITS 1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_SHIFT 4

/* Digital4 :: MiscRxStatus :: s_mr_an_enable [03:03] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_MASK    0x0008
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_ALIGN   0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_BITS    1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_SHIFT   3

/* Digital4 :: MiscRxStatus :: s_cl73_rslv_KX4 [02:02] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_MASK   0x0004
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_ALIGN  0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_BITS   1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_SHIFT  2

/* Digital4 :: MiscRxStatus :: s_cl73_rslv_KX [01:01] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_MASK    0x0002
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_ALIGN   0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_BITS    1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_SHIFT   1

/* Digital4 :: MiscRxStatus :: KX_detect [00:00] */
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_MASK         0x0001
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_ALIGN        0
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_BITS         1
#define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_SHIFT        0



/****************************************************************************
 * Digital4 :: lp_basePage
 ***************************************************************************/
/* Digital4 :: lp_basePage :: lp_basePage [15:00] */
#define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_MASK                      0xffff
#define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_ALIGN                     0
#define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_BITS                      16
#define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_SHIFT                     0


/****************************************************************************
 * Digital4 :: lp_nextPage_0
 ***************************************************************************/
/* Digital4 :: lp_nextPage_0 :: lp_nextPage_0 [15:00] */
#define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_MASK                  0xffff
#define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_ALIGN                 0
#define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_BITS                  16
#define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_SHIFT                 0


/****************************************************************************
 * Digital4 :: lp_nextPage_1
 ***************************************************************************/
/* Digital4 :: lp_nextPage_1 :: lp_nextPage_1 [15:00] */
#define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_MASK                  0xffff
#define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_ALIGN                 0
#define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_BITS                  16
#define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_SHIFT                 0


/****************************************************************************
 * Digital4 :: lp_nextPage_2
 ***************************************************************************/
/* Digital4 :: lp_nextPage_2 :: lp_nextPage_2 [15:00] */
#define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_MASK                  0xffff
#define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_ALIGN                 0
#define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_BITS                  16
#define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_SHIFT                 0


/****************************************************************************
 * Digital4 :: lp_nextPage_3
 ***************************************************************************/
/* Digital4 :: lp_nextPage_3 :: lp_nextPage_3 [15:00] */
#define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_MASK                  0xffff
#define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_ALIGN                 0
#define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_BITS                  16
#define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_SHIFT                 0


/****************************************************************************
 * Digital4 :: lp_nextPage_4
 ***************************************************************************/
/* Digital4 :: lp_nextPage_4 :: lp_nextPage_4 [15:00] */
#define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_MASK                  0xffff
#define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_ALIGN                 0
#define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_BITS                  16
#define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_SHIFT                 0


/****************************************************************************
 * Digital4 :: rp_nextPage_0
 ***************************************************************************/
/* Digital4 :: rp_nextPage_0 :: reserved0 [15:15] */
#define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_MASK                      0x8000
#define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_ALIGN                     0
#define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_BITS                      1
#define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_SHIFT                     15

/* Digital4 :: rp_nextPage_0 :: extra_page_disable [14:14] */
#define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_MASK             0x4000
#define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_ALIGN            0
#define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_BITS             1
#define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_SHIFT            14

/* Digital4 :: rp_nextPage_0 :: null_page_enable [13:13] */
#define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_MASK               0x2000
#define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_ALIGN              0
#define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_BITS               1
#define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_SHIFT              13

/* Digital4 :: rp_nextPage_0 :: over_1g_disable [12:12] */
#define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_MASK                0x1000
#define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_ALIGN               0
#define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_BITS                1
#define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_SHIFT               12

/* Digital4 :: rp_nextPage_0 :: remote_phy_enable [11:11] */
#define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_MASK              0x0800
#define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_ALIGN             0
#define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_BITS              1
#define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_SHIFT             11

/* Digital4 :: rp_nextPage_0 :: rp_nextPage_0 [10:00] */
#define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_MASK                  0x07ff
#define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_ALIGN                 0
#define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_BITS                  11
#define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_SHIFT                 0


/****************************************************************************
 * Digital4 :: rp_nextPage_1
 ***************************************************************************/
/* Digital4 :: rp_nextPage_1 :: reserved0 [15:15] */
#define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_MASK                      0x8000
#define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_ALIGN                     0
#define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_BITS                      1
#define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_SHIFT                     15

/* Digital4 :: rp_nextPage_1 :: remotePhy_linkDown_rstrt_disable [14:14] */
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_MASK 0x4000
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_ALIGN 0
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_BITS 1
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_SHIFT 14

/* Digital4 :: rp_nextPage_1 :: remotePhy_rsltn_err_rstrt_disable [13:13] */
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_MASK 0x2000
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_ALIGN 0
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_BITS 1
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_SHIFT 13

/* Digital4 :: rp_nextPage_1 :: remotePhy_resolution_disable [12:12] */
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_MASK   0x1000
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_ALIGN  0
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_BITS   1
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_SHIFT  12

/* Digital4 :: rp_nextPage_1 :: remotePhy_decode_enable [11:11] */
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_MASK        0x0800
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_ALIGN       0
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_BITS        1
#define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_SHIFT       11

/* Digital4 :: rp_nextPage_1 :: rp_nextPage_1 [10:00] */
#define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_MASK                  0x07ff
#define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_ALIGN                 0
#define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_BITS                  11
#define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_SHIFT                 0


/****************************************************************************
 * Digital4 :: rp_nextPage_2
 ***************************************************************************/
/* Digital4 :: rp_nextPage_2 :: reserved0 [15:12] */
#define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_MASK                      0xf000
#define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_ALIGN                     0
#define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_BITS                      4
#define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_SHIFT                     12

/* Digital4 :: rp_nextPage_2 :: remPhy_NP_clr_disable [11:11] */
#define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_MASK          0x0800
#define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_ALIGN         0
#define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_BITS          1
#define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_SHIFT         11

/* Digital4 :: rp_nextPage_2 :: rp_nextPage_2 [10:00] */
#define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_MASK                  0x07ff
#define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_ALIGN                 0
#define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_BITS                  11
#define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_SHIFT                 0


/****************************************************************************
 * Digital4 :: rp_nextPage_3
 ***************************************************************************/
/* Digital4 :: rp_nextPage_3 :: reserved0 [15:11] */
#define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_MASK                      0xf800
#define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_ALIGN                     0
#define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_BITS                      5
#define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_SHIFT                     11

/* Digital4 :: rp_nextPage_3 :: rp_nextPage_3 [10:00] */
#define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_MASK                  0x07ff
#define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_ALIGN                 0
#define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_BITS                  11
#define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_SHIFT                 0


/****************************************************************************
 * Digital4 :: rp_nextPage_4
 ***************************************************************************/
/* Digital4 :: rp_nextPage_4 :: reserved0 [15:11] */
#define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_MASK                      0xf800
#define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_ALIGN                     0
#define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_BITS                      5
#define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_SHIFT                     11

/* Digital4 :: rp_nextPage_4 :: rp_nextPage_4 [10:00] */
#define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_MASK                  0x07ff
#define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_ALIGN                 0
#define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_BITS                  11
#define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_SHIFT                 0


/****************************************************************************
 * Digital4 :: Misc3
 ***************************************************************************/
/* Digital4 :: Misc3 :: reserved0 [15:12] */
#define DIGITAL4_MISC3_RESERVED0_MASK                              0xf000
#define DIGITAL4_MISC3_RESERVED0_ALIGN                             0
#define DIGITAL4_MISC3_RESERVED0_BITS                              4
#define DIGITAL4_MISC3_RESERVED0_SHIFT                             12

/* Digital4 :: Misc3 :: rxck_mii_override_val [11:11] */
#define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_MASK                  0x0800
#define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_ALIGN                 0
#define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_BITS                  1
#define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_SHIFT                 11

/* Digital4 :: Misc3 :: rxck_mii_override [10:10] */
#define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_MASK                      0x0400
#define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_ALIGN                     0
#define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_BITS                      1
#define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_SHIFT                     10

/* Digital4 :: Misc3 :: fifo_ipg_cya [09:09] */
#define DIGITAL4_MISC3_FIFO_IPG_CYA_MASK                           0x0200
#define DIGITAL4_MISC3_FIFO_IPG_CYA_ALIGN                          0
#define DIGITAL4_MISC3_FIFO_IPG_CYA_BITS                           1
#define DIGITAL4_MISC3_FIFO_IPG_CYA_SHIFT                          9

/* Digital4 :: Misc3 :: scr_en_per_lane [08:08] */
#define DIGITAL4_MISC3_SCR_EN_PER_LANE_MASK                        0x0100
#define DIGITAL4_MISC3_SCR_EN_PER_LANE_ALIGN                       0
#define DIGITAL4_MISC3_SCR_EN_PER_LANE_BITS                        1
#define DIGITAL4_MISC3_SCR_EN_PER_LANE_SHIFT                       8

/* Digital4 :: Misc3 :: force_speed_b5 [07:07] */
#define DIGITAL4_MISC3_FORCE_SPEED_B5_MASK                         0x0080
#define DIGITAL4_MISC3_FORCE_SPEED_B5_ALIGN                        0
#define DIGITAL4_MISC3_FORCE_SPEED_B5_BITS                         1
#define DIGITAL4_MISC3_FORCE_SPEED_B5_SHIFT                        7

/* Digital4 :: Misc3 :: laneDisable [06:06] */
#define DIGITAL4_MISC3_LANEDISABLE_MASK                            0x0040
#define DIGITAL4_MISC3_LANEDISABLE_ALIGN                           0
#define DIGITAL4_MISC3_LANEDISABLE_BITS                            1
#define DIGITAL4_MISC3_LANEDISABLE_SHIFT                           6

/* Digital4 :: Misc3 :: fifo_err_cya2 [05:05] */
#define DIGITAL4_MISC3_FIFO_ERR_CYA2_MASK                          0x0020
#define DIGITAL4_MISC3_FIFO_ERR_CYA2_ALIGN                         0
#define DIGITAL4_MISC3_FIFO_ERR_CYA2_BITS                          1
#define DIGITAL4_MISC3_FIFO_ERR_CYA2_SHIFT                         5

/* Digital4 :: Misc3 :: disable_pcs_tx_r [04:04] */
#define DIGITAL4_MISC3_DISABLE_PCS_TX_R_MASK                       0x0010
#define DIGITAL4_MISC3_DISABLE_PCS_TX_R_ALIGN                      0
#define DIGITAL4_MISC3_DISABLE_PCS_TX_R_BITS                       1
#define DIGITAL4_MISC3_DISABLE_PCS_TX_R_SHIFT                      4

/* Digital4 :: Misc3 :: disable_pcs_tx_force_r [03:03] */
#define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_MASK                 0x0008
#define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_ALIGN                0
#define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_BITS                 1
#define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_SHIFT                3

/* Digital4 :: Misc3 :: tbi_mode_force_r [02:02] */
#define DIGITAL4_MISC3_TBI_MODE_FORCE_R_MASK                       0x0004
#define DIGITAL4_MISC3_TBI_MODE_FORCE_R_ALIGN                      0
#define DIGITAL4_MISC3_TBI_MODE_FORCE_R_BITS                       1
#define DIGITAL4_MISC3_TBI_MODE_FORCE_R_SHIFT                      2

/* Digital4 :: Misc3 :: rxSigdetPwrdn_override_val [01:01] */
#define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_MASK             0x0002
#define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_ALIGN            0
#define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_BITS             1
#define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_SHIFT            1

/* Digital4 :: Misc3 :: rxSigdetPwrdn_override [00:00] */
#define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_MASK                 0x0001
#define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_ALIGN                0
#define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_BITS                 1
#define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_SHIFT                0


/****************************************************************************
 * Hypercore_USER_Digital6
 ***************************************************************************/
/****************************************************************************
 * Digital6 :: mp5_NextPageCtrl
 ***************************************************************************/
/* Digital6 :: mp5_NextPageCtrl :: reserved0 [15:04] */
#define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_MASK                   0xfff0
#define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_ALIGN                  0
#define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_BITS                   12
#define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_SHIFT                  4

/* Digital6 :: mp5_NextPageCtrl :: np_sw_overRide_en [03:03] */
#define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_MASK           0x0008
#define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_ALIGN          0
#define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_BITS           1
#define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_SHIFT          3

/* Digital6 :: mp5_NextPageCtrl :: teton_mode_up3_en [02:02] */
#define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_MASK           0x0004
#define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_ALIGN          0
#define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_BITS           1
#define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_SHIFT          2

/* Digital6 :: mp5_NextPageCtrl :: teton_mode [01:01] */
#define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_MASK                  0x0002
#define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_ALIGN                 0
#define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_BITS                  1
#define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_SHIFT                 1

/* Digital6 :: mp5_NextPageCtrl :: bam_mode [00:00] */
#define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_MASK                    0x0001
#define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_ALIGN                   0
#define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_BITS                    1
#define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_SHIFT                   0


/****************************************************************************
 * Digital6 :: link_timer_offset1
 ***************************************************************************/
/* Digital6 :: link_timer_offset1 :: sgmii_offset [15:08] */
#define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_MASK              0xff00
#define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_ALIGN             0
#define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_BITS              8
#define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_SHIFT             8

/* Digital6 :: link_timer_offset1 :: max_offset [07:00] */
#define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_MASK                0x00ff
#define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_ALIGN               0
#define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_BITS                8
#define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_SHIFT               0


/****************************************************************************
 * Digital6 :: link_timer_offset2
 ***************************************************************************/
/* Digital6 :: link_timer_offset2 :: link_up_offset [15:08] */
#define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_MASK            0xff00
#define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_ALIGN           0
#define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_BITS            8
#define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_SHIFT           8

/* Digital6 :: link_timer_offset2 :: link_down_offset [07:00] */
#define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_MASK          0x00ff
#define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_ALIGN         0
#define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_BITS          8
#define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_SHIFT         0


/****************************************************************************
 * Digital6 :: link_timer_offset3
 ***************************************************************************/
/* Digital6 :: link_timer_offset3 :: break_link_offset [15:08] */
#define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_MASK         0xff00
#define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_ALIGN        0
#define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_BITS         8
#define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_SHIFT        8

/* Digital6 :: link_timer_offset3 :: np_link_offset [07:00] */
#define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_MASK            0x00ff
#define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_ALIGN           0
#define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_BITS            8
#define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_SHIFT           0


/****************************************************************************
 * Digital6 :: oui_msb_field
 ***************************************************************************/
/* Digital6 :: oui_msb_field :: reserved0 [15:11] */
#define DIGITAL6_OUI_MSB_FIELD_RESERVED0_MASK                      0xf800
#define DIGITAL6_OUI_MSB_FIELD_RESERVED0_ALIGN                     0
#define DIGITAL6_OUI_MSB_FIELD_RESERVED0_BITS                      5
#define DIGITAL6_OUI_MSB_FIELD_RESERVED0_SHIFT                     11

/* Digital6 :: oui_msb_field :: oui_msb_field [10:00] */
#define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_MASK                  0x07ff
#define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_ALIGN                 0
#define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_BITS                  11
#define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_SHIFT                 0


/****************************************************************************
 * Digital6 :: oui_lsb_field
 ***************************************************************************/
/* Digital6 :: oui_lsb_field :: reserved0 [15:11] */
#define DIGITAL6_OUI_LSB_FIELD_RESERVED0_MASK                      0xf800
#define DIGITAL6_OUI_LSB_FIELD_RESERVED0_ALIGN                     0
#define DIGITAL6_OUI_LSB_FIELD_RESERVED0_BITS                      5
#define DIGITAL6_OUI_LSB_FIELD_RESERVED0_SHIFT                     11

/* Digital6 :: oui_lsb_field :: oui_lsb_field [10:00] */
#define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_MASK                  0x07ff
#define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_ALIGN                 0
#define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_BITS                  11
#define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_SHIFT                 0


/****************************************************************************
 * Digital6 :: bam_field
 ***************************************************************************/
/* Digital6 :: bam_field :: reserved0 [15:11] */
#define DIGITAL6_BAM_FIELD_RESERVED0_MASK                          0xf800
#define DIGITAL6_BAM_FIELD_RESERVED0_ALIGN                         0
#define DIGITAL6_BAM_FIELD_RESERVED0_BITS                          5
#define DIGITAL6_BAM_FIELD_RESERVED0_SHIFT                         11

/* Digital6 :: bam_field :: oui_1_0 [10:09] */
#define DIGITAL6_BAM_FIELD_OUI_1_0_MASK                            0x0600
#define DIGITAL6_BAM_FIELD_OUI_1_0_ALIGN                           0
#define DIGITAL6_BAM_FIELD_OUI_1_0_BITS                            2
#define DIGITAL6_BAM_FIELD_OUI_1_0_SHIFT                           9

/* Digital6 :: bam_field :: bam_field [08:00] */
#define DIGITAL6_BAM_FIELD_BAM_FIELD_MASK                          0x01ff
#define DIGITAL6_BAM_FIELD_BAM_FIELD_ALIGN                         0
#define DIGITAL6_BAM_FIELD_BAM_FIELD_BITS                          9
#define DIGITAL6_BAM_FIELD_BAM_FIELD_SHIFT                         0


/****************************************************************************
 * Digital6 :: ud_field
 ***************************************************************************/
/* Digital6 :: ud_field :: reserved0 [15:11] */
#define DIGITAL6_UD_FIELD_RESERVED0_MASK                           0xf800
#define DIGITAL6_UD_FIELD_RESERVED0_ALIGN                          0
#define DIGITAL6_UD_FIELD_RESERVED0_BITS                           5
#define DIGITAL6_UD_FIELD_RESERVED0_SHIFT                          11

/* Digital6 :: ud_field :: ud_reserved [10:06] */
#define DIGITAL6_UD_FIELD_UD_RESERVED_MASK                         0x07c0
#define DIGITAL6_UD_FIELD_UD_RESERVED_ALIGN                        0
#define DIGITAL6_UD_FIELD_UD_RESERVED_BITS                         5
#define DIGITAL6_UD_FIELD_UD_RESERVED_SHIFT                        6

/* Digital6 :: ud_field :: remote_BN_page [05:05] */
#define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_MASK                      0x0020
#define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_ALIGN                     0
#define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_BITS                      1
#define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_SHIFT                     5

/* Digital6 :: ud_field :: inband_MDIO [04:04] */
#define DIGITAL6_UD_FIELD_INBAND_MDIO_MASK                         0x0010
#define DIGITAL6_UD_FIELD_INBAND_MDIO_ALIGN                        0
#define DIGITAL6_UD_FIELD_INBAND_MDIO_BITS                         1
#define DIGITAL6_UD_FIELD_INBAND_MDIO_SHIFT                        4

/* Digital6 :: ud_field :: autoneg_MDIO [03:03] */
#define DIGITAL6_UD_FIELD_AUTONEG_MDIO_MASK                        0x0008
#define DIGITAL6_UD_FIELD_AUTONEG_MDIO_ALIGN                       0
#define DIGITAL6_UD_FIELD_AUTONEG_MDIO_BITS                        1
#define DIGITAL6_UD_FIELD_AUTONEG_MDIO_SHIFT                       3

/* Digital6 :: ud_field :: remote_serdes_phy [02:02] */
#define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_MASK                   0x0004
#define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_ALIGN                  0
#define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_BITS                   1
#define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_SHIFT                  2

/* Digital6 :: ud_field :: remote_cu_phy [01:01] */
#define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_MASK                       0x0002
#define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_ALIGN                      0
#define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_BITS                       1
#define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_SHIFT                      1

/* Digital6 :: ud_field :: over1g [00:00] */
#define DIGITAL6_UD_FIELD_OVER1G_MASK                              0x0001
#define DIGITAL6_UD_FIELD_OVER1G_ALIGN                             0
#define DIGITAL6_UD_FIELD_OVER1G_BITS                              1
#define DIGITAL6_UD_FIELD_OVER1G_SHIFT                             0


/****************************************************************************
 * Digital6 :: lp_oui_msb_field
 ***************************************************************************/
/* Digital6 :: lp_oui_msb_field :: reserved0 [15:11] */
#define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_MASK                   0xf800
#define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_ALIGN                  0
#define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_BITS                   5
#define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_SHIFT                  11

/* Digital6 :: lp_oui_msb_field :: oui_msb_field [10:00] */
#define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_MASK               0x07ff
#define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_ALIGN              0
#define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_BITS               11
#define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_SHIFT              0


/****************************************************************************
 * Digital6 :: lp_oui_lsb_field
 ***************************************************************************/
/* Digital6 :: lp_oui_lsb_field :: reserved0 [15:11] */
#define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_MASK                   0xf800
#define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_ALIGN                  0
#define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_BITS                   5
#define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_SHIFT                  11

/* Digital6 :: lp_oui_lsb_field :: oui_lsb_field [10:00] */
#define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_MASK               0x07ff
#define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_ALIGN              0
#define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_BITS               11
#define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_SHIFT              0


/****************************************************************************
 * Digital6 :: lp_bam_field
 ***************************************************************************/
/* Digital6 :: lp_bam_field :: reserved0 [15:11] */
#define DIGITAL6_LP_BAM_FIELD_RESERVED0_MASK                       0xf800
#define DIGITAL6_LP_BAM_FIELD_RESERVED0_ALIGN                      0
#define DIGITAL6_LP_BAM_FIELD_RESERVED0_BITS                       5
#define DIGITAL6_LP_BAM_FIELD_RESERVED0_SHIFT                      11

/* Digital6 :: lp_bam_field :: oui_1_0 [10:09] */
#define DIGITAL6_LP_BAM_FIELD_OUI_1_0_MASK                         0x0600
#define DIGITAL6_LP_BAM_FIELD_OUI_1_0_ALIGN                        0
#define DIGITAL6_LP_BAM_FIELD_OUI_1_0_BITS                         2
#define DIGITAL6_LP_BAM_FIELD_OUI_1_0_SHIFT                        9

/* Digital6 :: lp_bam_field :: bam_field [08:00] */
#define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_MASK                       0x01ff
#define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_ALIGN                      0
#define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_BITS                       9
#define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_SHIFT                      0


/****************************************************************************
 * Digital6 :: lp_ud_field
 ***************************************************************************/
/* Digital6 :: lp_ud_field :: reserved0 [15:11] */
#define DIGITAL6_LP_UD_FIELD_RESERVED0_MASK                        0xf800
#define DIGITAL6_LP_UD_FIELD_RESERVED0_ALIGN                       0
#define DIGITAL6_LP_UD_FIELD_RESERVED0_BITS                        5
#define DIGITAL6_LP_UD_FIELD_RESERVED0_SHIFT                       11

/* Digital6 :: lp_ud_field :: ud_reserved [10:06] */
#define DIGITAL6_LP_UD_FIELD_UD_RESERVED_MASK                      0x07c0
#define DIGITAL6_LP_UD_FIELD_UD_RESERVED_ALIGN                     0
#define DIGITAL6_LP_UD_FIELD_UD_RESERVED_BITS                      5
#define DIGITAL6_LP_UD_FIELD_UD_RESERVED_SHIFT                     6

/* Digital6 :: lp_ud_field :: remote_BN_page [05:05] */
#define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_MASK                   0x0020
#define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_ALIGN                  0
#define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_BITS                   1
#define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_SHIFT                  5

/* Digital6 :: lp_ud_field :: inband_MDIO [04:04] */
#define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_MASK                      0x0010
#define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_ALIGN                     0
#define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_BITS                      1
#define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_SHIFT                     4

/* Digital6 :: lp_ud_field :: autoneg_MDIO [03:03] */
#define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_MASK                     0x0008
#define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_ALIGN                    0
#define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_BITS                     1
#define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_SHIFT                    3

/* Digital6 :: lp_ud_field :: remote_serdes_phy [02:02] */
#define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_MASK                0x0004
#define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_ALIGN               0
#define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_BITS                1
#define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_SHIFT               2

/* Digital6 :: lp_ud_field :: remote_cu_phy [01:01] */
#define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_MASK                    0x0002
#define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_ALIGN                   0
#define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_BITS                    1
#define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_SHIFT                   1

/* Digital6 :: lp_ud_field :: over1g [00:00] */
#define DIGITAL6_LP_UD_FIELD_OVER1G_MASK                           0x0001
#define DIGITAL6_LP_UD_FIELD_OVER1G_ALIGN                          0
#define DIGITAL6_LP_UD_FIELD_OVER1G_BITS                           1
#define DIGITAL6_LP_UD_FIELD_OVER1G_SHIFT                          0


/****************************************************************************
 * Hypercore_USER_CL73_UserB0
 ***************************************************************************/
/****************************************************************************
 * CL73_UserB0 :: CL73_UCtrl1
 ***************************************************************************/
/* CL73_UserB0 :: CL73_UCtrl1 :: reserved0 [15:13] */
#define CL73_USERB0_CL73_UCTRL1_RESERVED0_MASK                     0xe000
#define CL73_USERB0_CL73_UCTRL1_RESERVED0_ALIGN                    0
#define CL73_USERB0_CL73_UCTRL1_RESERVED0_BITS                     3
#define CL73_USERB0_CL73_UCTRL1_RESERVED0_SHIFT                    13

/* CL73_UserB0 :: CL73_UCtrl1 :: cl73_lossOfSyncFail_en [12:12] */
#define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_MASK        0x1000
#define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_ALIGN       0
#define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_BITS        1
#define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_SHIFT       12

/* CL73_UserB0 :: CL73_UCtrl1 :: cl73_parDet_dis [11:11] */
#define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_MASK               0x0800
#define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_ALIGN              0
#define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_BITS               1
#define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_SHIFT              11

/* CL73_UserB0 :: CL73_UCtrl1 :: cl73_allowCl37AN [10:10] */
#define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_MASK              0x0400
#define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_ALIGN             0
#define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_BITS              1
#define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_SHIFT             10

/* CL73_UserB0 :: CL73_UCtrl1 :: longParDetTimer_dis [09:09] */
#define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_MASK           0x0200
#define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_ALIGN          0
#define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_BITS           1
#define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_SHIFT          9

/* CL73_UserB0 :: CL73_UCtrl1 :: linkFailTimer_dis [08:08] */
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_MASK             0x0100
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_ALIGN            0
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_BITS             1
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_SHIFT            8

/* CL73_UserB0 :: CL73_UCtrl1 :: linkFailTimerQual_en [07:07] */
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_MASK          0x0080
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_ALIGN         0
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_BITS          1
#define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_SHIFT         7

/* CL73_UserB0 :: CL73_UCtrl1 :: cl73_nonce_match_over [06:06] */
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_MASK         0x0040
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_ALIGN        0
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_BITS         1
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_SHIFT        6

/* CL73_UserB0 :: CL73_UCtrl1 :: cl73_nonce_match_val [05:05] */
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_MASK          0x0020
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_ALIGN         0
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_BITS          1
#define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_SHIFT         5

/* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl73_restart_wo_link_fail [04:04] */
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_MASK 0x0010
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_ALIGN 0
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_BITS 1
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_SHIFT 4

/* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl73_restart [03:03] */
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_MASK         0x0008
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_ALIGN        0
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_BITS         1
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_SHIFT        3

/* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl37_restart [02:02] */
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_MASK         0x0004
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_ALIGN        0
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_BITS         1
#define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_SHIFT        2

/* CL73_UserB0 :: CL73_UCtrl1 :: CL73_Ustat1_muxsel [01:01] */
#define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_MASK            0x0002
#define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_ALIGN           0
#define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_BITS            1
#define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_SHIFT           1

/* CL73_UserB0 :: CL73_UCtrl1 :: force_cl73_tx_omux_en [00:00] */
#define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_MASK         0x0001
#define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_ALIGN        0
#define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_BITS         1
#define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_SHIFT        0


/****************************************************************************
 * CL73_UserB0 :: CL73_Ustat1
 ***************************************************************************/
/* CL73_UserB0 :: CL73_Ustat1 :: reserved0 [15:10] */
#define CL73_USERB0_CL73_USTAT1_RESERVED0_MASK                     0xfc00
#define CL73_USERB0_CL73_USTAT1_RESERVED0_ALIGN                    0
#define CL73_USERB0_CL73_USTAT1_RESERVED0_BITS                     6
#define CL73_USERB0_CL73_USTAT1_RESERVED0_SHIFT                    10

/* CL73_UserB0 :: CL73_Ustat1 :: arb_fsm [09:00] */
#define CL73_USERB0_CL73_USTAT1_ARB_FSM_MASK                       0x03ff
#define CL73_USERB0_CL73_USTAT1_ARB_FSM_ALIGN                      0
#define CL73_USERB0_CL73_USTAT1_ARB_FSM_BITS                       10
#define CL73_USERB0_CL73_USTAT1_ARB_FSM_SHIFT                      0


/****************************************************************************
 * CL73_UserB0 :: CL73_BAMCtrl1
 ***************************************************************************/
/* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bamEn [15:15] */
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_MASK                  0x8000
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_ALIGN                 0
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_BITS                  1
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_SHIFT                 15

/* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_station_mngr_en [14:14] */
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_MASK    0x4000
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_ALIGN   0
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_BITS    1
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_SHIFT   14

/* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bamNP_after_bp_en [13:13] */
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_MASK      0x2000
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_ALIGN     0
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_BITS      1
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_SHIFT     13

/* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_en [12:12] */
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_MASK   0x1000
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_ALIGN  0
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_BITS   1
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_SHIFT  12

/* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_step [11:11] */
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_MASK 0x0800
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_ALIGN 0
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_BITS 1
#define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_SHIFT 11

/* CL73_UserB0 :: CL73_BAMCtrl1 :: reserved0 [10:10] */
#define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_MASK                   0x0400
#define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_ALIGN                  0
#define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_BITS                   1
#define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_SHIFT                  10

/* CL73_UserB0 :: CL73_BAMCtrl1 :: UD_code_field [09:00] */
#define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_MASK               0x03ff
#define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_ALIGN              0
#define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_BITS               10
#define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_SHIFT              0


/****************************************************************************
 * CL73_UserB0 :: CL73_BAMCtrl2
 ***************************************************************************/
/* CL73_UserB0 :: CL73_BAMCtrl2 :: UD_code_field [15:00] */
#define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_MASK               0xffff
#define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_ALIGN              0
#define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_BITS               16
#define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_SHIFT              0


/****************************************************************************
 * CL73_UserB0 :: CL73_BAMCtrl3
 ***************************************************************************/
/* CL73_UserB0 :: CL73_BAMCtrl3 :: UD_code_field [15:00] */
#define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_MASK               0xffff
#define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_ALIGN              0
#define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_BITS               16
#define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_SHIFT              0


/****************************************************************************
 * CL73_UserB0 :: CL73_BAMStat1
 ***************************************************************************/
/* CL73_UserB0 :: CL73_BAMStat1 :: reserved0 [15:10] */
#define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_MASK                   0xfc00
#define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_ALIGN                  0
#define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_BITS                   6
#define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_SHIFT                  10

/* CL73_UserB0 :: CL73_BAMStat1 :: LP_UD_code_field [09:00] */
#define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_MASK            0x03ff
#define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_ALIGN           0
#define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_BITS            10
#define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_SHIFT           0


/****************************************************************************
 * CL73_UserB0 :: CL73_BAMStat2
 ***************************************************************************/
/* CL73_UserB0 :: CL73_BAMStat2 :: LP_UD_code_field [15:00] */
#define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_MASK            0xffff
#define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_ALIGN           0
#define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_BITS            16
#define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_SHIFT           0


/****************************************************************************
 * CL73_UserB0 :: CL73_BAMStat3
 ***************************************************************************/
/* CL73_UserB0 :: CL73_BAMStat3 :: LP_UD_code_field [15:00] */
#define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_MASK            0xffff
#define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_ALIGN           0
#define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_BITS            16
#define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_SHIFT           0


/****************************************************************************
 * Hypercore_USER_Dsc4b0
 ***************************************************************************/
/****************************************************************************
 * Dsc4b0 :: sm_ctrl13
 ***************************************************************************/
/* Dsc4b0 :: sm_ctrl13 :: reserved0 [15:15] */
#define DSC4B0_SM_CTRL13_RESERVED0_MASK                            0x8000
#define DSC4B0_SM_CTRL13_RESERVED0_ALIGN                           0
#define DSC4B0_SM_CTRL13_RESERVED0_BITS                            1
#define DSC4B0_SM_CTRL13_RESERVED0_SHIFT                           15

/* Dsc4b0 :: sm_ctrl13 :: br_vga_trn2_timeout [14:10] */
#define DSC4B0_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_MASK                  0x7c00
#define DSC4B0_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_ALIGN                 0
#define DSC4B0_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_BITS                  5
#define DSC4B0_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_SHIFT                 10

/* Dsc4b0 :: sm_ctrl13 :: br_pf_trn2_timeout [09:05] */
#define DSC4B0_SM_CTRL13_BR_PF_TRN2_TIMEOUT_MASK                   0x03e0
#define DSC4B0_SM_CTRL13_BR_PF_TRN2_TIMEOUT_ALIGN                  0
#define DSC4B0_SM_CTRL13_BR_PF_TRN2_TIMEOUT_BITS                   5
#define DSC4B0_SM_CTRL13_BR_PF_TRN2_TIMEOUT_SHIFT                  5

/* Dsc4b0 :: sm_ctrl13 :: br_pf_trn1_timeout [04:00] */
#define DSC4B0_SM_CTRL13_BR_PF_TRN1_TIMEOUT_MASK                   0x001f
#define DSC4B0_SM_CTRL13_BR_PF_TRN1_TIMEOUT_ALIGN                  0
#define DSC4B0_SM_CTRL13_BR_PF_TRN1_TIMEOUT_BITS                   5
#define DSC4B0_SM_CTRL13_BR_PF_TRN1_TIMEOUT_SHIFT                  0


/****************************************************************************
 * Dsc4b0 :: sm_ctrl14
 ***************************************************************************/
/* Dsc4b0 :: sm_ctrl14 :: reserved0 [15:14] */
#define DSC4B0_SM_CTRL14_RESERVED0_MASK                            0xc000
#define DSC4B0_SM_CTRL14_RESERVED0_ALIGN                           0
#define DSC4B0_SM_CTRL14_RESERVED0_BITS                            2
#define DSC4B0_SM_CTRL14_RESERVED0_SHIFT                           14

/* Dsc4b0 :: sm_ctrl14 :: br_postc_tap_en [13:07] */
#define DSC4B0_SM_CTRL14_BR_POSTC_TAP_EN_MASK                      0x3f80
#define DSC4B0_SM_CTRL14_BR_POSTC_TAP_EN_ALIGN                     0
#define DSC4B0_SM_CTRL14_BR_POSTC_TAP_EN_BITS                      7
#define DSC4B0_SM_CTRL14_BR_POSTC_TAP_EN_SHIFT                     7

/* Dsc4b0 :: sm_ctrl14 :: osx2_pf_tap_en [06:00] */
#define DSC4B0_SM_CTRL14_OSX2_PF_TAP_EN_MASK                       0x007f
#define DSC4B0_SM_CTRL14_OSX2_PF_TAP_EN_ALIGN                      0
#define DSC4B0_SM_CTRL14_OSX2_PF_TAP_EN_BITS                       7
#define DSC4B0_SM_CTRL14_OSX2_PF_TAP_EN_SHIFT                      0


/****************************************************************************
 * Dsc4b0 :: sm_ctrl15
 ***************************************************************************/
/* Dsc4b0 :: sm_ctrl15 :: reserved0 [15:14] */
#define DSC4B0_SM_CTRL15_RESERVED0_MASK                            0xc000
#define DSC4B0_SM_CTRL15_RESERVED0_ALIGN                           0
#define DSC4B0_SM_CTRL15_RESERVED0_BITS                            2
#define DSC4B0_SM_CTRL15_RESERVED0_SHIFT                           14

/* Dsc4b0 :: sm_ctrl15 :: osx2_postc_tap_en [13:07] */
#define DSC4B0_SM_CTRL15_OSX2_POSTC_TAP_EN_MASK                    0x3f80
#define DSC4B0_SM_CTRL15_OSX2_POSTC_TAP_EN_ALIGN                   0
#define DSC4B0_SM_CTRL15_OSX2_POSTC_TAP_EN_BITS                    7
#define DSC4B0_SM_CTRL15_OSX2_POSTC_TAP_EN_SHIFT                   7

/* Dsc4b0 :: sm_ctrl15 :: osx1_postc_tap_en [06:00] */
#define DSC4B0_SM_CTRL15_OSX1_POSTC_TAP_EN_MASK                    0x007f
#define DSC4B0_SM_CTRL15_OSX1_POSTC_TAP_EN_ALIGN                   0
#define DSC4B0_SM_CTRL15_OSX1_POSTC_TAP_EN_BITS                    7
#define DSC4B0_SM_CTRL15_OSX1_POSTC_TAP_EN_SHIFT                   0


/****************************************************************************
 * Dsc4b0 :: sm_ctrl16
 ***************************************************************************/
/* Dsc4b0 :: sm_ctrl16 :: reserved0 [15:15] */
#define DSC4B0_SM_CTRL16_RESERVED0_MASK                            0x8000
#define DSC4B0_SM_CTRL16_RESERVED0_ALIGN                           0
#define DSC4B0_SM_CTRL16_RESERVED0_BITS                            1
#define DSC4B0_SM_CTRL16_RESERVED0_SHIFT                           15

/* Dsc4b0 :: sm_ctrl16 :: msr_slicer_slow_timeout [14:10] */
#define DSC4B0_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_MASK              0x7c00
#define DSC4B0_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_ALIGN             0
#define DSC4B0_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_BITS              5
#define DSC4B0_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_SHIFT             10

/* Dsc4b0 :: sm_ctrl16 :: msr_slicer_fast_timeout [09:05] */
#define DSC4B0_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_MASK              0x03e0
#define DSC4B0_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_ALIGN             0
#define DSC4B0_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_BITS              5
#define DSC4B0_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_SHIFT             5

/* Dsc4b0 :: sm_ctrl16 :: default_trn2_timeout [04:00] */
#define DSC4B0_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_MASK                 0x001f
#define DSC4B0_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_ALIGN                0
#define DSC4B0_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_BITS                 5
#define DSC4B0_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_SHIFT                0


/****************************************************************************
 * Dsc4b0 :: sm_ctrl17
 ***************************************************************************/
/* Dsc4b0 :: sm_ctrl17 :: reserved0 [15:02] */
#define DSC4B0_SM_CTRL17_RESERVED0_MASK                            0xfffc
#define DSC4B0_SM_CTRL17_RESERVED0_ALIGN                           0
#define DSC4B0_SM_CTRL17_RESERVED0_BITS                            14
#define DSC4B0_SM_CTRL17_RESERVED0_SHIFT                           2

/* Dsc4b0 :: sm_ctrl17 :: bypass_osx1_slicer_cal [01:01] */
#define DSC4B0_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_MASK               0x0002
#define DSC4B0_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_ALIGN              0
#define DSC4B0_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_BITS               1
#define DSC4B0_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_SHIFT              1

/* Dsc4b0 :: sm_ctrl17 :: bypass_osx2_slicer_cal [00:00] */
#define DSC4B0_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_MASK               0x0001
#define DSC4B0_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_ALIGN              0
#define DSC4B0_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_BITS               1
#define DSC4B0_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_SHIFT              0


/****************************************************************************
 * Dsc4b0 :: sm_status7
 ***************************************************************************/
/* Dsc4b0 :: sm_status7 :: reserved_for_eco0 [15:12] */
#define DSC4B0_SM_STATUS7_RESERVED_FOR_ECO0_MASK                   0xf000
#define DSC4B0_SM_STATUS7_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC4B0_SM_STATUS7_RESERVED_FOR_ECO0_BITS                   4
#define DSC4B0_SM_STATUS7_RESERVED_FOR_ECO0_SHIFT                  12

/* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_11 [11:11] */
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_11_MASK                0x0800
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_11_ALIGN               0
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_11_BITS                1
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_11_SHIFT               11

/* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_10 [10:10] */
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_10_MASK                0x0400
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_10_ALIGN               0
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_10_BITS                1
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_10_SHIFT               10

/* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_9 [09:09] */
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_9_MASK                 0x0200
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_9_ALIGN                0
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_9_BITS                 1
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_9_SHIFT                9

/* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_8 [08:08] */
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_8_MASK                 0x0100
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_8_ALIGN                0
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_8_BITS                 1
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_8_SHIFT                8

/* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_7 [07:07] */
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_7_MASK                 0x0080
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_7_ALIGN                0
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_7_BITS                 1
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_7_SHIFT                7

/* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_6 [06:06] */
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_6_MASK                 0x0040
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_6_ALIGN                0
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_6_BITS                 1
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_6_SHIFT                6

/* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_5 [05:05] */
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_5_MASK                 0x0020
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_5_ALIGN                0
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_5_BITS                 1
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_5_SHIFT                5

/* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_4 [04:04] */
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_4_MASK                 0x0010
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_4_ALIGN                0
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_4_BITS                 1
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_4_SHIFT                4

/* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_3 [03:03] */
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_3_MASK                 0x0008
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_3_ALIGN                0
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_3_BITS                 1
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_3_SHIFT                3

/* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_2 [02:02] */
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_2_MASK                 0x0004
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_2_ALIGN                0
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_2_BITS                 1
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_2_SHIFT                2

/* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_1 [01:01] */
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_1_MASK                 0x0002
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_1_ALIGN                0
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_1_BITS                 1
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_1_SHIFT                1

/* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_0 [00:00] */
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_0_MASK                 0x0001
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_0_ALIGN                0
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_0_BITS                 1
#define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_0_SHIFT                0


/****************************************************************************
 * Dsc4b0 :: sm_status8
 ***************************************************************************/
/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_15 [15:15] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_15_MASK             0x8000
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_15_ALIGN            0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_15_BITS             1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_15_SHIFT            15

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_14 [14:14] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_14_MASK             0x4000
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_14_ALIGN            0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_14_BITS             1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_14_SHIFT            14

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_13 [13:13] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_13_MASK             0x2000
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_13_ALIGN            0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_13_BITS             1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_13_SHIFT            13

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_12 [12:12] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_12_MASK             0x1000
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_12_ALIGN            0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_12_BITS             1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_12_SHIFT            12

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_11 [11:11] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_11_MASK             0x0800
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_11_ALIGN            0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_11_BITS             1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_11_SHIFT            11

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_10 [10:10] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_10_MASK             0x0400
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_10_ALIGN            0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_10_BITS             1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_10_SHIFT            10

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_9 [09:09] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_9_MASK              0x0200
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_9_ALIGN             0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_9_BITS              1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_9_SHIFT             9

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_8 [08:08] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_8_MASK              0x0100
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_8_ALIGN             0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_8_BITS              1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_8_SHIFT             8

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_7 [07:07] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_7_MASK              0x0080
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_7_ALIGN             0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_7_BITS              1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_7_SHIFT             7

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_6 [06:06] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_6_MASK              0x0040
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_6_ALIGN             0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_6_BITS              1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_6_SHIFT             6

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_5 [05:05] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_5_MASK              0x0020
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_5_ALIGN             0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_5_BITS              1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_5_SHIFT             5

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_4 [04:04] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_4_MASK              0x0010
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_4_ALIGN             0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_4_BITS              1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_4_SHIFT             4

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_3 [03:03] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_3_MASK              0x0008
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_3_ALIGN             0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_3_BITS              1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_3_SHIFT             3

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_2 [02:02] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_2_MASK              0x0004
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_2_ALIGN             0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_2_BITS              1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_2_SHIFT             2

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_1 [01:01] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_1_MASK              0x0002
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_1_ALIGN             0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_1_BITS              1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_1_SHIFT             1

/* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_0 [00:00] */
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_0_MASK              0x0001
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_0_ALIGN             0
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_0_BITS              1
#define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_0_SHIFT             0


/****************************************************************************
 * Dsc4b0 :: sm_status9
 ***************************************************************************/
/* Dsc4b0 :: sm_status9 :: reserved_for_eco0 [15:12] */
#define DSC4B0_SM_STATUS9_RESERVED_FOR_ECO0_MASK                   0xf000
#define DSC4B0_SM_STATUS9_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC4B0_SM_STATUS9_RESERVED_FOR_ECO0_BITS                   4
#define DSC4B0_SM_STATUS9_RESERVED_FOR_ECO0_SHIFT                  12

/* Dsc4b0 :: sm_status9 :: tuning_state_one_hot_17 [11:11] */
#define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_17_MASK             0x0800
#define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_17_ALIGN            0
#define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_17_BITS             1
#define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_17_SHIFT            11

/* Dsc4b0 :: sm_status9 :: tuning_state_one_hot_16 [10:10] */
#define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_16_MASK             0x0400
#define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_16_ALIGN            0
#define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_16_BITS             1
#define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_16_SHIFT            10

/* Dsc4b0 :: sm_status9 :: srch_state_one_hot_9 [09:09] */
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_9_MASK                0x0200
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_9_ALIGN               0
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_9_BITS                1
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_9_SHIFT               9

/* Dsc4b0 :: sm_status9 :: srch_state_one_hot_8 [08:08] */
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_8_MASK                0x0100
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_8_ALIGN               0
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_8_BITS                1
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_8_SHIFT               8

/* Dsc4b0 :: sm_status9 :: srch_state_one_hot_7 [07:07] */
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_7_MASK                0x0080
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_7_ALIGN               0
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_7_BITS                1
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_7_SHIFT               7

/* Dsc4b0 :: sm_status9 :: srch_state_one_hot_6 [06:06] */
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_6_MASK                0x0040
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_6_ALIGN               0
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_6_BITS                1
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_6_SHIFT               6

/* Dsc4b0 :: sm_status9 :: srch_state_one_hot_5 [05:05] */
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_5_MASK                0x0020
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_5_ALIGN               0
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_5_BITS                1
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_5_SHIFT               5

/* Dsc4b0 :: sm_status9 :: srch_state_one_hot_4 [04:04] */
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_4_MASK                0x0010
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_4_ALIGN               0
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_4_BITS                1
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_4_SHIFT               4

/* Dsc4b0 :: sm_status9 :: srch_state_one_hot_3 [03:03] */
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_3_MASK                0x0008
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_3_ALIGN               0
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_3_BITS                1
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_3_SHIFT               3

/* Dsc4b0 :: sm_status9 :: srch_state_one_hot_2 [02:02] */
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_2_MASK                0x0004
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_2_ALIGN               0
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_2_BITS                1
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_2_SHIFT               2

/* Dsc4b0 :: sm_status9 :: srch_state_one_hot_1 [01:01] */
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_1_MASK                0x0002
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_1_ALIGN               0
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_1_BITS                1
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_1_SHIFT               1

/* Dsc4b0 :: sm_status9 :: srch_state_one_hot_0 [00:00] */
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_0_MASK                0x0001
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_0_ALIGN               0
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_0_BITS                1
#define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_0_SHIFT               0


/****************************************************************************
 * Hypercore_USER_Dsc4b1
 ***************************************************************************/
/****************************************************************************
 * Dsc4b1 :: sm_ctrl13
 ***************************************************************************/
/* Dsc4b1 :: sm_ctrl13 :: reserved0 [15:15] */
#define DSC4B1_SM_CTRL13_RESERVED0_MASK                            0x8000
#define DSC4B1_SM_CTRL13_RESERVED0_ALIGN                           0
#define DSC4B1_SM_CTRL13_RESERVED0_BITS                            1
#define DSC4B1_SM_CTRL13_RESERVED0_SHIFT                           15

/* Dsc4b1 :: sm_ctrl13 :: br_vga_trn2_timeout [14:10] */
#define DSC4B1_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_MASK                  0x7c00
#define DSC4B1_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_ALIGN                 0
#define DSC4B1_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_BITS                  5
#define DSC4B1_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_SHIFT                 10

/* Dsc4b1 :: sm_ctrl13 :: br_pf_trn2_timeout [09:05] */
#define DSC4B1_SM_CTRL13_BR_PF_TRN2_TIMEOUT_MASK                   0x03e0
#define DSC4B1_SM_CTRL13_BR_PF_TRN2_TIMEOUT_ALIGN                  0
#define DSC4B1_SM_CTRL13_BR_PF_TRN2_TIMEOUT_BITS                   5
#define DSC4B1_SM_CTRL13_BR_PF_TRN2_TIMEOUT_SHIFT                  5

/* Dsc4b1 :: sm_ctrl13 :: br_pf_trn1_timeout [04:00] */
#define DSC4B1_SM_CTRL13_BR_PF_TRN1_TIMEOUT_MASK                   0x001f
#define DSC4B1_SM_CTRL13_BR_PF_TRN1_TIMEOUT_ALIGN                  0
#define DSC4B1_SM_CTRL13_BR_PF_TRN1_TIMEOUT_BITS                   5
#define DSC4B1_SM_CTRL13_BR_PF_TRN1_TIMEOUT_SHIFT                  0


/****************************************************************************
 * Dsc4b1 :: sm_ctrl14
 ***************************************************************************/
/* Dsc4b1 :: sm_ctrl14 :: reserved0 [15:14] */
#define DSC4B1_SM_CTRL14_RESERVED0_MASK                            0xc000
#define DSC4B1_SM_CTRL14_RESERVED0_ALIGN                           0
#define DSC4B1_SM_CTRL14_RESERVED0_BITS                            2
#define DSC4B1_SM_CTRL14_RESERVED0_SHIFT                           14

/* Dsc4b1 :: sm_ctrl14 :: br_postc_tap_en [13:07] */
#define DSC4B1_SM_CTRL14_BR_POSTC_TAP_EN_MASK                      0x3f80
#define DSC4B1_SM_CTRL14_BR_POSTC_TAP_EN_ALIGN                     0
#define DSC4B1_SM_CTRL14_BR_POSTC_TAP_EN_BITS                      7
#define DSC4B1_SM_CTRL14_BR_POSTC_TAP_EN_SHIFT                     7

/* Dsc4b1 :: sm_ctrl14 :: osx2_pf_tap_en [06:00] */
#define DSC4B1_SM_CTRL14_OSX2_PF_TAP_EN_MASK                       0x007f
#define DSC4B1_SM_CTRL14_OSX2_PF_TAP_EN_ALIGN                      0
#define DSC4B1_SM_CTRL14_OSX2_PF_TAP_EN_BITS                       7
#define DSC4B1_SM_CTRL14_OSX2_PF_TAP_EN_SHIFT                      0


/****************************************************************************
 * Dsc4b1 :: sm_ctrl15
 ***************************************************************************/
/* Dsc4b1 :: sm_ctrl15 :: reserved0 [15:14] */
#define DSC4B1_SM_CTRL15_RESERVED0_MASK                            0xc000
#define DSC4B1_SM_CTRL15_RESERVED0_ALIGN                           0
#define DSC4B1_SM_CTRL15_RESERVED0_BITS                            2
#define DSC4B1_SM_CTRL15_RESERVED0_SHIFT                           14

/* Dsc4b1 :: sm_ctrl15 :: osx2_postc_tap_en [13:07] */
#define DSC4B1_SM_CTRL15_OSX2_POSTC_TAP_EN_MASK                    0x3f80
#define DSC4B1_SM_CTRL15_OSX2_POSTC_TAP_EN_ALIGN                   0
#define DSC4B1_SM_CTRL15_OSX2_POSTC_TAP_EN_BITS                    7
#define DSC4B1_SM_CTRL15_OSX2_POSTC_TAP_EN_SHIFT                   7

/* Dsc4b1 :: sm_ctrl15 :: osx1_postc_tap_en [06:00] */
#define DSC4B1_SM_CTRL15_OSX1_POSTC_TAP_EN_MASK                    0x007f
#define DSC4B1_SM_CTRL15_OSX1_POSTC_TAP_EN_ALIGN                   0
#define DSC4B1_SM_CTRL15_OSX1_POSTC_TAP_EN_BITS                    7
#define DSC4B1_SM_CTRL15_OSX1_POSTC_TAP_EN_SHIFT                   0


/****************************************************************************
 * Dsc4b1 :: sm_ctrl16
 ***************************************************************************/
/* Dsc4b1 :: sm_ctrl16 :: reserved0 [15:15] */
#define DSC4B1_SM_CTRL16_RESERVED0_MASK                            0x8000
#define DSC4B1_SM_CTRL16_RESERVED0_ALIGN                           0
#define DSC4B1_SM_CTRL16_RESERVED0_BITS                            1
#define DSC4B1_SM_CTRL16_RESERVED0_SHIFT                           15

/* Dsc4b1 :: sm_ctrl16 :: msr_slicer_slow_timeout [14:10] */
#define DSC4B1_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_MASK              0x7c00
#define DSC4B1_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_ALIGN             0
#define DSC4B1_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_BITS              5
#define DSC4B1_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_SHIFT             10

/* Dsc4b1 :: sm_ctrl16 :: msr_slicer_fast_timeout [09:05] */
#define DSC4B1_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_MASK              0x03e0
#define DSC4B1_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_ALIGN             0
#define DSC4B1_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_BITS              5
#define DSC4B1_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_SHIFT             5

/* Dsc4b1 :: sm_ctrl16 :: default_trn2_timeout [04:00] */
#define DSC4B1_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_MASK                 0x001f
#define DSC4B1_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_ALIGN                0
#define DSC4B1_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_BITS                 5
#define DSC4B1_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_SHIFT                0


/****************************************************************************
 * Dsc4b1 :: sm_ctrl17
 ***************************************************************************/
/* Dsc4b1 :: sm_ctrl17 :: reserved0 [15:02] */
#define DSC4B1_SM_CTRL17_RESERVED0_MASK                            0xfffc
#define DSC4B1_SM_CTRL17_RESERVED0_ALIGN                           0
#define DSC4B1_SM_CTRL17_RESERVED0_BITS                            14
#define DSC4B1_SM_CTRL17_RESERVED0_SHIFT                           2

/* Dsc4b1 :: sm_ctrl17 :: bypass_osx1_slicer_cal [01:01] */
#define DSC4B1_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_MASK               0x0002
#define DSC4B1_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_ALIGN              0
#define DSC4B1_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_BITS               1
#define DSC4B1_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_SHIFT              1

/* Dsc4b1 :: sm_ctrl17 :: bypass_osx2_slicer_cal [00:00] */
#define DSC4B1_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_MASK               0x0001
#define DSC4B1_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_ALIGN              0
#define DSC4B1_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_BITS               1
#define DSC4B1_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_SHIFT              0


/****************************************************************************
 * Dsc4b1 :: sm_status7
 ***************************************************************************/
/* Dsc4b1 :: sm_status7 :: reserved_for_eco0 [15:12] */
#define DSC4B1_SM_STATUS7_RESERVED_FOR_ECO0_MASK                   0xf000
#define DSC4B1_SM_STATUS7_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC4B1_SM_STATUS7_RESERVED_FOR_ECO0_BITS                   4
#define DSC4B1_SM_STATUS7_RESERVED_FOR_ECO0_SHIFT                  12

/* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_11 [11:11] */
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_11_MASK                0x0800
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_11_ALIGN               0
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_11_BITS                1
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_11_SHIFT               11

/* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_10 [10:10] */
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_10_MASK                0x0400
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_10_ALIGN               0
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_10_BITS                1
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_10_SHIFT               10

/* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_9 [09:09] */
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_9_MASK                 0x0200
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_9_ALIGN                0
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_9_BITS                 1
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_9_SHIFT                9

/* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_8 [08:08] */
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_8_MASK                 0x0100
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_8_ALIGN                0
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_8_BITS                 1
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_8_SHIFT                8

/* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_7 [07:07] */
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_7_MASK                 0x0080
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_7_ALIGN                0
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_7_BITS                 1
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_7_SHIFT                7

/* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_6 [06:06] */
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_6_MASK                 0x0040
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_6_ALIGN                0
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_6_BITS                 1
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_6_SHIFT                6

/* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_5 [05:05] */
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_5_MASK                 0x0020
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_5_ALIGN                0
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_5_BITS                 1
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_5_SHIFT                5

/* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_4 [04:04] */
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_4_MASK                 0x0010
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_4_ALIGN                0
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_4_BITS                 1
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_4_SHIFT                4

/* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_3 [03:03] */
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_3_MASK                 0x0008
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_3_ALIGN                0
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_3_BITS                 1
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_3_SHIFT                3

/* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_2 [02:02] */
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_2_MASK                 0x0004
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_2_ALIGN                0
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_2_BITS                 1
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_2_SHIFT                2

/* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_1 [01:01] */
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_1_MASK                 0x0002
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_1_ALIGN                0
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_1_BITS                 1
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_1_SHIFT                1

/* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_0 [00:00] */
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_0_MASK                 0x0001
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_0_ALIGN                0
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_0_BITS                 1
#define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_0_SHIFT                0


/****************************************************************************
 * Dsc4b1 :: sm_status8
 ***************************************************************************/
/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_15 [15:15] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_15_MASK             0x8000
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_15_ALIGN            0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_15_BITS             1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_15_SHIFT            15

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_14 [14:14] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_14_MASK             0x4000
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_14_ALIGN            0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_14_BITS             1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_14_SHIFT            14

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_13 [13:13] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_13_MASK             0x2000
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_13_ALIGN            0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_13_BITS             1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_13_SHIFT            13

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_12 [12:12] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_12_MASK             0x1000
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_12_ALIGN            0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_12_BITS             1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_12_SHIFT            12

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_11 [11:11] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_11_MASK             0x0800
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_11_ALIGN            0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_11_BITS             1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_11_SHIFT            11

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_10 [10:10] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_10_MASK             0x0400
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_10_ALIGN            0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_10_BITS             1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_10_SHIFT            10

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_9 [09:09] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_9_MASK              0x0200
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_9_ALIGN             0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_9_BITS              1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_9_SHIFT             9

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_8 [08:08] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_8_MASK              0x0100
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_8_ALIGN             0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_8_BITS              1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_8_SHIFT             8

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_7 [07:07] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_7_MASK              0x0080
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_7_ALIGN             0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_7_BITS              1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_7_SHIFT             7

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_6 [06:06] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_6_MASK              0x0040
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_6_ALIGN             0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_6_BITS              1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_6_SHIFT             6

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_5 [05:05] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_5_MASK              0x0020
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_5_ALIGN             0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_5_BITS              1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_5_SHIFT             5

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_4 [04:04] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_4_MASK              0x0010
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_4_ALIGN             0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_4_BITS              1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_4_SHIFT             4

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_3 [03:03] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_3_MASK              0x0008
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_3_ALIGN             0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_3_BITS              1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_3_SHIFT             3

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_2 [02:02] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_2_MASK              0x0004
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_2_ALIGN             0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_2_BITS              1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_2_SHIFT             2

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_1 [01:01] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_1_MASK              0x0002
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_1_ALIGN             0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_1_BITS              1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_1_SHIFT             1

/* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_0 [00:00] */
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_0_MASK              0x0001
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_0_ALIGN             0
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_0_BITS              1
#define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_0_SHIFT             0


/****************************************************************************
 * Dsc4b1 :: sm_status9
 ***************************************************************************/
/* Dsc4b1 :: sm_status9 :: reserved_for_eco0 [15:12] */
#define DSC4B1_SM_STATUS9_RESERVED_FOR_ECO0_MASK                   0xf000
#define DSC4B1_SM_STATUS9_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC4B1_SM_STATUS9_RESERVED_FOR_ECO0_BITS                   4
#define DSC4B1_SM_STATUS9_RESERVED_FOR_ECO0_SHIFT                  12

/* Dsc4b1 :: sm_status9 :: tuning_state_one_hot_17 [11:11] */
#define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_17_MASK             0x0800
#define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_17_ALIGN            0
#define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_17_BITS             1
#define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_17_SHIFT            11

/* Dsc4b1 :: sm_status9 :: tuning_state_one_hot_16 [10:10] */
#define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_16_MASK             0x0400
#define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_16_ALIGN            0
#define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_16_BITS             1
#define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_16_SHIFT            10

/* Dsc4b1 :: sm_status9 :: srch_state_one_hot_9 [09:09] */
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_9_MASK                0x0200
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_9_ALIGN               0
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_9_BITS                1
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_9_SHIFT               9

/* Dsc4b1 :: sm_status9 :: srch_state_one_hot_8 [08:08] */
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_8_MASK                0x0100
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_8_ALIGN               0
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_8_BITS                1
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_8_SHIFT               8

/* Dsc4b1 :: sm_status9 :: srch_state_one_hot_7 [07:07] */
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_7_MASK                0x0080
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_7_ALIGN               0
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_7_BITS                1
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_7_SHIFT               7

/* Dsc4b1 :: sm_status9 :: srch_state_one_hot_6 [06:06] */
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_6_MASK                0x0040
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_6_ALIGN               0
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_6_BITS                1
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_6_SHIFT               6

/* Dsc4b1 :: sm_status9 :: srch_state_one_hot_5 [05:05] */
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_5_MASK                0x0020
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_5_ALIGN               0
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_5_BITS                1
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_5_SHIFT               5

/* Dsc4b1 :: sm_status9 :: srch_state_one_hot_4 [04:04] */
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_4_MASK                0x0010
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_4_ALIGN               0
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_4_BITS                1
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_4_SHIFT               4

/* Dsc4b1 :: sm_status9 :: srch_state_one_hot_3 [03:03] */
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_3_MASK                0x0008
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_3_ALIGN               0
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_3_BITS                1
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_3_SHIFT               3

/* Dsc4b1 :: sm_status9 :: srch_state_one_hot_2 [02:02] */
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_2_MASK                0x0004
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_2_ALIGN               0
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_2_BITS                1
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_2_SHIFT               2

/* Dsc4b1 :: sm_status9 :: srch_state_one_hot_1 [01:01] */
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_1_MASK                0x0002
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_1_ALIGN               0
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_1_BITS                1
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_1_SHIFT               1

/* Dsc4b1 :: sm_status9 :: srch_state_one_hot_0 [00:00] */
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_0_MASK                0x0001
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_0_ALIGN               0
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_0_BITS                1
#define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_0_SHIFT               0


/****************************************************************************
 * Hypercore_USER_Dsc4b2
 ***************************************************************************/
/****************************************************************************
 * Dsc4b2 :: sm_ctrl13
 ***************************************************************************/
/* Dsc4b2 :: sm_ctrl13 :: reserved0 [15:15] */
#define DSC4B2_SM_CTRL13_RESERVED0_MASK                            0x8000
#define DSC4B2_SM_CTRL13_RESERVED0_ALIGN                           0
#define DSC4B2_SM_CTRL13_RESERVED0_BITS                            1
#define DSC4B2_SM_CTRL13_RESERVED0_SHIFT                           15

/* Dsc4b2 :: sm_ctrl13 :: br_vga_trn2_timeout [14:10] */
#define DSC4B2_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_MASK                  0x7c00
#define DSC4B2_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_ALIGN                 0
#define DSC4B2_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_BITS                  5
#define DSC4B2_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_SHIFT                 10

/* Dsc4b2 :: sm_ctrl13 :: br_pf_trn2_timeout [09:05] */
#define DSC4B2_SM_CTRL13_BR_PF_TRN2_TIMEOUT_MASK                   0x03e0
#define DSC4B2_SM_CTRL13_BR_PF_TRN2_TIMEOUT_ALIGN                  0
#define DSC4B2_SM_CTRL13_BR_PF_TRN2_TIMEOUT_BITS                   5
#define DSC4B2_SM_CTRL13_BR_PF_TRN2_TIMEOUT_SHIFT                  5

/* Dsc4b2 :: sm_ctrl13 :: br_pf_trn1_timeout [04:00] */
#define DSC4B2_SM_CTRL13_BR_PF_TRN1_TIMEOUT_MASK                   0x001f
#define DSC4B2_SM_CTRL13_BR_PF_TRN1_TIMEOUT_ALIGN                  0
#define DSC4B2_SM_CTRL13_BR_PF_TRN1_TIMEOUT_BITS                   5
#define DSC4B2_SM_CTRL13_BR_PF_TRN1_TIMEOUT_SHIFT                  0


/****************************************************************************
 * Dsc4b2 :: sm_ctrl14
 ***************************************************************************/
/* Dsc4b2 :: sm_ctrl14 :: reserved0 [15:14] */
#define DSC4B2_SM_CTRL14_RESERVED0_MASK                            0xc000
#define DSC4B2_SM_CTRL14_RESERVED0_ALIGN                           0
#define DSC4B2_SM_CTRL14_RESERVED0_BITS                            2
#define DSC4B2_SM_CTRL14_RESERVED0_SHIFT                           14

/* Dsc4b2 :: sm_ctrl14 :: br_postc_tap_en [13:07] */
#define DSC4B2_SM_CTRL14_BR_POSTC_TAP_EN_MASK                      0x3f80
#define DSC4B2_SM_CTRL14_BR_POSTC_TAP_EN_ALIGN                     0
#define DSC4B2_SM_CTRL14_BR_POSTC_TAP_EN_BITS                      7
#define DSC4B2_SM_CTRL14_BR_POSTC_TAP_EN_SHIFT                     7

/* Dsc4b2 :: sm_ctrl14 :: osx2_pf_tap_en [06:00] */
#define DSC4B2_SM_CTRL14_OSX2_PF_TAP_EN_MASK                       0x007f
#define DSC4B2_SM_CTRL14_OSX2_PF_TAP_EN_ALIGN                      0
#define DSC4B2_SM_CTRL14_OSX2_PF_TAP_EN_BITS                       7
#define DSC4B2_SM_CTRL14_OSX2_PF_TAP_EN_SHIFT                      0


/****************************************************************************
 * Dsc4b2 :: sm_ctrl15
 ***************************************************************************/
/* Dsc4b2 :: sm_ctrl15 :: reserved0 [15:14] */
#define DSC4B2_SM_CTRL15_RESERVED0_MASK                            0xc000
#define DSC4B2_SM_CTRL15_RESERVED0_ALIGN                           0
#define DSC4B2_SM_CTRL15_RESERVED0_BITS                            2
#define DSC4B2_SM_CTRL15_RESERVED0_SHIFT                           14

/* Dsc4b2 :: sm_ctrl15 :: osx2_postc_tap_en [13:07] */
#define DSC4B2_SM_CTRL15_OSX2_POSTC_TAP_EN_MASK                    0x3f80
#define DSC4B2_SM_CTRL15_OSX2_POSTC_TAP_EN_ALIGN                   0
#define DSC4B2_SM_CTRL15_OSX2_POSTC_TAP_EN_BITS                    7
#define DSC4B2_SM_CTRL15_OSX2_POSTC_TAP_EN_SHIFT                   7

/* Dsc4b2 :: sm_ctrl15 :: osx1_postc_tap_en [06:00] */
#define DSC4B2_SM_CTRL15_OSX1_POSTC_TAP_EN_MASK                    0x007f
#define DSC4B2_SM_CTRL15_OSX1_POSTC_TAP_EN_ALIGN                   0
#define DSC4B2_SM_CTRL15_OSX1_POSTC_TAP_EN_BITS                    7
#define DSC4B2_SM_CTRL15_OSX1_POSTC_TAP_EN_SHIFT                   0


/****************************************************************************
 * Dsc4b2 :: sm_ctrl16
 ***************************************************************************/
/* Dsc4b2 :: sm_ctrl16 :: reserved0 [15:15] */
#define DSC4B2_SM_CTRL16_RESERVED0_MASK                            0x8000
#define DSC4B2_SM_CTRL16_RESERVED0_ALIGN                           0
#define DSC4B2_SM_CTRL16_RESERVED0_BITS                            1
#define DSC4B2_SM_CTRL16_RESERVED0_SHIFT                           15

/* Dsc4b2 :: sm_ctrl16 :: msr_slicer_slow_timeout [14:10] */
#define DSC4B2_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_MASK              0x7c00
#define DSC4B2_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_ALIGN             0
#define DSC4B2_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_BITS              5
#define DSC4B2_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_SHIFT             10

/* Dsc4b2 :: sm_ctrl16 :: msr_slicer_fast_timeout [09:05] */
#define DSC4B2_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_MASK              0x03e0
#define DSC4B2_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_ALIGN             0
#define DSC4B2_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_BITS              5
#define DSC4B2_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_SHIFT             5

/* Dsc4b2 :: sm_ctrl16 :: default_trn2_timeout [04:00] */
#define DSC4B2_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_MASK                 0x001f
#define DSC4B2_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_ALIGN                0
#define DSC4B2_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_BITS                 5
#define DSC4B2_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_SHIFT                0


/****************************************************************************
 * Dsc4b2 :: sm_ctrl17
 ***************************************************************************/
/* Dsc4b2 :: sm_ctrl17 :: reserved0 [15:02] */
#define DSC4B2_SM_CTRL17_RESERVED0_MASK                            0xfffc
#define DSC4B2_SM_CTRL17_RESERVED0_ALIGN                           0
#define DSC4B2_SM_CTRL17_RESERVED0_BITS                            14
#define DSC4B2_SM_CTRL17_RESERVED0_SHIFT                           2

/* Dsc4b2 :: sm_ctrl17 :: bypass_osx1_slicer_cal [01:01] */
#define DSC4B2_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_MASK               0x0002
#define DSC4B2_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_ALIGN              0
#define DSC4B2_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_BITS               1
#define DSC4B2_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_SHIFT              1

/* Dsc4b2 :: sm_ctrl17 :: bypass_osx2_slicer_cal [00:00] */
#define DSC4B2_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_MASK               0x0001
#define DSC4B2_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_ALIGN              0
#define DSC4B2_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_BITS               1
#define DSC4B2_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_SHIFT              0


/****************************************************************************
 * Dsc4b2 :: sm_status7
 ***************************************************************************/
/* Dsc4b2 :: sm_status7 :: reserved_for_eco0 [15:12] */
#define DSC4B2_SM_STATUS7_RESERVED_FOR_ECO0_MASK                   0xf000
#define DSC4B2_SM_STATUS7_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC4B2_SM_STATUS7_RESERVED_FOR_ECO0_BITS                   4
#define DSC4B2_SM_STATUS7_RESERVED_FOR_ECO0_SHIFT                  12

/* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_11 [11:11] */
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_11_MASK                0x0800
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_11_ALIGN               0
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_11_BITS                1
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_11_SHIFT               11

/* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_10 [10:10] */
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_10_MASK                0x0400
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_10_ALIGN               0
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_10_BITS                1
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_10_SHIFT               10

/* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_9 [09:09] */
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_9_MASK                 0x0200
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_9_ALIGN                0
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_9_BITS                 1
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_9_SHIFT                9

/* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_8 [08:08] */
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_8_MASK                 0x0100
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_8_ALIGN                0
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_8_BITS                 1
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_8_SHIFT                8

/* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_7 [07:07] */
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_7_MASK                 0x0080
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_7_ALIGN                0
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_7_BITS                 1
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_7_SHIFT                7

/* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_6 [06:06] */
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_6_MASK                 0x0040
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_6_ALIGN                0
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_6_BITS                 1
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_6_SHIFT                6

/* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_5 [05:05] */
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_5_MASK                 0x0020
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_5_ALIGN                0
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_5_BITS                 1
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_5_SHIFT                5

/* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_4 [04:04] */
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_4_MASK                 0x0010
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_4_ALIGN                0
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_4_BITS                 1
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_4_SHIFT                4

/* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_3 [03:03] */
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_3_MASK                 0x0008
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_3_ALIGN                0
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_3_BITS                 1
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_3_SHIFT                3

/* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_2 [02:02] */
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_2_MASK                 0x0004
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_2_ALIGN                0
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_2_BITS                 1
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_2_SHIFT                2

/* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_1 [01:01] */
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_1_MASK                 0x0002
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_1_ALIGN                0
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_1_BITS                 1
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_1_SHIFT                1

/* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_0 [00:00] */
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_0_MASK                 0x0001
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_0_ALIGN                0
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_0_BITS                 1
#define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_0_SHIFT                0


/****************************************************************************
 * Dsc4b2 :: sm_status8
 ***************************************************************************/
/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_15 [15:15] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_15_MASK             0x8000
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_15_ALIGN            0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_15_BITS             1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_15_SHIFT            15

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_14 [14:14] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_14_MASK             0x4000
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_14_ALIGN            0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_14_BITS             1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_14_SHIFT            14

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_13 [13:13] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_13_MASK             0x2000
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_13_ALIGN            0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_13_BITS             1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_13_SHIFT            13

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_12 [12:12] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_12_MASK             0x1000
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_12_ALIGN            0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_12_BITS             1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_12_SHIFT            12

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_11 [11:11] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_11_MASK             0x0800
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_11_ALIGN            0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_11_BITS             1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_11_SHIFT            11

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_10 [10:10] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_10_MASK             0x0400
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_10_ALIGN            0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_10_BITS             1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_10_SHIFT            10

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_9 [09:09] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_9_MASK              0x0200
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_9_ALIGN             0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_9_BITS              1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_9_SHIFT             9

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_8 [08:08] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_8_MASK              0x0100
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_8_ALIGN             0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_8_BITS              1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_8_SHIFT             8

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_7 [07:07] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_7_MASK              0x0080
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_7_ALIGN             0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_7_BITS              1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_7_SHIFT             7

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_6 [06:06] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_6_MASK              0x0040
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_6_ALIGN             0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_6_BITS              1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_6_SHIFT             6

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_5 [05:05] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_5_MASK              0x0020
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_5_ALIGN             0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_5_BITS              1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_5_SHIFT             5

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_4 [04:04] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_4_MASK              0x0010
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_4_ALIGN             0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_4_BITS              1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_4_SHIFT             4

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_3 [03:03] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_3_MASK              0x0008
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_3_ALIGN             0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_3_BITS              1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_3_SHIFT             3

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_2 [02:02] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_2_MASK              0x0004
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_2_ALIGN             0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_2_BITS              1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_2_SHIFT             2

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_1 [01:01] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_1_MASK              0x0002
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_1_ALIGN             0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_1_BITS              1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_1_SHIFT             1

/* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_0 [00:00] */
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_0_MASK              0x0001
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_0_ALIGN             0
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_0_BITS              1
#define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_0_SHIFT             0


/****************************************************************************
 * Dsc4b2 :: sm_status9
 ***************************************************************************/
/* Dsc4b2 :: sm_status9 :: reserved_for_eco0 [15:12] */
#define DSC4B2_SM_STATUS9_RESERVED_FOR_ECO0_MASK                   0xf000
#define DSC4B2_SM_STATUS9_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC4B2_SM_STATUS9_RESERVED_FOR_ECO0_BITS                   4
#define DSC4B2_SM_STATUS9_RESERVED_FOR_ECO0_SHIFT                  12

/* Dsc4b2 :: sm_status9 :: tuning_state_one_hot_17 [11:11] */
#define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_17_MASK             0x0800
#define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_17_ALIGN            0
#define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_17_BITS             1
#define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_17_SHIFT            11

/* Dsc4b2 :: sm_status9 :: tuning_state_one_hot_16 [10:10] */
#define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_16_MASK             0x0400
#define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_16_ALIGN            0
#define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_16_BITS             1
#define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_16_SHIFT            10

/* Dsc4b2 :: sm_status9 :: srch_state_one_hot_9 [09:09] */
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_9_MASK                0x0200
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_9_ALIGN               0
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_9_BITS                1
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_9_SHIFT               9

/* Dsc4b2 :: sm_status9 :: srch_state_one_hot_8 [08:08] */
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_8_MASK                0x0100
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_8_ALIGN               0
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_8_BITS                1
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_8_SHIFT               8

/* Dsc4b2 :: sm_status9 :: srch_state_one_hot_7 [07:07] */
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_7_MASK                0x0080
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_7_ALIGN               0
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_7_BITS                1
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_7_SHIFT               7

/* Dsc4b2 :: sm_status9 :: srch_state_one_hot_6 [06:06] */
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_6_MASK                0x0040
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_6_ALIGN               0
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_6_BITS                1
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_6_SHIFT               6

/* Dsc4b2 :: sm_status9 :: srch_state_one_hot_5 [05:05] */
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_5_MASK                0x0020
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_5_ALIGN               0
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_5_BITS                1
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_5_SHIFT               5

/* Dsc4b2 :: sm_status9 :: srch_state_one_hot_4 [04:04] */
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_4_MASK                0x0010
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_4_ALIGN               0
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_4_BITS                1
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_4_SHIFT               4

/* Dsc4b2 :: sm_status9 :: srch_state_one_hot_3 [03:03] */
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_3_MASK                0x0008
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_3_ALIGN               0
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_3_BITS                1
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_3_SHIFT               3

/* Dsc4b2 :: sm_status9 :: srch_state_one_hot_2 [02:02] */
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_2_MASK                0x0004
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_2_ALIGN               0
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_2_BITS                1
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_2_SHIFT               2

/* Dsc4b2 :: sm_status9 :: srch_state_one_hot_1 [01:01] */
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_1_MASK                0x0002
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_1_ALIGN               0
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_1_BITS                1
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_1_SHIFT               1

/* Dsc4b2 :: sm_status9 :: srch_state_one_hot_0 [00:00] */
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_0_MASK                0x0001
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_0_ALIGN               0
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_0_BITS                1
#define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_0_SHIFT               0


/****************************************************************************
 * Hypercore_USER_Dsc4b3
 ***************************************************************************/
/****************************************************************************
 * Dsc4b3 :: sm_ctrl13
 ***************************************************************************/
/* Dsc4b3 :: sm_ctrl13 :: reserved0 [15:15] */
#define DSC4B3_SM_CTRL13_RESERVED0_MASK                            0x8000
#define DSC4B3_SM_CTRL13_RESERVED0_ALIGN                           0
#define DSC4B3_SM_CTRL13_RESERVED0_BITS                            1
#define DSC4B3_SM_CTRL13_RESERVED0_SHIFT                           15

/* Dsc4b3 :: sm_ctrl13 :: br_vga_trn2_timeout [14:10] */
#define DSC4B3_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_MASK                  0x7c00
#define DSC4B3_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_ALIGN                 0
#define DSC4B3_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_BITS                  5
#define DSC4B3_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_SHIFT                 10

/* Dsc4b3 :: sm_ctrl13 :: br_pf_trn2_timeout [09:05] */
#define DSC4B3_SM_CTRL13_BR_PF_TRN2_TIMEOUT_MASK                   0x03e0
#define DSC4B3_SM_CTRL13_BR_PF_TRN2_TIMEOUT_ALIGN                  0
#define DSC4B3_SM_CTRL13_BR_PF_TRN2_TIMEOUT_BITS                   5
#define DSC4B3_SM_CTRL13_BR_PF_TRN2_TIMEOUT_SHIFT                  5

/* Dsc4b3 :: sm_ctrl13 :: br_pf_trn1_timeout [04:00] */
#define DSC4B3_SM_CTRL13_BR_PF_TRN1_TIMEOUT_MASK                   0x001f
#define DSC4B3_SM_CTRL13_BR_PF_TRN1_TIMEOUT_ALIGN                  0
#define DSC4B3_SM_CTRL13_BR_PF_TRN1_TIMEOUT_BITS                   5
#define DSC4B3_SM_CTRL13_BR_PF_TRN1_TIMEOUT_SHIFT                  0


/****************************************************************************
 * Dsc4b3 :: sm_ctrl14
 ***************************************************************************/
/* Dsc4b3 :: sm_ctrl14 :: reserved0 [15:14] */
#define DSC4B3_SM_CTRL14_RESERVED0_MASK                            0xc000
#define DSC4B3_SM_CTRL14_RESERVED0_ALIGN                           0
#define DSC4B3_SM_CTRL14_RESERVED0_BITS                            2
#define DSC4B3_SM_CTRL14_RESERVED0_SHIFT                           14

/* Dsc4b3 :: sm_ctrl14 :: br_postc_tap_en [13:07] */
#define DSC4B3_SM_CTRL14_BR_POSTC_TAP_EN_MASK                      0x3f80
#define DSC4B3_SM_CTRL14_BR_POSTC_TAP_EN_ALIGN                     0
#define DSC4B3_SM_CTRL14_BR_POSTC_TAP_EN_BITS                      7
#define DSC4B3_SM_CTRL14_BR_POSTC_TAP_EN_SHIFT                     7

/* Dsc4b3 :: sm_ctrl14 :: osx2_pf_tap_en [06:00] */
#define DSC4B3_SM_CTRL14_OSX2_PF_TAP_EN_MASK                       0x007f
#define DSC4B3_SM_CTRL14_OSX2_PF_TAP_EN_ALIGN                      0
#define DSC4B3_SM_CTRL14_OSX2_PF_TAP_EN_BITS                       7
#define DSC4B3_SM_CTRL14_OSX2_PF_TAP_EN_SHIFT                      0


/****************************************************************************
 * Dsc4b3 :: sm_ctrl15
 ***************************************************************************/
/* Dsc4b3 :: sm_ctrl15 :: reserved0 [15:14] */
#define DSC4B3_SM_CTRL15_RESERVED0_MASK                            0xc000
#define DSC4B3_SM_CTRL15_RESERVED0_ALIGN                           0
#define DSC4B3_SM_CTRL15_RESERVED0_BITS                            2
#define DSC4B3_SM_CTRL15_RESERVED0_SHIFT                           14

/* Dsc4b3 :: sm_ctrl15 :: osx2_postc_tap_en [13:07] */
#define DSC4B3_SM_CTRL15_OSX2_POSTC_TAP_EN_MASK                    0x3f80
#define DSC4B3_SM_CTRL15_OSX2_POSTC_TAP_EN_ALIGN                   0
#define DSC4B3_SM_CTRL15_OSX2_POSTC_TAP_EN_BITS                    7
#define DSC4B3_SM_CTRL15_OSX2_POSTC_TAP_EN_SHIFT                   7

/* Dsc4b3 :: sm_ctrl15 :: osx1_postc_tap_en [06:00] */
#define DSC4B3_SM_CTRL15_OSX1_POSTC_TAP_EN_MASK                    0x007f
#define DSC4B3_SM_CTRL15_OSX1_POSTC_TAP_EN_ALIGN                   0
#define DSC4B3_SM_CTRL15_OSX1_POSTC_TAP_EN_BITS                    7
#define DSC4B3_SM_CTRL15_OSX1_POSTC_TAP_EN_SHIFT                   0


/****************************************************************************
 * Dsc4b3 :: sm_ctrl16
 ***************************************************************************/
/* Dsc4b3 :: sm_ctrl16 :: reserved0 [15:15] */
#define DSC4B3_SM_CTRL16_RESERVED0_MASK                            0x8000
#define DSC4B3_SM_CTRL16_RESERVED0_ALIGN                           0
#define DSC4B3_SM_CTRL16_RESERVED0_BITS                            1
#define DSC4B3_SM_CTRL16_RESERVED0_SHIFT                           15

/* Dsc4b3 :: sm_ctrl16 :: msr_slicer_slow_timeout [14:10] */
#define DSC4B3_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_MASK              0x7c00
#define DSC4B3_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_ALIGN             0
#define DSC4B3_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_BITS              5
#define DSC4B3_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_SHIFT             10

/* Dsc4b3 :: sm_ctrl16 :: msr_slicer_fast_timeout [09:05] */
#define DSC4B3_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_MASK              0x03e0
#define DSC4B3_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_ALIGN             0
#define DSC4B3_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_BITS              5
#define DSC4B3_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_SHIFT             5

/* Dsc4b3 :: sm_ctrl16 :: default_trn2_timeout [04:00] */
#define DSC4B3_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_MASK                 0x001f
#define DSC4B3_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_ALIGN                0
#define DSC4B3_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_BITS                 5
#define DSC4B3_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_SHIFT                0


/****************************************************************************
 * Dsc4b3 :: sm_ctrl17
 ***************************************************************************/
/* Dsc4b3 :: sm_ctrl17 :: reserved0 [15:02] */
#define DSC4B3_SM_CTRL17_RESERVED0_MASK                            0xfffc
#define DSC4B3_SM_CTRL17_RESERVED0_ALIGN                           0
#define DSC4B3_SM_CTRL17_RESERVED0_BITS                            14
#define DSC4B3_SM_CTRL17_RESERVED0_SHIFT                           2

/* Dsc4b3 :: sm_ctrl17 :: bypass_osx1_slicer_cal [01:01] */
#define DSC4B3_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_MASK               0x0002
#define DSC4B3_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_ALIGN              0
#define DSC4B3_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_BITS               1
#define DSC4B3_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_SHIFT              1

/* Dsc4b3 :: sm_ctrl17 :: bypass_osx2_slicer_cal [00:00] */
#define DSC4B3_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_MASK               0x0001
#define DSC4B3_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_ALIGN              0
#define DSC4B3_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_BITS               1
#define DSC4B3_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_SHIFT              0


/****************************************************************************
 * Dsc4b3 :: sm_status7
 ***************************************************************************/
/* Dsc4b3 :: sm_status7 :: reserved_for_eco0 [15:12] */
#define DSC4B3_SM_STATUS7_RESERVED_FOR_ECO0_MASK                   0xf000
#define DSC4B3_SM_STATUS7_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC4B3_SM_STATUS7_RESERVED_FOR_ECO0_BITS                   4
#define DSC4B3_SM_STATUS7_RESERVED_FOR_ECO0_SHIFT                  12

/* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_11 [11:11] */
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_11_MASK                0x0800
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_11_ALIGN               0
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_11_BITS                1
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_11_SHIFT               11

/* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_10 [10:10] */
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_10_MASK                0x0400
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_10_ALIGN               0
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_10_BITS                1
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_10_SHIFT               10

/* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_9 [09:09] */
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_9_MASK                 0x0200
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_9_ALIGN                0
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_9_BITS                 1
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_9_SHIFT                9

/* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_8 [08:08] */
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_8_MASK                 0x0100
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_8_ALIGN                0
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_8_BITS                 1
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_8_SHIFT                8

/* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_7 [07:07] */
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_7_MASK                 0x0080
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_7_ALIGN                0
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_7_BITS                 1
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_7_SHIFT                7

/* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_6 [06:06] */
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_6_MASK                 0x0040
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_6_ALIGN                0
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_6_BITS                 1
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_6_SHIFT                6

/* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_5 [05:05] */
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_5_MASK                 0x0020
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_5_ALIGN                0
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_5_BITS                 1
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_5_SHIFT                5

/* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_4 [04:04] */
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_4_MASK                 0x0010
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_4_ALIGN                0
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_4_BITS                 1
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_4_SHIFT                4

/* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_3 [03:03] */
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_3_MASK                 0x0008
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_3_ALIGN                0
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_3_BITS                 1
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_3_SHIFT                3

/* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_2 [02:02] */
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_2_MASK                 0x0004
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_2_ALIGN                0
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_2_BITS                 1
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_2_SHIFT                2

/* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_1 [01:01] */
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_1_MASK                 0x0002
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_1_ALIGN                0
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_1_BITS                 1
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_1_SHIFT                1

/* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_0 [00:00] */
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_0_MASK                 0x0001
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_0_ALIGN                0
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_0_BITS                 1
#define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_0_SHIFT                0


/****************************************************************************
 * Dsc4b3 :: sm_status8
 ***************************************************************************/
/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_15 [15:15] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_15_MASK             0x8000
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_15_ALIGN            0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_15_BITS             1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_15_SHIFT            15

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_14 [14:14] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_14_MASK             0x4000
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_14_ALIGN            0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_14_BITS             1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_14_SHIFT            14

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_13 [13:13] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_13_MASK             0x2000
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_13_ALIGN            0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_13_BITS             1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_13_SHIFT            13

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_12 [12:12] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_12_MASK             0x1000
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_12_ALIGN            0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_12_BITS             1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_12_SHIFT            12

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_11 [11:11] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_11_MASK             0x0800
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_11_ALIGN            0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_11_BITS             1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_11_SHIFT            11

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_10 [10:10] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_10_MASK             0x0400
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_10_ALIGN            0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_10_BITS             1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_10_SHIFT            10

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_9 [09:09] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_9_MASK              0x0200
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_9_ALIGN             0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_9_BITS              1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_9_SHIFT             9

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_8 [08:08] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_8_MASK              0x0100
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_8_ALIGN             0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_8_BITS              1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_8_SHIFT             8

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_7 [07:07] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_7_MASK              0x0080
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_7_ALIGN             0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_7_BITS              1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_7_SHIFT             7

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_6 [06:06] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_6_MASK              0x0040
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_6_ALIGN             0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_6_BITS              1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_6_SHIFT             6

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_5 [05:05] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_5_MASK              0x0020
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_5_ALIGN             0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_5_BITS              1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_5_SHIFT             5

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_4 [04:04] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_4_MASK              0x0010
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_4_ALIGN             0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_4_BITS              1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_4_SHIFT             4

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_3 [03:03] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_3_MASK              0x0008
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_3_ALIGN             0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_3_BITS              1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_3_SHIFT             3

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_2 [02:02] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_2_MASK              0x0004
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_2_ALIGN             0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_2_BITS              1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_2_SHIFT             2

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_1 [01:01] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_1_MASK              0x0002
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_1_ALIGN             0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_1_BITS              1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_1_SHIFT             1

/* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_0 [00:00] */
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_0_MASK              0x0001
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_0_ALIGN             0
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_0_BITS              1
#define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_0_SHIFT             0


/****************************************************************************
 * Dsc4b3 :: sm_status9
 ***************************************************************************/
/* Dsc4b3 :: sm_status9 :: reserved_for_eco0 [15:12] */
#define DSC4B3_SM_STATUS9_RESERVED_FOR_ECO0_MASK                   0xf000
#define DSC4B3_SM_STATUS9_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC4B3_SM_STATUS9_RESERVED_FOR_ECO0_BITS                   4
#define DSC4B3_SM_STATUS9_RESERVED_FOR_ECO0_SHIFT                  12

/* Dsc4b3 :: sm_status9 :: tuning_state_one_hot_17 [11:11] */
#define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_17_MASK             0x0800
#define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_17_ALIGN            0
#define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_17_BITS             1
#define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_17_SHIFT            11

/* Dsc4b3 :: sm_status9 :: tuning_state_one_hot_16 [10:10] */
#define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_16_MASK             0x0400
#define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_16_ALIGN            0
#define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_16_BITS             1
#define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_16_SHIFT            10

/* Dsc4b3 :: sm_status9 :: srch_state_one_hot_9 [09:09] */
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_9_MASK                0x0200
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_9_ALIGN               0
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_9_BITS                1
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_9_SHIFT               9

/* Dsc4b3 :: sm_status9 :: srch_state_one_hot_8 [08:08] */
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_8_MASK                0x0100
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_8_ALIGN               0
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_8_BITS                1
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_8_SHIFT               8

/* Dsc4b3 :: sm_status9 :: srch_state_one_hot_7 [07:07] */
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_7_MASK                0x0080
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_7_ALIGN               0
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_7_BITS                1
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_7_SHIFT               7

/* Dsc4b3 :: sm_status9 :: srch_state_one_hot_6 [06:06] */
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_6_MASK                0x0040
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_6_ALIGN               0
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_6_BITS                1
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_6_SHIFT               6

/* Dsc4b3 :: sm_status9 :: srch_state_one_hot_5 [05:05] */
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_5_MASK                0x0020
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_5_ALIGN               0
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_5_BITS                1
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_5_SHIFT               5

/* Dsc4b3 :: sm_status9 :: srch_state_one_hot_4 [04:04] */
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_4_MASK                0x0010
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_4_ALIGN               0
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_4_BITS                1
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_4_SHIFT               4

/* Dsc4b3 :: sm_status9 :: srch_state_one_hot_3 [03:03] */
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_3_MASK                0x0008
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_3_ALIGN               0
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_3_BITS                1
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_3_SHIFT               3

/* Dsc4b3 :: sm_status9 :: srch_state_one_hot_2 [02:02] */
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_2_MASK                0x0004
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_2_ALIGN               0
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_2_BITS                1
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_2_SHIFT               2

/* Dsc4b3 :: sm_status9 :: srch_state_one_hot_1 [01:01] */
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_1_MASK                0x0002
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_1_ALIGN               0
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_1_BITS                1
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_1_SHIFT               1

/* Dsc4b3 :: sm_status9 :: srch_state_one_hot_0 [00:00] */
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_0_MASK                0x0001
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_0_ALIGN               0
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_0_BITS                1
#define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_0_SHIFT               0


/****************************************************************************
 * Hypercore_USER_Dsc4bB
 ***************************************************************************/
/****************************************************************************
 * Dsc4bB :: sm_ctrl13
 ***************************************************************************/
/* Dsc4bB :: sm_ctrl13 :: reserved0 [15:15] */
#define DSC4BB_SM_CTRL13_RESERVED0_MASK                            0x8000
#define DSC4BB_SM_CTRL13_RESERVED0_ALIGN                           0
#define DSC4BB_SM_CTRL13_RESERVED0_BITS                            1
#define DSC4BB_SM_CTRL13_RESERVED0_SHIFT                           15

/* Dsc4bB :: sm_ctrl13 :: br_vga_trn2_timeout [14:10] */
#define DSC4BB_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_MASK                  0x7c00
#define DSC4BB_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_ALIGN                 0
#define DSC4BB_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_BITS                  5
#define DSC4BB_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_SHIFT                 10

/* Dsc4bB :: sm_ctrl13 :: br_pf_trn2_timeout [09:05] */
#define DSC4BB_SM_CTRL13_BR_PF_TRN2_TIMEOUT_MASK                   0x03e0
#define DSC4BB_SM_CTRL13_BR_PF_TRN2_TIMEOUT_ALIGN                  0
#define DSC4BB_SM_CTRL13_BR_PF_TRN2_TIMEOUT_BITS                   5
#define DSC4BB_SM_CTRL13_BR_PF_TRN2_TIMEOUT_SHIFT                  5

/* Dsc4bB :: sm_ctrl13 :: br_pf_trn1_timeout [04:00] */
#define DSC4BB_SM_CTRL13_BR_PF_TRN1_TIMEOUT_MASK                   0x001f
#define DSC4BB_SM_CTRL13_BR_PF_TRN1_TIMEOUT_ALIGN                  0
#define DSC4BB_SM_CTRL13_BR_PF_TRN1_TIMEOUT_BITS                   5
#define DSC4BB_SM_CTRL13_BR_PF_TRN1_TIMEOUT_SHIFT                  0


/****************************************************************************
 * Dsc4bB :: sm_ctrl14
 ***************************************************************************/
/* Dsc4bB :: sm_ctrl14 :: reserved0 [15:14] */
#define DSC4BB_SM_CTRL14_RESERVED0_MASK                            0xc000
#define DSC4BB_SM_CTRL14_RESERVED0_ALIGN                           0
#define DSC4BB_SM_CTRL14_RESERVED0_BITS                            2
#define DSC4BB_SM_CTRL14_RESERVED0_SHIFT                           14

/* Dsc4bB :: sm_ctrl14 :: br_postc_tap_en [13:07] */
#define DSC4BB_SM_CTRL14_BR_POSTC_TAP_EN_MASK                      0x3f80
#define DSC4BB_SM_CTRL14_BR_POSTC_TAP_EN_ALIGN                     0
#define DSC4BB_SM_CTRL14_BR_POSTC_TAP_EN_BITS                      7
#define DSC4BB_SM_CTRL14_BR_POSTC_TAP_EN_SHIFT                     7

/* Dsc4bB :: sm_ctrl14 :: osx2_pf_tap_en [06:00] */
#define DSC4BB_SM_CTRL14_OSX2_PF_TAP_EN_MASK                       0x007f
#define DSC4BB_SM_CTRL14_OSX2_PF_TAP_EN_ALIGN                      0
#define DSC4BB_SM_CTRL14_OSX2_PF_TAP_EN_BITS                       7
#define DSC4BB_SM_CTRL14_OSX2_PF_TAP_EN_SHIFT                      0


/****************************************************************************
 * Dsc4bB :: sm_ctrl15
 ***************************************************************************/
/* Dsc4bB :: sm_ctrl15 :: reserved0 [15:14] */
#define DSC4BB_SM_CTRL15_RESERVED0_MASK                            0xc000
#define DSC4BB_SM_CTRL15_RESERVED0_ALIGN                           0
#define DSC4BB_SM_CTRL15_RESERVED0_BITS                            2
#define DSC4BB_SM_CTRL15_RESERVED0_SHIFT                           14

/* Dsc4bB :: sm_ctrl15 :: osx2_postc_tap_en [13:07] */
#define DSC4BB_SM_CTRL15_OSX2_POSTC_TAP_EN_MASK                    0x3f80
#define DSC4BB_SM_CTRL15_OSX2_POSTC_TAP_EN_ALIGN                   0
#define DSC4BB_SM_CTRL15_OSX2_POSTC_TAP_EN_BITS                    7
#define DSC4BB_SM_CTRL15_OSX2_POSTC_TAP_EN_SHIFT                   7

/* Dsc4bB :: sm_ctrl15 :: osx1_postc_tap_en [06:00] */
#define DSC4BB_SM_CTRL15_OSX1_POSTC_TAP_EN_MASK                    0x007f
#define DSC4BB_SM_CTRL15_OSX1_POSTC_TAP_EN_ALIGN                   0
#define DSC4BB_SM_CTRL15_OSX1_POSTC_TAP_EN_BITS                    7
#define DSC4BB_SM_CTRL15_OSX1_POSTC_TAP_EN_SHIFT                   0


/****************************************************************************
 * Dsc4bB :: sm_ctrl16
 ***************************************************************************/
/* Dsc4bB :: sm_ctrl16 :: reserved0 [15:15] */
#define DSC4BB_SM_CTRL16_RESERVED0_MASK                            0x8000
#define DSC4BB_SM_CTRL16_RESERVED0_ALIGN                           0
#define DSC4BB_SM_CTRL16_RESERVED0_BITS                            1
#define DSC4BB_SM_CTRL16_RESERVED0_SHIFT                           15

/* Dsc4bB :: sm_ctrl16 :: msr_slicer_slow_timeout [14:10] */
#define DSC4BB_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_MASK              0x7c00
#define DSC4BB_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_ALIGN             0
#define DSC4BB_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_BITS              5
#define DSC4BB_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_SHIFT             10

/* Dsc4bB :: sm_ctrl16 :: msr_slicer_fast_timeout [09:05] */
#define DSC4BB_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_MASK              0x03e0
#define DSC4BB_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_ALIGN             0
#define DSC4BB_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_BITS              5
#define DSC4BB_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_SHIFT             5

/* Dsc4bB :: sm_ctrl16 :: default_trn2_timeout [04:00] */
#define DSC4BB_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_MASK                 0x001f
#define DSC4BB_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_ALIGN                0
#define DSC4BB_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_BITS                 5
#define DSC4BB_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_SHIFT                0


/****************************************************************************
 * Dsc4bB :: sm_ctrl17
 ***************************************************************************/
/* Dsc4bB :: sm_ctrl17 :: reserved0 [15:02] */
#define DSC4BB_SM_CTRL17_RESERVED0_MASK                            0xfffc
#define DSC4BB_SM_CTRL17_RESERVED0_ALIGN                           0
#define DSC4BB_SM_CTRL17_RESERVED0_BITS                            14
#define DSC4BB_SM_CTRL17_RESERVED0_SHIFT                           2

/* Dsc4bB :: sm_ctrl17 :: bypass_osx1_slicer_cal [01:01] */
#define DSC4BB_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_MASK               0x0002
#define DSC4BB_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_ALIGN              0
#define DSC4BB_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_BITS               1
#define DSC4BB_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_SHIFT              1

/* Dsc4bB :: sm_ctrl17 :: bypass_osx2_slicer_cal [00:00] */
#define DSC4BB_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_MASK               0x0001
#define DSC4BB_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_ALIGN              0
#define DSC4BB_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_BITS               1
#define DSC4BB_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_SHIFT              0


/****************************************************************************
 * Dsc4bB :: sm_status7
 ***************************************************************************/
/* Dsc4bB :: sm_status7 :: reserved_for_eco0 [15:12] */
#define DSC4BB_SM_STATUS7_RESERVED_FOR_ECO0_MASK                   0xf000
#define DSC4BB_SM_STATUS7_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC4BB_SM_STATUS7_RESERVED_FOR_ECO0_BITS                   4
#define DSC4BB_SM_STATUS7_RESERVED_FOR_ECO0_SHIFT                  12

/* Dsc4bB :: sm_status7 :: dsc_state_one_hot_11 [11:11] */
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_11_MASK                0x0800
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_11_ALIGN               0
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_11_BITS                1
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_11_SHIFT               11

/* Dsc4bB :: sm_status7 :: dsc_state_one_hot_10 [10:10] */
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_10_MASK                0x0400
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_10_ALIGN               0
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_10_BITS                1
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_10_SHIFT               10

/* Dsc4bB :: sm_status7 :: dsc_state_one_hot_9 [09:09] */
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_9_MASK                 0x0200
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_9_ALIGN                0
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_9_BITS                 1
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_9_SHIFT                9

/* Dsc4bB :: sm_status7 :: dsc_state_one_hot_8 [08:08] */
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_8_MASK                 0x0100
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_8_ALIGN                0
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_8_BITS                 1
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_8_SHIFT                8

/* Dsc4bB :: sm_status7 :: dsc_state_one_hot_7 [07:07] */
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_7_MASK                 0x0080
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_7_ALIGN                0
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_7_BITS                 1
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_7_SHIFT                7

/* Dsc4bB :: sm_status7 :: dsc_state_one_hot_6 [06:06] */
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_6_MASK                 0x0040
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_6_ALIGN                0
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_6_BITS                 1
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_6_SHIFT                6

/* Dsc4bB :: sm_status7 :: dsc_state_one_hot_5 [05:05] */
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_5_MASK                 0x0020
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_5_ALIGN                0
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_5_BITS                 1
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_5_SHIFT                5

/* Dsc4bB :: sm_status7 :: dsc_state_one_hot_4 [04:04] */
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_4_MASK                 0x0010
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_4_ALIGN                0
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_4_BITS                 1
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_4_SHIFT                4

/* Dsc4bB :: sm_status7 :: dsc_state_one_hot_3 [03:03] */
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_3_MASK                 0x0008
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_3_ALIGN                0
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_3_BITS                 1
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_3_SHIFT                3

/* Dsc4bB :: sm_status7 :: dsc_state_one_hot_2 [02:02] */
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_2_MASK                 0x0004
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_2_ALIGN                0
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_2_BITS                 1
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_2_SHIFT                2

/* Dsc4bB :: sm_status7 :: dsc_state_one_hot_1 [01:01] */
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_1_MASK                 0x0002
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_1_ALIGN                0
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_1_BITS                 1
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_1_SHIFT                1

/* Dsc4bB :: sm_status7 :: dsc_state_one_hot_0 [00:00] */
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_0_MASK                 0x0001
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_0_ALIGN                0
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_0_BITS                 1
#define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_0_SHIFT                0


/****************************************************************************
 * Dsc4bB :: sm_status8
 ***************************************************************************/
/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_15 [15:15] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_15_MASK             0x8000
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_15_ALIGN            0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_15_BITS             1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_15_SHIFT            15

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_14 [14:14] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_14_MASK             0x4000
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_14_ALIGN            0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_14_BITS             1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_14_SHIFT            14

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_13 [13:13] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_13_MASK             0x2000
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_13_ALIGN            0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_13_BITS             1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_13_SHIFT            13

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_12 [12:12] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_12_MASK             0x1000
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_12_ALIGN            0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_12_BITS             1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_12_SHIFT            12

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_11 [11:11] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_11_MASK             0x0800
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_11_ALIGN            0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_11_BITS             1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_11_SHIFT            11

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_10 [10:10] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_10_MASK             0x0400
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_10_ALIGN            0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_10_BITS             1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_10_SHIFT            10

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_9 [09:09] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_9_MASK              0x0200
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_9_ALIGN             0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_9_BITS              1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_9_SHIFT             9

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_8 [08:08] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_8_MASK              0x0100
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_8_ALIGN             0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_8_BITS              1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_8_SHIFT             8

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_7 [07:07] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_7_MASK              0x0080
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_7_ALIGN             0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_7_BITS              1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_7_SHIFT             7

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_6 [06:06] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_6_MASK              0x0040
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_6_ALIGN             0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_6_BITS              1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_6_SHIFT             6

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_5 [05:05] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_5_MASK              0x0020
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_5_ALIGN             0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_5_BITS              1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_5_SHIFT             5

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_4 [04:04] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_4_MASK              0x0010
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_4_ALIGN             0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_4_BITS              1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_4_SHIFT             4

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_3 [03:03] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_3_MASK              0x0008
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_3_ALIGN             0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_3_BITS              1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_3_SHIFT             3

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_2 [02:02] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_2_MASK              0x0004
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_2_ALIGN             0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_2_BITS              1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_2_SHIFT             2

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_1 [01:01] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_1_MASK              0x0002
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_1_ALIGN             0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_1_BITS              1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_1_SHIFT             1

/* Dsc4bB :: sm_status8 :: tuning_state_one_hot_0 [00:00] */
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_0_MASK              0x0001
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_0_ALIGN             0
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_0_BITS              1
#define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_0_SHIFT             0


/****************************************************************************
 * Dsc4bB :: sm_status9
 ***************************************************************************/
/* Dsc4bB :: sm_status9 :: reserved_for_eco0 [15:12] */
#define DSC4BB_SM_STATUS9_RESERVED_FOR_ECO0_MASK                   0xf000
#define DSC4BB_SM_STATUS9_RESERVED_FOR_ECO0_ALIGN                  0
#define DSC4BB_SM_STATUS9_RESERVED_FOR_ECO0_BITS                   4
#define DSC4BB_SM_STATUS9_RESERVED_FOR_ECO0_SHIFT                  12

/* Dsc4bB :: sm_status9 :: tuning_state_one_hot_17 [11:11] */
#define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_17_MASK             0x0800
#define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_17_ALIGN            0
#define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_17_BITS             1
#define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_17_SHIFT            11

/* Dsc4bB :: sm_status9 :: tuning_state_one_hot_16 [10:10] */
#define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_16_MASK             0x0400
#define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_16_ALIGN            0
#define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_16_BITS             1
#define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_16_SHIFT            10

/* Dsc4bB :: sm_status9 :: srch_state_one_hot_9 [09:09] */
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_9_MASK                0x0200
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_9_ALIGN               0
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_9_BITS                1
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_9_SHIFT               9

/* Dsc4bB :: sm_status9 :: srch_state_one_hot_8 [08:08] */
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_8_MASK                0x0100
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_8_ALIGN               0
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_8_BITS                1
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_8_SHIFT               8

/* Dsc4bB :: sm_status9 :: srch_state_one_hot_7 [07:07] */
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_7_MASK                0x0080
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_7_ALIGN               0
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_7_BITS                1
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_7_SHIFT               7

/* Dsc4bB :: sm_status9 :: srch_state_one_hot_6 [06:06] */
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_6_MASK                0x0040
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_6_ALIGN               0
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_6_BITS                1
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_6_SHIFT               6

/* Dsc4bB :: sm_status9 :: srch_state_one_hot_5 [05:05] */
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_5_MASK                0x0020
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_5_ALIGN               0
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_5_BITS                1
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_5_SHIFT               5

/* Dsc4bB :: sm_status9 :: srch_state_one_hot_4 [04:04] */
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_4_MASK                0x0010
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_4_ALIGN               0
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_4_BITS                1
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_4_SHIFT               4

/* Dsc4bB :: sm_status9 :: srch_state_one_hot_3 [03:03] */
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_3_MASK                0x0008
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_3_ALIGN               0
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_3_BITS                1
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_3_SHIFT               3

/* Dsc4bB :: sm_status9 :: srch_state_one_hot_2 [02:02] */
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_2_MASK                0x0004
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_2_ALIGN               0
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_2_BITS                1
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_2_SHIFT               2

/* Dsc4bB :: sm_status9 :: srch_state_one_hot_1 [01:01] */
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_1_MASK                0x0002
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_1_ALIGN               0
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_1_BITS                1
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_1_SHIFT               1

/* Dsc4bB :: sm_status9 :: srch_state_one_hot_0 [00:00] */
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_0_MASK                0x0001
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_0_ALIGN               0
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_0_BITS                1
#define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_0_SHIFT               0


/****************************************************************************
 * Hypercore_USER_FX100
 ***************************************************************************/
/****************************************************************************
 * FX100 :: Control1
 ***************************************************************************/
/* FX100 :: Control1 :: data_sampler_en [15:15] */
#define FX100_CONTROL1_DATA_SAMPLER_EN_MASK                        0x8000
#define FX100_CONTROL1_DATA_SAMPLER_EN_ALIGN                       0
#define FX100_CONTROL1_DATA_SAMPLER_EN_BITS                        1
#define FX100_CONTROL1_DATA_SAMPLER_EN_SHIFT                       15

/* FX100 :: Control1 :: fiber_autopwrdwn_wakeup [14:14] */
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_MASK                0x4000
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_ALIGN               0
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_BITS                1
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_SHIFT               14

/* FX100 :: Control1 :: fiber_autopwrdwn_sleep [13:13] */
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_MASK                 0x2000
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_ALIGN                0
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_BITS                 1
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_SHIFT                13

/* FX100 :: Control1 :: fiberautopwrdwn_en [12:12] */
#define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_MASK                     0x1000
#define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_ALIGN                    0
#define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_BITS                     1
#define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_SHIFT                    12

/* FX100 :: Control1 :: fiber_autopwrdwn_dis [11:11] */
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_MASK                   0x0800
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_ALIGN                  0
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_BITS                   1
#define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_SHIFT                  11

/* FX100 :: Control1 :: autodet_timer_sel [10:10] */
#define FX100_CONTROL1_AUTODET_TIMER_SEL_MASK                      0x0400
#define FX100_CONTROL1_AUTODET_TIMER_SEL_ALIGN                     0
#define FX100_CONTROL1_AUTODET_TIMER_SEL_BITS                      1
#define FX100_CONTROL1_AUTODET_TIMER_SEL_SHIFT                     10

/* FX100 :: Control1 :: rxdata_sel [09:06] */
#define FX100_CONTROL1_RXDATA_SEL_MASK                             0x03c0
#define FX100_CONTROL1_RXDATA_SEL_ALIGN                            0
#define FX100_CONTROL1_RXDATA_SEL_BITS                             4
#define FX100_CONTROL1_RXDATA_SEL_SHIFT                            6

/* FX100 :: Control1 :: disable_rx_qual [05:05] */
#define FX100_CONTROL1_DISABLE_RX_QUAL_MASK                        0x0020
#define FX100_CONTROL1_DISABLE_RX_QUAL_ALIGN                       0
#define FX100_CONTROL1_DISABLE_RX_QUAL_BITS                        1
#define FX100_CONTROL1_DISABLE_RX_QUAL_SHIFT                       5

/* FX100 :: Control1 :: force_rx_qual [04:04] */
#define FX100_CONTROL1_FORCE_RX_QUAL_MASK                          0x0010
#define FX100_CONTROL1_FORCE_RX_QUAL_ALIGN                         0
#define FX100_CONTROL1_FORCE_RX_QUAL_BITS                          1
#define FX100_CONTROL1_FORCE_RX_QUAL_SHIFT                         4

/* FX100 :: Control1 :: far_end_fault_en [03:03] */
#define FX100_CONTROL1_FAR_END_FAULT_EN_MASK                       0x0008
#define FX100_CONTROL1_FAR_END_FAULT_EN_ALIGN                      0
#define FX100_CONTROL1_FAR_END_FAULT_EN_BITS                       1
#define FX100_CONTROL1_FAR_END_FAULT_EN_SHIFT                      3

/* FX100 :: Control1 :: autodet_en [02:02] */
#define FX100_CONTROL1_AUTODET_EN_MASK                             0x0004
#define FX100_CONTROL1_AUTODET_EN_ALIGN                            0
#define FX100_CONTROL1_AUTODET_EN_BITS                             1
#define FX100_CONTROL1_AUTODET_EN_SHIFT                            2

/* FX100 :: Control1 :: full_duplex [01:01] */
#define FX100_CONTROL1_FULL_DUPLEX_MASK                            0x0002
#define FX100_CONTROL1_FULL_DUPLEX_ALIGN                           0
#define FX100_CONTROL1_FULL_DUPLEX_BITS                            1
#define FX100_CONTROL1_FULL_DUPLEX_SHIFT                           1

/* FX100 :: Control1 :: enable [00:00] */
#define FX100_CONTROL1_ENABLE_MASK                                 0x0001
#define FX100_CONTROL1_ENABLE_ALIGN                                0
#define FX100_CONTROL1_ENABLE_BITS                                 1
#define FX100_CONTROL1_ENABLE_SHIFT                                0


/****************************************************************************
 * FX100 :: Control2
 ***************************************************************************/
/* FX100 :: Control2 :: reserved0 [15:12] */
#define FX100_CONTROL2_RESERVED0_MASK                              0xf000
#define FX100_CONTROL2_RESERVED0_ALIGN                             0
#define FX100_CONTROL2_RESERVED0_BITS                              4
#define FX100_CONTROL2_RESERVED0_SHIFT                             12

/* FX100 :: Control2 :: ping_pong_disable [11:11] */
#define FX100_CONTROL2_PING_PONG_DISABLE_MASK                      0x0800
#define FX100_CONTROL2_PING_PONG_DISABLE_ALIGN                     0
#define FX100_CONTROL2_PING_PONG_DISABLE_BITS                      1
#define FX100_CONTROL2_PING_PONG_DISABLE_SHIFT                     11

/* FX100 :: Control2 :: pll_clk125_sw_ref [10:10] */
#define FX100_CONTROL2_PLL_CLK125_SW_REF_MASK                      0x0400
#define FX100_CONTROL2_PLL_CLK125_SW_REF_ALIGN                     0
#define FX100_CONTROL2_PLL_CLK125_SW_REF_BITS                      1
#define FX100_CONTROL2_PLL_CLK125_SW_REF_SHIFT                     10

/* FX100 :: Control2 :: pll_clk125_sw_en [09:09] */
#define FX100_CONTROL2_PLL_CLK125_SW_EN_MASK                       0x0200
#define FX100_CONTROL2_PLL_CLK125_SW_EN_ALIGN                      0
#define FX100_CONTROL2_PLL_CLK125_SW_EN_BITS                       1
#define FX100_CONTROL2_PLL_CLK125_SW_EN_SHIFT                      9

/* FX100 :: Control2 :: clk_out_1000_sw_def [08:08] */
#define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_MASK                    0x0100
#define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_ALIGN                   0
#define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_BITS                    1
#define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_SHIFT                   8

/* FX100 :: Control2 :: clk_out_1000_sw_en [07:07] */
#define FX100_CONTROL2_CLK_OUT_1000_SW_EN_MASK                     0x0080
#define FX100_CONTROL2_CLK_OUT_1000_SW_EN_ALIGN                    0
#define FX100_CONTROL2_CLK_OUT_1000_SW_EN_BITS                     1
#define FX100_CONTROL2_CLK_OUT_1000_SW_EN_SHIFT                    7

/* FX100 :: Control2 :: mii_rxc_out_sw_ref [06:06] */
#define FX100_CONTROL2_MII_RXC_OUT_SW_REF_MASK                     0x0040
#define FX100_CONTROL2_MII_RXC_OUT_SW_REF_ALIGN                    0
#define FX100_CONTROL2_MII_RXC_OUT_SW_REF_BITS                     1
#define FX100_CONTROL2_MII_RXC_OUT_SW_REF_SHIFT                    6

/* FX100 :: Control2 :: mii_rxc_out_sw_en [05:05] */
#define FX100_CONTROL2_MII_RXC_OUT_SW_EN_MASK                      0x0020
#define FX100_CONTROL2_MII_RXC_OUT_SW_EN_ALIGN                     0
#define FX100_CONTROL2_MII_RXC_OUT_SW_EN_BITS                      1
#define FX100_CONTROL2_MII_RXC_OUT_SW_EN_SHIFT                     5

/* FX100 :: Control2 :: mii_rxc_out_sm_rst [04:04] */
#define FX100_CONTROL2_MII_RXC_OUT_SM_RST_MASK                     0x0010
#define FX100_CONTROL2_MII_RXC_OUT_SM_RST_ALIGN                    0
#define FX100_CONTROL2_MII_RXC_OUT_SM_RST_BITS                     1
#define FX100_CONTROL2_MII_RXC_OUT_SM_RST_SHIFT                    4

/* FX100 :: Control2 :: mode_chg_nrst [03:03] */
#define FX100_CONTROL2_MODE_CHG_NRST_MASK                          0x0008
#define FX100_CONTROL2_MODE_CHG_NRST_ALIGN                         0
#define FX100_CONTROL2_MODE_CHG_NRST_BITS                          1
#define FX100_CONTROL2_MODE_CHG_NRST_SHIFT                         3

/* FX100 :: Control2 :: reset_rxfifo [02:02] */
#define FX100_CONTROL2_RESET_RXFIFO_MASK                           0x0004
#define FX100_CONTROL2_RESET_RXFIFO_ALIGN                          0
#define FX100_CONTROL2_RESET_RXFIFO_BITS                           1
#define FX100_CONTROL2_RESET_RXFIFO_SHIFT                          2

/* FX100 :: Control2 :: bypass_rxfifo [01:01] */
#define FX100_CONTROL2_BYPASS_RXFIFO_MASK                          0x0002
#define FX100_CONTROL2_BYPASS_RXFIFO_ALIGN                         0
#define FX100_CONTROL2_BYPASS_RXFIFO_BITS                          1
#define FX100_CONTROL2_BYPASS_RXFIFO_SHIFT                         1

/* FX100 :: Control2 :: extend_pkt_size [00:00] */
#define FX100_CONTROL2_EXTEND_PKT_SIZE_MASK                        0x0001
#define FX100_CONTROL2_EXTEND_PKT_SIZE_ALIGN                       0
#define FX100_CONTROL2_EXTEND_PKT_SIZE_BITS                        1
#define FX100_CONTROL2_EXTEND_PKT_SIZE_SHIFT                       0


/****************************************************************************
 * FX100 :: Control3
 ***************************************************************************/
/* FX100 :: Control3 :: number_of_idle [15:08] */
#define FX100_CONTROL3_NUMBER_OF_IDLE_MASK                         0xff00
#define FX100_CONTROL3_NUMBER_OF_IDLE_ALIGN                        0
#define FX100_CONTROL3_NUMBER_OF_IDLE_BITS                         8
#define FX100_CONTROL3_NUMBER_OF_IDLE_SHIFT                        8

/* FX100 :: Control3 :: correlator_disable [07:07] */
#define FX100_CONTROL3_CORRELATOR_DISABLE_MASK                     0x0080
#define FX100_CONTROL3_CORRELATOR_DISABLE_ALIGN                    0
#define FX100_CONTROL3_CORRELATOR_DISABLE_BITS                     1
#define FX100_CONTROL3_CORRELATOR_DISABLE_SHIFT                    7

/* FX100 :: Control3 :: bypass_nrz [06:06] */
#define FX100_CONTROL3_BYPASS_NRZ_MASK                             0x0040
#define FX100_CONTROL3_BYPASS_NRZ_ALIGN                            0
#define FX100_CONTROL3_BYPASS_NRZ_BITS                             1
#define FX100_CONTROL3_BYPASS_NRZ_SHIFT                            6

/* FX100 :: Control3 :: bypass_encoder [05:05] */
#define FX100_CONTROL3_BYPASS_ENCODER_MASK                         0x0020
#define FX100_CONTROL3_BYPASS_ENCODER_ALIGN                        0
#define FX100_CONTROL3_BYPASS_ENCODER_BITS                         1
#define FX100_CONTROL3_BYPASS_ENCODER_SHIFT                        5

/* FX100 :: Control3 :: bypass_alignment [04:04] */
#define FX100_CONTROL3_BYPASS_ALIGNMENT_MASK                       0x0010
#define FX100_CONTROL3_BYPASS_ALIGNMENT_ALIGN                      0
#define FX100_CONTROL3_BYPASS_ALIGNMENT_BITS                       1
#define FX100_CONTROL3_BYPASS_ALIGNMENT_SHIFT                      4

/* FX100 :: Control3 :: force_link [03:03] */
#define FX100_CONTROL3_FORCE_LINK_MASK                             0x0008
#define FX100_CONTROL3_FORCE_LINK_ALIGN                            0
#define FX100_CONTROL3_FORCE_LINK_BITS                             1
#define FX100_CONTROL3_FORCE_LINK_SHIFT                            3

/* FX100 :: Control3 :: force_lock [02:02] */
#define FX100_CONTROL3_FORCE_LOCK_MASK                             0x0004
#define FX100_CONTROL3_FORCE_LOCK_ALIGN                            0
#define FX100_CONTROL3_FORCE_LOCK_BITS                             1
#define FX100_CONTROL3_FORCE_LOCK_SHIFT                            2

/* FX100 :: Control3 :: fast_unlock_timer [01:01] */
#define FX100_CONTROL3_FAST_UNLOCK_TIMER_MASK                      0x0002
#define FX100_CONTROL3_FAST_UNLOCK_TIMER_ALIGN                     0
#define FX100_CONTROL3_FAST_UNLOCK_TIMER_BITS                      1
#define FX100_CONTROL3_FAST_UNLOCK_TIMER_SHIFT                     1

/* FX100 :: Control3 :: fast_timers [00:00] */
#define FX100_CONTROL3_FAST_TIMERS_MASK                            0x0001
#define FX100_CONTROL3_FAST_TIMERS_ALIGN                           0
#define FX100_CONTROL3_FAST_TIMERS_BITS                            1
#define FX100_CONTROL3_FAST_TIMERS_SHIFT                           0


/****************************************************************************
 * FX100 :: Status1
 ***************************************************************************/
/* FX100 :: Status1 :: mode_change [15:15] */
#define FX100_STATUS1_MODE_CHANGE_MASK                             0x8000
#define FX100_STATUS1_MODE_CHANGE_ALIGN                            0
#define FX100_STATUS1_MODE_CHANGE_BITS                             1
#define FX100_STATUS1_MODE_CHANGE_SHIFT                            15

/* FX100 :: Status1 :: reserved0 [14:12] */
#define FX100_STATUS1_RESERVED0_MASK                               0x7000
#define FX100_STATUS1_RESERVED0_ALIGN                              0
#define FX100_STATUS1_RESERVED0_BITS                               3
#define FX100_STATUS1_RESERVED0_SHIFT                              12

/* FX100 :: Status1 :: fiber_pwrdwn_status_chg [11:11] */
#define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_MASK                 0x0800
#define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_ALIGN                0
#define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_BITS                 1
#define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_SHIFT                11

/* FX100 :: Status1 :: fiber_pwrdwn [10:10] */
#define FX100_STATUS1_FIBER_PWRDWN_MASK                            0x0400
#define FX100_STATUS1_FIBER_PWRDWN_ALIGN                           0
#define FX100_STATUS1_FIBER_PWRDWN_BITS                            1
#define FX100_STATUS1_FIBER_PWRDWN_SHIFT                           10

/* FX100 :: Status1 :: link_status_chg [09:09] */
#define FX100_STATUS1_LINK_STATUS_CHG_MASK                         0x0200
#define FX100_STATUS1_LINK_STATUS_CHG_ALIGN                        0
#define FX100_STATUS1_LINK_STATUS_CHG_BITS                         1
#define FX100_STATUS1_LINK_STATUS_CHG_SHIFT                        9

/* FX100 :: Status1 :: bad_esd_detected [08:08] */
#define FX100_STATUS1_BAD_ESD_DETECTED_MASK                        0x0100
#define FX100_STATUS1_BAD_ESD_DETECTED_ALIGN                       0
#define FX100_STATUS1_BAD_ESD_DETECTED_BITS                        1
#define FX100_STATUS1_BAD_ESD_DETECTED_SHIFT                       8

/* FX100 :: Status1 :: false_carrier_detected [07:07] */
#define FX100_STATUS1_FALSE_CARRIER_DETECTED_MASK                  0x0080
#define FX100_STATUS1_FALSE_CARRIER_DETECTED_ALIGN                 0
#define FX100_STATUS1_FALSE_CARRIER_DETECTED_BITS                  1
#define FX100_STATUS1_FALSE_CARRIER_DETECTED_SHIFT                 7

/* FX100 :: Status1 :: tx_err_detected [06:06] */
#define FX100_STATUS1_TX_ERR_DETECTED_MASK                         0x0040
#define FX100_STATUS1_TX_ERR_DETECTED_ALIGN                        0
#define FX100_STATUS1_TX_ERR_DETECTED_BITS                         1
#define FX100_STATUS1_TX_ERR_DETECTED_SHIFT                        6

/* FX100 :: Status1 :: rx_err_detected [05:05] */
#define FX100_STATUS1_RX_ERR_DETECTED_MASK                         0x0020
#define FX100_STATUS1_RX_ERR_DETECTED_ALIGN                        0
#define FX100_STATUS1_RX_ERR_DETECTED_BITS                         1
#define FX100_STATUS1_RX_ERR_DETECTED_SHIFT                        5

/* FX100 :: Status1 :: lock_timer_expired [04:04] */
#define FX100_STATUS1_LOCK_TIMER_EXPIRED_MASK                      0x0010
#define FX100_STATUS1_LOCK_TIMER_EXPIRED_ALIGN                     0
#define FX100_STATUS1_LOCK_TIMER_EXPIRED_BITS                      1
#define FX100_STATUS1_LOCK_TIMER_EXPIRED_SHIFT                     4

/* FX100 :: Status1 :: lost_lock [03:03] */
#define FX100_STATUS1_LOST_LOCK_MASK                               0x0008
#define FX100_STATUS1_LOST_LOCK_ALIGN                              0
#define FX100_STATUS1_LOST_LOCK_BITS                               1
#define FX100_STATUS1_LOST_LOCK_SHIFT                              3

/* FX100 :: Status1 :: faulting [02:02] */
#define FX100_STATUS1_FAULTING_MASK                                0x0004
#define FX100_STATUS1_FAULTING_ALIGN                               0
#define FX100_STATUS1_FAULTING_BITS                                1
#define FX100_STATUS1_FAULTING_SHIFT                               2

/* FX100 :: Status1 :: locked [01:01] */
#define FX100_STATUS1_LOCKED_MASK                                  0x0002
#define FX100_STATUS1_LOCKED_ALIGN                                 0
#define FX100_STATUS1_LOCKED_BITS                                  1
#define FX100_STATUS1_LOCKED_SHIFT                                 1

/* FX100 :: Status1 :: link [00:00] */
#define FX100_STATUS1_LINK_MASK                                    0x0001
#define FX100_STATUS1_LINK_ALIGN                                   0
#define FX100_STATUS1_LINK_BITS                                    1
#define FX100_STATUS1_LINK_SHIFT                                   0


/****************************************************************************
 * FX100 :: Status3
 ***************************************************************************/
/* FX100 :: Status3 :: linkmon_cntr [15:08] */
#define FX100_STATUS3_LINKMON_CNTR_MASK                            0xff00
#define FX100_STATUS3_LINKMON_CNTR_ALIGN                           0
#define FX100_STATUS3_LINKMON_CNTR_BITS                            8
#define FX100_STATUS3_LINKMON_CNTR_SHIFT                           8

/* FX100 :: Status3 :: reserved0 [07:07] */
#define FX100_STATUS3_RESERVED0_MASK                               0x0080
#define FX100_STATUS3_RESERVED0_ALIGN                              0
#define FX100_STATUS3_RESERVED0_BITS                               1
#define FX100_STATUS3_RESERVED0_SHIFT                              7

/* FX100 :: Status3 :: idles_detected_5b [06:06] */
#define FX100_STATUS3_IDLES_DETECTED_5B_MASK                       0x0040
#define FX100_STATUS3_IDLES_DETECTED_5B_ALIGN                      0
#define FX100_STATUS3_IDLES_DETECTED_5B_BITS                       1
#define FX100_STATUS3_IDLES_DETECTED_5B_SHIFT                      6

/* FX100 :: Status3 :: crs_ind_detected [05:05] */
#define FX100_STATUS3_CRS_IND_DETECTED_MASK                        0x0020
#define FX100_STATUS3_CRS_IND_DETECTED_ALIGN                       0
#define FX100_STATUS3_CRS_IND_DETECTED_BITS                        1
#define FX100_STATUS3_CRS_IND_DETECTED_SHIFT                       5

/* FX100 :: Status3 :: err_detected [04:04] */
#define FX100_STATUS3_ERR_DETECTED_MASK                            0x0010
#define FX100_STATUS3_ERR_DETECTED_ALIGN                           0
#define FX100_STATUS3_ERR_DETECTED_BITS                            1
#define FX100_STATUS3_ERR_DETECTED_SHIFT                           4

/* FX100 :: Status3 :: esd_detected [03:03] */
#define FX100_STATUS3_ESD_DETECTED_MASK                            0x0008
#define FX100_STATUS3_ESD_DETECTED_ALIGN                           0
#define FX100_STATUS3_ESD_DETECTED_BITS                            1
#define FX100_STATUS3_ESD_DETECTED_SHIFT                           3

/* FX100 :: Status3 :: ssd_detected [02:02] */
#define FX100_STATUS3_SSD_DETECTED_MASK                            0x0004
#define FX100_STATUS3_SSD_DETECTED_ALIGN                           0
#define FX100_STATUS3_SSD_DETECTED_BITS                            1
#define FX100_STATUS3_SSD_DETECTED_SHIFT                           2

/* FX100 :: Status3 :: ij_detected [01:01] */
#define FX100_STATUS3_IJ_DETECTED_MASK                             0x0002
#define FX100_STATUS3_IJ_DETECTED_ALIGN                            0
#define FX100_STATUS3_IJ_DETECTED_BITS                             1
#define FX100_STATUS3_IJ_DETECTED_SHIFT                            1

/* FX100 :: Status3 :: idles_detected [00:00] */
#define FX100_STATUS3_IDLES_DETECTED_MASK                          0x0001
#define FX100_STATUS3_IDLES_DETECTED_ALIGN                         0
#define FX100_STATUS3_IDLES_DETECTED_BITS                          1
#define FX100_STATUS3_IDLES_DETECTED_SHIFT                         0


/****************************************************************************
 * FX100 :: Status4
 ***************************************************************************/
/* FX100 :: Status4 :: reserved0 [15:15] */
#define FX100_STATUS4_RESERVED0_MASK                               0x8000
#define FX100_STATUS4_RESERVED0_ALIGN                              0
#define FX100_STATUS4_RESERVED0_BITS                               1
#define FX100_STATUS4_RESERVED0_SHIFT                              15

/* FX100 :: Status4 :: rx_badend [14:14] */
#define FX100_STATUS4_RX_BADEND_MASK                               0x4000
#define FX100_STATUS4_RX_BADEND_ALIGN                              0
#define FX100_STATUS4_RX_BADEND_BITS                               1
#define FX100_STATUS4_RX_BADEND_SHIFT                              14

/* FX100 :: Status4 :: rx_data [13:13] */
#define FX100_STATUS4_RX_DATA_MASK                                 0x2000
#define FX100_STATUS4_RX_DATA_ALIGN                                0
#define FX100_STATUS4_RX_DATA_BITS                                 1
#define FX100_STATUS4_RX_DATA_SHIFT                                13

/* FX100 :: Status4 :: rx_ssk [12:12] */
#define FX100_STATUS4_RX_SSK_MASK                                  0x1000
#define FX100_STATUS4_RX_SSK_ALIGN                                 0
#define FX100_STATUS4_RX_SSK_BITS                                  1
#define FX100_STATUS4_RX_SSK_SHIFT                                 12

/* FX100 :: Status4 :: rx_ssj [11:11] */
#define FX100_STATUS4_RX_SSJ_MASK                                  0x0800
#define FX100_STATUS4_RX_SSJ_ALIGN                                 0
#define FX100_STATUS4_RX_SSJ_BITS                                  1
#define FX100_STATUS4_RX_SSJ_SHIFT                                 11

/* FX100 :: Status4 :: rx_confirmk [10:10] */
#define FX100_STATUS4_RX_CONFIRMK_MASK                             0x0400
#define FX100_STATUS4_RX_CONFIRMK_ALIGN                            0
#define FX100_STATUS4_RX_CONFIRMK_BITS                             1
#define FX100_STATUS4_RX_CONFIRMK_SHIFT                            10

/* FX100 :: Status4 :: rx_badssd [09:09] */
#define FX100_STATUS4_RX_BADSSD_MASK                               0x0200
#define FX100_STATUS4_RX_BADSSD_ALIGN                              0
#define FX100_STATUS4_RX_BADSSD_BITS                               1
#define FX100_STATUS4_RX_BADSSD_SHIFT                              9

/* FX100 :: Status4 :: fx_linkfail [08:08] */
#define FX100_STATUS4_FX_LINKFAIL_MASK                             0x0100
#define FX100_STATUS4_FX_LINKFAIL_ALIGN                            0
#define FX100_STATUS4_FX_LINKFAIL_BITS                             1
#define FX100_STATUS4_FX_LINKFAIL_SHIFT                            8

/* FX100 :: Status4 :: tx_esr [07:07] */
#define FX100_STATUS4_TX_ESR_MASK                                  0x0080
#define FX100_STATUS4_TX_ESR_ALIGN                                 0
#define FX100_STATUS4_TX_ESR_BITS                                  1
#define FX100_STATUS4_TX_ESR_SHIFT                                 7

/* FX100 :: Status4 :: tx_est [06:06] */
#define FX100_STATUS4_TX_EST_MASK                                  0x0040
#define FX100_STATUS4_TX_EST_ALIGN                                 0
#define FX100_STATUS4_TX_EST_BITS                                  1
#define FX100_STATUS4_TX_EST_SHIFT                                 6

/* FX100 :: Status4 :: tx_terror [05:05] */
#define FX100_STATUS4_TX_TERROR_MASK                               0x0020
#define FX100_STATUS4_TX_TERROR_ALIGN                              0
#define FX100_STATUS4_TX_TERROR_BITS                               1
#define FX100_STATUS4_TX_TERROR_SHIFT                              5

/* FX100 :: Status4 :: tx_tdata [04:04] */
#define FX100_STATUS4_TX_TDATA_MASK                                0x0010
#define FX100_STATUS4_TX_TDATA_ALIGN                               0
#define FX100_STATUS4_TX_TDATA_BITS                                1
#define FX100_STATUS4_TX_TDATA_SHIFT                               4

/* FX100 :: Status4 :: tx_ssk [03:03] */
#define FX100_STATUS4_TX_SSK_MASK                                  0x0008
#define FX100_STATUS4_TX_SSK_ALIGN                                 0
#define FX100_STATUS4_TX_SSK_BITS                                  1
#define FX100_STATUS4_TX_SSK_SHIFT                                 3

/* FX100 :: Status4 :: tx_sek [02:02] */
#define FX100_STATUS4_TX_SEK_MASK                                  0x0004
#define FX100_STATUS4_TX_SEK_ALIGN                                 0
#define FX100_STATUS4_TX_SEK_BITS                                  1
#define FX100_STATUS4_TX_SEK_SHIFT                                 2

/* FX100 :: Status4 :: tx_ssj [01:01] */
#define FX100_STATUS4_TX_SSJ_MASK                                  0x0002
#define FX100_STATUS4_TX_SSJ_ALIGN                                 0
#define FX100_STATUS4_TX_SSJ_BITS                                  1
#define FX100_STATUS4_TX_SSJ_SHIFT                                 1

/* FX100 :: Status4 :: tx_sej [00:00] */
#define FX100_STATUS4_TX_SEJ_MASK                                  0x0001
#define FX100_STATUS4_TX_SEJ_ALIGN                                 0
#define FX100_STATUS4_TX_SEJ_BITS                                  1
#define FX100_STATUS4_TX_SEJ_SHIFT                                 0


/****************************************************************************
 * Hypercore_USER_aerBlk
 ***************************************************************************/
/****************************************************************************
 * aerBlk :: aer
 ***************************************************************************/
/* aerBlk :: aer :: MMD_deviceType [15:10] */
#define AERBLK_AER_MMD_DEVICETYPE_MASK                             0xfc00
#define AERBLK_AER_MMD_DEVICETYPE_ALIGN                            0
#define AERBLK_AER_MMD_DEVICETYPE_BITS                             6
#define AERBLK_AER_MMD_DEVICETYPE_SHIFT                            10

/* aerBlk :: aer :: MMD_port [09:00] */
#define AERBLK_AER_MMD_PORT_MASK                                   0x03ff
#define AERBLK_AER_MMD_PORT_ALIGN                                  0
#define AERBLK_AER_MMD_PORT_BITS                                   10
#define AERBLK_AER_MMD_PORT_SHIFT                                  0


/****************************************************************************
 * Hypercore_USER_Combo_IEEE0
 ***************************************************************************/
/****************************************************************************
 * Combo_IEEE0 :: MIICntl
 ***************************************************************************/
/* Combo_IEEE0 :: MIICntl :: rst_hw [15:15] */
#define COMBO_IEEE0_MIICNTL_RST_HW_MASK                            0x8000
#define COMBO_IEEE0_MIICNTL_RST_HW_ALIGN                           0
#define COMBO_IEEE0_MIICNTL_RST_HW_BITS                            1
#define COMBO_IEEE0_MIICNTL_RST_HW_SHIFT                           15

/* Combo_IEEE0 :: MIICntl :: gloopback [14:14] */
#define COMBO_IEEE0_MIICNTL_GLOOPBACK_MASK                         0x4000
#define COMBO_IEEE0_MIICNTL_GLOOPBACK_ALIGN                        0
#define COMBO_IEEE0_MIICNTL_GLOOPBACK_BITS                         1
#define COMBO_IEEE0_MIICNTL_GLOOPBACK_SHIFT                        14

/* Combo_IEEE0 :: MIICntl :: manual_speed0 [13:13] */
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_MASK                     0x2000
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_ALIGN                    0
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_BITS                     1
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_SHIFT                    13

/* Combo_IEEE0 :: MIICntl :: autoneg_enable [12:12] */
#define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_MASK                    0x1000
#define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_ALIGN                   0
#define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_BITS                    1
#define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_SHIFT                   12

/* Combo_IEEE0 :: MIICntl :: pwrdwn_sw [11:11] */
#define COMBO_IEEE0_MIICNTL_PWRDWN_SW_MASK                         0x0800
#define COMBO_IEEE0_MIICNTL_PWRDWN_SW_ALIGN                        0
#define COMBO_IEEE0_MIICNTL_PWRDWN_SW_BITS                         1
#define COMBO_IEEE0_MIICNTL_PWRDWN_SW_SHIFT                        11

/* Combo_IEEE0 :: MIICntl :: reserved0 [10:10] */
#define COMBO_IEEE0_MIICNTL_RESERVED0_MASK                         0x0400
#define COMBO_IEEE0_MIICNTL_RESERVED0_ALIGN                        0
#define COMBO_IEEE0_MIICNTL_RESERVED0_BITS                         1
#define COMBO_IEEE0_MIICNTL_RESERVED0_SHIFT                        10

/* Combo_IEEE0 :: MIICntl :: restart_autoneg [09:09] */
#define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_MASK                   0x0200
#define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_ALIGN                  0
#define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_BITS                   1
#define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_SHIFT                  9

/* Combo_IEEE0 :: MIICntl :: full_duplex [08:08] */
#define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_MASK                       0x0100
#define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_ALIGN                      0
#define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_BITS                       1
#define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_SHIFT                      8

/* Combo_IEEE0 :: MIICntl :: collision_test_en [07:07] */
#define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_MASK                 0x0080
#define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_ALIGN                0
#define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_BITS                 1
#define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_SHIFT                7

/* Combo_IEEE0 :: MIICntl :: manual_speed1 [06:06] */
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_MASK                     0x0040
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_ALIGN                    0
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_BITS                     1
#define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_SHIFT                    6

/* Combo_IEEE0 :: MIICntl :: reserved1 [05:00] */
#define COMBO_IEEE0_MIICNTL_RESERVED1_MASK                         0x003f
#define COMBO_IEEE0_MIICNTL_RESERVED1_ALIGN                        0
#define COMBO_IEEE0_MIICNTL_RESERVED1_BITS                         6
#define COMBO_IEEE0_MIICNTL_RESERVED1_SHIFT                        0


/****************************************************************************
 * Combo_IEEE0 :: MIIStat
 ***************************************************************************/
/* Combo_IEEE0 :: MIIStat :: s100BASE_T4_capable [15:15] */
#define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_MASK               0x8000
#define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_ALIGN              0
#define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_BITS               1
#define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_SHIFT              15

/* Combo_IEEE0 :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */
#define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK    0x4000
#define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN   0
#define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS    1
#define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT   14

/* Combo_IEEE0 :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */
#define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK    0x2000
#define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN   0
#define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS    1
#define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT   13

/* Combo_IEEE0 :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */
#define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK     0x1000
#define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN    0
#define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS     1
#define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT    12

/* Combo_IEEE0 :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */
#define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK     0x0800
#define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN    0
#define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS     1
#define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT    11

/* Combo_IEEE0 :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK   0x0400
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN  0
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS   1
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT  10

/* Combo_IEEE0 :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK   0x0200
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN  0
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS   1
#define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT  9

/* Combo_IEEE0 :: MIIStat :: extended_status [08:08] */
#define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_MASK                   0x0100
#define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_ALIGN                  0
#define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_BITS                   1
#define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_SHIFT                  8

/* Combo_IEEE0 :: MIIStat :: reserved0 [07:07] */
#define COMBO_IEEE0_MIISTAT_RESERVED0_MASK                         0x0080
#define COMBO_IEEE0_MIISTAT_RESERVED0_ALIGN                        0
#define COMBO_IEEE0_MIISTAT_RESERVED0_BITS                         1
#define COMBO_IEEE0_MIISTAT_RESERVED0_SHIFT                        7

/* Combo_IEEE0 :: MIIStat :: mf_preamble_supression [06:06] */
#define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK            0x0040
#define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN           0
#define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS            1
#define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT           6

/* Combo_IEEE0 :: MIIStat :: autoneg_complete [05:05] */
#define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_MASK                  0x0020
#define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_ALIGN                 0
#define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_BITS                  1
#define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_SHIFT                 5

/* Combo_IEEE0 :: MIIStat :: remote_fault [04:04] */
#define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_MASK                      0x0010
#define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_ALIGN                     0
#define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_BITS                      1
#define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_SHIFT                     4

/* Combo_IEEE0 :: MIIStat :: autoneg_ability [03:03] */
#define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_MASK                   0x0008
#define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_ALIGN                  0
#define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_BITS                   1
#define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_SHIFT                  3

/* Combo_IEEE0 :: MIIStat :: link_status [02:02] */
#define COMBO_IEEE0_MIISTAT_LINK_STATUS_MASK                       0x0004
#define COMBO_IEEE0_MIISTAT_LINK_STATUS_ALIGN                      0
#define COMBO_IEEE0_MIISTAT_LINK_STATUS_BITS                       1
#define COMBO_IEEE0_MIISTAT_LINK_STATUS_SHIFT                      2

/* Combo_IEEE0 :: MIIStat :: jabber_detect [01:01] */
#define COMBO_IEEE0_MIISTAT_JABBER_DETECT_MASK                     0x0002
#define COMBO_IEEE0_MIISTAT_JABBER_DETECT_ALIGN                    0
#define COMBO_IEEE0_MIISTAT_JABBER_DETECT_BITS                     1
#define COMBO_IEEE0_MIISTAT_JABBER_DETECT_SHIFT                    1

/* Combo_IEEE0 :: MIIStat :: extended_capability [00:00] */
#define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_MASK               0x0001
#define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_ALIGN              0
#define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_BITS               1
#define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_SHIFT              0


/****************************************************************************
 * Combo_IEEE0 :: Id1
 ***************************************************************************/
/* Combo_IEEE0 :: Id1 :: regid [15:00] */
#define COMBO_IEEE0_ID1_REGID_MASK                                 0xffff
#define COMBO_IEEE0_ID1_REGID_ALIGN                                0
#define COMBO_IEEE0_ID1_REGID_BITS                                 16
#define COMBO_IEEE0_ID1_REGID_SHIFT                                0


/****************************************************************************
 * Combo_IEEE0 :: Id2
 ***************************************************************************/
/* Combo_IEEE0 :: Id2 :: regid [15:00] */
#define COMBO_IEEE0_ID2_REGID_MASK                                 0xffff
#define COMBO_IEEE0_ID2_REGID_ALIGN                                0
#define COMBO_IEEE0_ID2_REGID_BITS                                 16
#define COMBO_IEEE0_ID2_REGID_SHIFT                                0


/****************************************************************************
 * Combo_IEEE0 :: AutoNegAdv
 ***************************************************************************/
/* Combo_IEEE0 :: AutoNegAdv :: next_page [15:15] */
#define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_MASK                      0x8000
#define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_ALIGN                     0
#define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_BITS                      1
#define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_SHIFT                     15

/* Combo_IEEE0 :: AutoNegAdv :: reserved0 [14:14] */
#define COMBO_IEEE0_AUTONEGADV_RESERVED0_MASK                      0x4000
#define COMBO_IEEE0_AUTONEGADV_RESERVED0_ALIGN                     0
#define COMBO_IEEE0_AUTONEGADV_RESERVED0_BITS                      1
#define COMBO_IEEE0_AUTONEGADV_RESERVED0_SHIFT                     14

/* Combo_IEEE0 :: AutoNegAdv :: remote_fault [13:12] */
#define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_MASK                   0x3000
#define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_ALIGN                  0
#define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_BITS                   2
#define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_SHIFT                  12

/* Combo_IEEE0 :: AutoNegAdv :: reserved1 [11:09] */
#define COMBO_IEEE0_AUTONEGADV_RESERVED1_MASK                      0x0e00
#define COMBO_IEEE0_AUTONEGADV_RESERVED1_ALIGN                     0
#define COMBO_IEEE0_AUTONEGADV_RESERVED1_BITS                      3
#define COMBO_IEEE0_AUTONEGADV_RESERVED1_SHIFT                     9

/* Combo_IEEE0 :: AutoNegAdv :: pause [08:07] */
#define COMBO_IEEE0_AUTONEGADV_PAUSE_MASK                          0x0180
#define COMBO_IEEE0_AUTONEGADV_PAUSE_ALIGN                         0
#define COMBO_IEEE0_AUTONEGADV_PAUSE_BITS                          2
#define COMBO_IEEE0_AUTONEGADV_PAUSE_SHIFT                         7

/* Combo_IEEE0 :: AutoNegAdv :: half_duplex [06:06] */
#define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_MASK                    0x0040
#define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_ALIGN                   0
#define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_BITS                    1
#define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_SHIFT                   6

/* Combo_IEEE0 :: AutoNegAdv :: full_duplex [05:05] */
#define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_MASK                    0x0020
#define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_ALIGN                   0
#define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_BITS                    1
#define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_SHIFT                   5

/* Combo_IEEE0 :: AutoNegAdv :: reserved2 [04:00] */
#define COMBO_IEEE0_AUTONEGADV_RESERVED2_MASK                      0x001f
#define COMBO_IEEE0_AUTONEGADV_RESERVED2_ALIGN                     0
#define COMBO_IEEE0_AUTONEGADV_RESERVED2_BITS                      5
#define COMBO_IEEE0_AUTONEGADV_RESERVED2_SHIFT                     0


/****************************************************************************
 * Combo_IEEE0 :: AutoNegLPAbil
 ***************************************************************************/
/* Combo_IEEE0 :: AutoNegLPAbil :: next_page [15:15] */
#define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_MASK                   0x8000
#define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_ALIGN                  0
#define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_BITS                   1
#define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_SHIFT                  15

/* Combo_IEEE0 :: AutoNegLPAbil :: acknowledge [14:14] */
#define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_MASK                 0x4000
#define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN                0
#define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_BITS                 1
#define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT                14

/* Combo_IEEE0 :: AutoNegLPAbil :: remote_fault [13:12] */
#define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_MASK                0x3000
#define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_ALIGN               0
#define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_BITS                2
#define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_SHIFT               12

/* Combo_IEEE0 :: AutoNegLPAbil :: reserved0 [11:09] */
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_MASK                   0x0e00
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_ALIGN                  0
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_BITS                   3
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_SHIFT                  9

/* Combo_IEEE0 :: AutoNegLPAbil :: pause [08:07] */
#define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_MASK                       0x0180
#define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_ALIGN                      0
#define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_BITS                       2
#define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_SHIFT                      7

/* Combo_IEEE0 :: AutoNegLPAbil :: half_duplex [06:06] */
#define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_MASK                 0x0040
#define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_ALIGN                0
#define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_BITS                 1
#define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_SHIFT                6

/* Combo_IEEE0 :: AutoNegLPAbil :: full_duplex [05:05] */
#define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_MASK                 0x0020
#define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_ALIGN                0
#define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_BITS                 1
#define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_SHIFT                5

/* Combo_IEEE0 :: AutoNegLPAbil :: reserved1 [04:01] */
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_MASK                   0x001e
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_ALIGN                  0
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_BITS                   4
#define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_SHIFT                  1

/* Combo_IEEE0 :: AutoNegLPAbil :: sgmii_mode [00:00] */
#define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_MASK                  0x0001
#define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_ALIGN                 0
#define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_BITS                  1
#define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_SHIFT                 0


/****************************************************************************
 * Combo_IEEE0 :: AutoNegExp
 ***************************************************************************/
/* Combo_IEEE0 :: AutoNegExp :: reserved0 [15:03] */
#define COMBO_IEEE0_AUTONEGEXP_RESERVED0_MASK                      0xfff8
#define COMBO_IEEE0_AUTONEGEXP_RESERVED0_ALIGN                     0
#define COMBO_IEEE0_AUTONEGEXP_RESERVED0_BITS                      13
#define COMBO_IEEE0_AUTONEGEXP_RESERVED0_SHIFT                     3

/* Combo_IEEE0 :: AutoNegExp :: next_page_ability [02:02] */
#define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK              0x0004
#define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN             0
#define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS              1
#define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT             2

/* Combo_IEEE0 :: AutoNegExp :: page_received [01:01] */
#define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_MASK                  0x0002
#define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_ALIGN                 0
#define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_BITS                  1
#define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_SHIFT                 1

/* Combo_IEEE0 :: AutoNegExp :: reserved1 [00:00] */
#define COMBO_IEEE0_AUTONEGEXP_RESERVED1_MASK                      0x0001
#define COMBO_IEEE0_AUTONEGEXP_RESERVED1_ALIGN                     0
#define COMBO_IEEE0_AUTONEGEXP_RESERVED1_BITS                      1
#define COMBO_IEEE0_AUTONEGEXP_RESERVED1_SHIFT                     0


/****************************************************************************
 * Combo_IEEE0 :: AutoNegNP
 ***************************************************************************/
/* Combo_IEEE0 :: AutoNegNP :: Next_Page [15:15] */
#define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_MASK                       0x8000
#define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_ALIGN                      0
#define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_BITS                       1
#define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_SHIFT                      15

/* Combo_IEEE0 :: AutoNegNP :: Ack [14:14] */
#define COMBO_IEEE0_AUTONEGNP_ACK_MASK                             0x4000
#define COMBO_IEEE0_AUTONEGNP_ACK_ALIGN                            0
#define COMBO_IEEE0_AUTONEGNP_ACK_BITS                             1
#define COMBO_IEEE0_AUTONEGNP_ACK_SHIFT                            14

/* Combo_IEEE0 :: AutoNegNP :: Message_Page [13:13] */
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_MASK                    0x2000
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_ALIGN                   0
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_BITS                    1
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_SHIFT                   13

/* Combo_IEEE0 :: AutoNegNP :: Ack2 [12:12] */
#define COMBO_IEEE0_AUTONEGNP_ACK2_MASK                            0x1000
#define COMBO_IEEE0_AUTONEGNP_ACK2_ALIGN                           0
#define COMBO_IEEE0_AUTONEGNP_ACK2_BITS                            1
#define COMBO_IEEE0_AUTONEGNP_ACK2_SHIFT                           12

/* Combo_IEEE0 :: AutoNegNP :: Toggle [11:11] */
#define COMBO_IEEE0_AUTONEGNP_TOGGLE_MASK                          0x0800
#define COMBO_IEEE0_AUTONEGNP_TOGGLE_ALIGN                         0
#define COMBO_IEEE0_AUTONEGNP_TOGGLE_BITS                          1
#define COMBO_IEEE0_AUTONEGNP_TOGGLE_SHIFT                         11

/* Combo_IEEE0 :: AutoNegNP :: Message [10:00] */
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_MASK                         0x07ff
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_ALIGN                        0
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_BITS                         11
#define COMBO_IEEE0_AUTONEGNP_MESSAGE_SHIFT                        0


/****************************************************************************
 * Combo_IEEE0 :: AutoNegLPAbil2
 ***************************************************************************/
/* Combo_IEEE0 :: AutoNegLPAbil2 :: Next_Page [15:15] */
#define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_MASK                  0x8000
#define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_ALIGN                 0
#define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_BITS                  1
#define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_SHIFT                 15

/* Combo_IEEE0 :: AutoNegLPAbil2 :: Ack [14:14] */
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK_MASK                        0x4000
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK_ALIGN                       0
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK_BITS                        1
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK_SHIFT                       14

/* Combo_IEEE0 :: AutoNegLPAbil2 :: Message_Page [13:13] */
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_MASK               0x2000
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN              0
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_BITS               1
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT              13

/* Combo_IEEE0 :: AutoNegLPAbil2 :: Ack2 [12:12] */
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_MASK                       0x1000
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_ALIGN                      0
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_BITS                       1
#define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_SHIFT                      12

/* Combo_IEEE0 :: AutoNegLPAbil2 :: Toggle [11:11] */
#define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_MASK                     0x0800
#define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_ALIGN                    0
#define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_BITS                     1
#define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_SHIFT                    11

/* Combo_IEEE0 :: AutoNegLPAbil2 :: Message [10:00] */
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_MASK                    0x07ff
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_ALIGN                   0
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_BITS                    11
#define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_SHIFT                   0


/****************************************************************************
 * Combo_IEEE0 :: MIIextStat
 ***************************************************************************/
/* Combo_IEEE0 :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x8000
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 15

/* Combo_IEEE0 :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x4000
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 14

/* Combo_IEEE0 :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x2000
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS 1
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 13

/* Combo_IEEE0 :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x1000
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS 1
#define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 12

/* Combo_IEEE0 :: MIIextStat :: reserved0 [11:00] */
#define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_MASK                      0x0fff
#define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_ALIGN                     0
#define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_BITS                      12
#define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_SHIFT                     0


/****************************************************************************
 * Hypercore_IEEE_PMD_PMD_ieee0Blk
 ***************************************************************************/
/****************************************************************************
 * PMD_ieee0Blk :: PMD_ieeeControl1
 ***************************************************************************/
/* PMD_ieee0Blk :: PMD_ieeeControl1 :: rst_sw [15:15] */
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_MASK                  0x8000
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_ALIGN                 0
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_BITS                  1
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_SHIFT                 15

/* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved0 [14:14] */
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_MASK               0x4000
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_ALIGN              0
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_BITS               1
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_SHIFT              14

/* PMD_ieee0Blk :: PMD_ieeeControl1 :: SpeedSelection0 [13:13] */
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_MASK         0x2000
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_ALIGN        0
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_BITS         1
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_SHIFT        13

/* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved1 [12:12] */
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_MASK               0x1000
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_ALIGN              0
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_BITS               1
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_SHIFT              12

/* PMD_ieee0Blk :: PMD_ieeeControl1 :: pwrdwn_sw_10g [11:11] */
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_MASK           0x0800
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_ALIGN          0
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_BITS           1
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_SHIFT          11

/* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved2 [10:07] */
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_MASK               0x0780
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_ALIGN              0
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_BITS               4
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_SHIFT              7

/* PMD_ieee0Blk :: PMD_ieeeControl1 :: SpeedSelection1 [06:06] */
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_MASK         0x0040
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_ALIGN        0
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_BITS         1
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_SHIFT        6

/* PMD_ieee0Blk :: PMD_ieeeControl1 :: SpeedSelection2 [05:02] */
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_MASK         0x003c
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_ALIGN        0
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_BITS         4
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_SHIFT        2

/* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved3 [01:01] */
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_MASK               0x0002
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_ALIGN              0
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_BITS               1
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_SHIFT              1

/* PMD_ieee0Blk :: PMD_ieeeControl1 :: gloop10g [00:00] */
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_MASK                0x0001
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_ALIGN               0
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_BITS                1
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_SHIFT               0


/****************************************************************************
 * PMD_ieee0Blk :: PMD_ieeeStatus1
 ***************************************************************************/
/* PMD_ieee0Blk :: PMD_ieeeStatus1 :: reserved0 [15:08] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_MASK                0xff00
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_ALIGN               0
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_BITS                8
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_SHIFT               8

/* PMD_ieee0Blk :: PMD_ieeeStatus1 :: Fault [07:07] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_MASK                    0x0080
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_ALIGN                   0
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_BITS                    1
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_SHIFT                   7

/* PMD_ieee0Blk :: PMD_ieeeStatus1 :: reserved1 [06:03] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_MASK                0x0078
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_ALIGN               0
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_BITS                4
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_SHIFT               3

/* PMD_ieee0Blk :: PMD_ieeeStatus1 :: Rx_linkStatus [02:02] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_MASK            0x0004
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_ALIGN           0
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_BITS            1
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_SHIFT           2

/* PMD_ieee0Blk :: PMD_ieeeStatus1 :: lowPoerwAbility [01:01] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_MASK          0x0002
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_ALIGN         0
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_BITS          1
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_SHIFT         1

/* PMD_ieee0Blk :: PMD_ieeeStatus1 :: reserved2 [00:00] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_MASK                0x0001
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_ALIGN               0
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_BITS                1
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_SHIFT               0


/****************************************************************************
 * PMD_ieee0Blk :: PMD_ieeeId1
 ***************************************************************************/
/* PMD_ieee0Blk :: PMD_ieeeId1 :: IEEEID1 [15:00] */
#define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_MASK                      0xffff
#define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_ALIGN                     0
#define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_BITS                      16
#define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_SHIFT                     0


/****************************************************************************
 * PMD_ieee0Blk :: PMD_ieeeId2
 ***************************************************************************/
/* PMD_ieee0Blk :: PMD_ieeeId2 :: IEEEID2 [15:00] */
#define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_MASK                      0xffff
#define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_ALIGN                     0
#define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_BITS                      16
#define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_SHIFT                     0


/****************************************************************************
 * PMD_ieee0Blk :: PMD_ieeeSpeedAbility
 ***************************************************************************/
/* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: reserved0 [15:07] */
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_MASK           0xff80
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_ALIGN          0
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_BITS           9
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_SHIFT          7

/* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed10M [06:06] */
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_MASK            0x0040
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_ALIGN           0
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_BITS            1
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_SHIFT           6

/* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed100M [05:05] */
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_MASK           0x0020
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_ALIGN          0
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_BITS           1
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_SHIFT          5

/* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed1000B [04:04] */
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_MASK          0x0010
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_ALIGN         0
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_BITS          1
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_SHIFT         4

/* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: reserved1 [03:03] */
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_MASK           0x0008
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_ALIGN          0
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_BITS           1
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_SHIFT          3

/* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed10PASS_TS [02:02] */
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_MASK      0x0004
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_ALIGN     0
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_BITS      1
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_SHIFT     2

/* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed2BASE_TL [01:01] */
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_MASK       0x0002
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_ALIGN      0
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_BITS       1
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_SHIFT      1

/* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed10G [00:00] */
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_MASK            0x0001
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_ALIGN           0
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_BITS            1
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_SHIFT           0


/****************************************************************************
 * PMD_ieee0Blk :: PMD_ieeeDevInPkg2
 ***************************************************************************/
/* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: Vendor2 [15:15] */
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR2_MASK                0x8000
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR2_ALIGN               0
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR2_BITS                1
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR2_SHIFT               15

/* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: Vendor1 [14:14] */
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR1_MASK                0x4000
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR1_ALIGN               0
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR1_BITS                1
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR1_SHIFT               14

/* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: CL22ext [13:13] */
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CL22EXT_MASK                0x2000
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CL22EXT_ALIGN               0
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CL22EXT_BITS                1
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CL22EXT_SHIFT               13

/* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: reserved0 [12:00] */
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_MASK              0x1fff
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_ALIGN             0
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_BITS              13
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_SHIFT             0


/****************************************************************************
 * PMD_ieee0Blk :: PMD_ieeeDevInPkg1
 ***************************************************************************/
/* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: reserved0 [15:08] */
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_MASK              0xff00
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_ALIGN             0
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_BITS              8
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_SHIFT             8

/* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: AN [07:07] */
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_AN_MASK                     0x0080
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_AN_ALIGN                    0
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_AN_BITS                     1
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_AN_SHIFT                    7

/* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: TC [06:06] */
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_TC_MASK                     0x0040
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_TC_ALIGN                    0
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_TC_BITS                     1
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_TC_SHIFT                    6

/* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: DTE_XS [05:05] */
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_DTE_XS_MASK                 0x0020
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_DTE_XS_ALIGN                0
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_DTE_XS_BITS                 1
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_DTE_XS_SHIFT                5

/* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: PHY_XS [04:04] */
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PHY_XS_MASK                 0x0010
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PHY_XS_ALIGN                0
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PHY_XS_BITS                 1
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PHY_XS_SHIFT                4

/* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: PCS_XS [03:03] */
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PCS_XS_MASK                 0x0008
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PCS_XS_ALIGN                0
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PCS_XS_BITS                 1
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PCS_XS_SHIFT                3

/* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: WIS [02:02] */
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_WIS_MASK                    0x0004
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_WIS_ALIGN                   0
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_WIS_BITS                    1
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_WIS_SHIFT                   2

/* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: PMA_PMD [01:01] */
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PMA_PMD_MASK                0x0002
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PMA_PMD_ALIGN               0
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PMA_PMD_BITS                1
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PMA_PMD_SHIFT               1

/* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: Clause22 [00:00] */
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CLAUSE22_MASK               0x0001
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CLAUSE22_ALIGN              0
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CLAUSE22_BITS               1
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CLAUSE22_SHIFT              0


/****************************************************************************
 * PMD_ieee0Blk :: PMD_ieeeControl2
 ***************************************************************************/
/* PMD_ieee0Blk :: PMD_ieeeControl2 :: reserved0 [15:03] */
#define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_MASK               0xfff8
#define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_ALIGN              0
#define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_BITS               13
#define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_SHIFT              3

/* PMD_ieee0Blk :: PMD_ieeeControl2 :: PMA_PMD_typeSel [02:00] */
#define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_MASK         0x0007
#define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_ALIGN        0
#define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_BITS         3
#define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_SHIFT        0


/****************************************************************************
 * PMD_ieee0Blk :: PMD_ieeeStatus2
 ***************************************************************************/
/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: devPresent [15:14] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_MASK               0xc000
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_ALIGN              0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_BITS               2
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_SHIFT              14

/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: txFaultAbility [13:13] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_MASK           0x2000
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_ALIGN          0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_BITS           1
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_SHIFT          13

/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: rxFaultAbility [12:12] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_MASK           0x1000
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_ALIGN          0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_BITS           1
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_SHIFT          12

/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: txFault [11:11] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_MASK                  0x0800
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_ALIGN                 0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_BITS                  1
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_SHIFT                 11

/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: rxFault [10:10] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_MASK                  0x0400
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_ALIGN                 0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_BITS                  1
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_SHIFT                 10

/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: extAbilities [09:09] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_MASK             0x0200
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_ALIGN            0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_BITS             1
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_SHIFT            9

/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_txDisableAble [08:08] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_MASK        0x0100
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_ALIGN       0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_BITS        1
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_SHIFT       8

/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_SR_able [07:07] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_MASK      0x0080
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_ALIGN     0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_BITS      1
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_SHIFT     7

/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_LR_able [06:06] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_MASK      0x0040
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_ALIGN     0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_BITS      1
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_SHIFT     6

/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_ER_able [05:05] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_MASK      0x0020
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_ALIGN     0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_BITS      1
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_SHIFT     5

/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_LX4_able [04:04] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_MASK     0x0010
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_ALIGN    0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_BITS     1
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_SHIFT    4

/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_SW_able [03:03] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_MASK      0x0008
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_ALIGN     0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_BITS      1
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_SHIFT     3

/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_LW_able [02:02] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_MASK      0x0004
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_ALIGN     0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_BITS      1
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_SHIFT     2

/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_EW_able [01:01] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_MASK      0x0002
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_ALIGN     0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_BITS      1
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_SHIFT     1

/* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMA_loopback_able [00:00] */
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_MASK        0x0001
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_ALIGN       0
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_BITS        1
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_SHIFT       0


/****************************************************************************
 * PMD_ieee0Blk :: PMD_txDisable_type
 ***************************************************************************/
/* PMD_ieee0Blk :: PMD_txDisable_type :: reserved0 [15:05] */
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_RESERVED0_MASK             0xffe0
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_RESERVED0_ALIGN            0
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_RESERVED0_BITS             11
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_RESERVED0_SHIFT            5

/* PMD_ieee0Blk :: PMD_txDisable_type :: tx_disable_ln3 [04:04] */
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN3_MASK        0x0010
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN3_ALIGN       0
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN3_BITS        1
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN3_SHIFT       4

/* PMD_ieee0Blk :: PMD_txDisable_type :: tx_disable_ln2 [03:03] */
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN2_MASK        0x0008
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN2_ALIGN       0
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN2_BITS        1
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN2_SHIFT       3

/* PMD_ieee0Blk :: PMD_txDisable_type :: tx_disable_ln1 [02:02] */
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN1_MASK        0x0004
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN1_ALIGN       0
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN1_BITS        1
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN1_SHIFT       2

/* PMD_ieee0Blk :: PMD_txDisable_type :: tx_disable_ln0 [01:01] */
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN0_MASK        0x0002
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN0_ALIGN       0
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN0_BITS        1
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN0_SHIFT       1

/* PMD_ieee0Blk :: PMD_txDisable_type :: tx_disable_global [00:00] */
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_GLOBAL_MASK     0x0001
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_GLOBAL_ALIGN    0
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_GLOBAL_BITS     1
#define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_GLOBAL_SHIFT    0


/****************************************************************************
 * PMD_ieee0Blk :: PMD_rxSignalDetect
 ***************************************************************************/
/* PMD_ieee0Blk :: PMD_rxSignalDetect :: reserved0 [15:05] */
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RESERVED0_MASK             0xffe0
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RESERVED0_ALIGN            0
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RESERVED0_BITS             11
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RESERVED0_SHIFT            5

/* PMD_ieee0Blk :: PMD_rxSignalDetect :: rxSigdet_ln3 [04:04] */
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN3_MASK          0x0010
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN3_ALIGN         0
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN3_BITS          1
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN3_SHIFT         4

/* PMD_ieee0Blk :: PMD_rxSignalDetect :: rxSigdet_ln2 [03:03] */
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN2_MASK          0x0008
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN2_ALIGN         0
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN2_BITS          1
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN2_SHIFT         3

/* PMD_ieee0Blk :: PMD_rxSignalDetect :: rxSigdet_ln1 [02:02] */
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN1_MASK          0x0004
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN1_ALIGN         0
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN1_BITS          1
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN1_SHIFT         2

/* PMD_ieee0Blk :: PMD_rxSignalDetect :: rxSigdet_ln0 [01:01] */
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN0_MASK          0x0002
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN0_ALIGN         0
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN0_BITS          1
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN0_SHIFT         1

/* PMD_ieee0Blk :: PMD_rxSignalDetect :: rxSigdet_global [00:00] */
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_GLOBAL_MASK       0x0001
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_GLOBAL_ALIGN      0
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_GLOBAL_BITS       1
#define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_GLOBAL_SHIFT      0


/****************************************************************************
 * PMD_ieee0Blk :: PMD_extendedAbility
 ***************************************************************************/
/* PMD_ieee0Blk :: PMD_extendedAbility :: reserved0 [15:09] */
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_MASK            0xfe00
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_ALIGN           0
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_BITS            7
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_SHIFT           9

/* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10BASE_T_Ability [08:08] */
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_MASK 0x0100
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_ALIGN 0
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_BITS 1
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_SHIFT 8

/* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_100BASE_TX_Ability [07:07] */
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_MASK 0x0080
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_ALIGN 0
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_BITS 1
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_SHIFT 7

/* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_1000BASE_KX_Ability [06:06] */
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_MASK 0x0040
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_ALIGN 0
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_BITS 1
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_SHIFT 6

/* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_1000BASE_T_Ability [05:05] */
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_MASK 0x0020
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_ALIGN 0
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_BITS 1
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_SHIFT 5

/* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_KR_Ability [04:04] */
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_MASK 0x0010
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_ALIGN 0
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_BITS 1
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_SHIFT 4

/* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_KX4_Ability [03:03] */
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_MASK 0x0008
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_ALIGN 0
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_BITS 1
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_SHIFT 3

/* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_T_Ability [02:02] */
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_MASK 0x0004
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_ALIGN 0
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_BITS 1
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_SHIFT 2

/* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_LRM_Ability [01:01] */
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_MASK 0x0002
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_ALIGN 0
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_BITS 1
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_SHIFT 1

/* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_CX4_Ability [00:00] */
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_MASK 0x0001
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_ALIGN 0
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_BITS 1
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_SHIFT 0


/****************************************************************************
 * Hypercore_IEEE_PMD_PMD_ieee10Blk
 ***************************************************************************/
/****************************************************************************
 * PMD_ieee10Blk :: PMD_KX_control
 ***************************************************************************/
/* PMD_ieee10Blk :: PMD_KX_control :: reserved0 [15:01] */
#define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_MASK                0xfffe
#define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_ALIGN               0
#define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_BITS                15
#define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_SHIFT               1

/* PMD_ieee10Blk :: PMD_KX_control :: tx_disable [00:00] */
#define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_MASK               0x0001
#define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_ALIGN              0
#define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_BITS               1
#define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_SHIFT              0


/****************************************************************************
 * PMD_ieee10Blk :: PMD_KX_status
 ***************************************************************************/
/* PMD_ieee10Blk :: PMD_KX_status :: reserved0 [15:14] */
#define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_MASK                 0xc000
#define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_ALIGN                0
#define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_BITS                 2
#define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_SHIFT                14

/* PMD_ieee10Blk :: PMD_KX_status :: KX_txFaultAbility [13:13] */
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_MASK         0x2000
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_ALIGN        0
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_BITS         1
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_SHIFT        13

/* PMD_ieee10Blk :: PMD_KX_status :: KX_rxFaultAbility [12:12] */
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_MASK         0x1000
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_ALIGN        0
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_BITS         1
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_SHIFT        12

/* PMD_ieee10Blk :: PMD_KX_status :: KX_txFault [11:11] */
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_MASK                0x0800
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_ALIGN               0
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_BITS                1
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_SHIFT               11

/* PMD_ieee10Blk :: PMD_KX_status :: KX_rsFault [10:10] */
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_MASK                0x0400
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_ALIGN               0
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_BITS                1
#define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_SHIFT               10

/* PMD_ieee10Blk :: PMD_KX_status :: reserved1 [09:09] */
#define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_MASK                 0x0200
#define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_ALIGN                0
#define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_BITS                 1
#define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_SHIFT                9

/* PMD_ieee10Blk :: PMD_KX_status :: txDisableAbility [08:08] */
#define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_MASK          0x0100
#define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_ALIGN         0
#define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_BITS          1
#define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_SHIFT         8

/* PMD_ieee10Blk :: PMD_KX_status :: reserved2 [07:01] */
#define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_MASK                 0x00fe
#define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_ALIGN                0
#define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_BITS                 7
#define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_SHIFT                1

/* PMD_ieee10Blk :: PMD_KX_status :: PMD_sigdet [00:00] */
#define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_MASK                0x0001
#define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_ALIGN               0
#define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_BITS                1
#define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_SHIFT               0


/****************************************************************************
 * Hypercore_IEEE_DTE_DTE_ieee0Blk
 ***************************************************************************/
/****************************************************************************
 * DTE_ieee0Blk :: DTE_ieeeControl1
 ***************************************************************************/
/* DTE_ieee0Blk :: DTE_ieeeControl1 :: rst_sw [15:15] */
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RST_SW_MASK                  0x8000
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RST_SW_ALIGN                 0
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RST_SW_BITS                  1
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RST_SW_SHIFT                 15

/* DTE_ieee0Blk :: DTE_ieeeControl1 :: gloop10g [14:14] */
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_GLOOP10G_MASK                0x4000
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_GLOOP10G_ALIGN               0
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_GLOOP10G_BITS                1
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_GLOOP10G_SHIFT               14

/* DTE_ieee0Blk :: DTE_ieeeControl1 :: SpeedSelection0 [13:13] */
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION0_MASK         0x2000
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION0_ALIGN        0
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION0_BITS         1
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION0_SHIFT        13

/* DTE_ieee0Blk :: DTE_ieeeControl1 :: reserved0 [12:12] */
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED0_MASK               0x1000
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED0_ALIGN              0
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED0_BITS               1
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED0_SHIFT              12

/* DTE_ieee0Blk :: DTE_ieeeControl1 :: pwrdwn_sw_10g [11:11] */
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_PWRDWN_SW_10G_MASK           0x0800
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_PWRDWN_SW_10G_ALIGN          0
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_PWRDWN_SW_10G_BITS           1
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_PWRDWN_SW_10G_SHIFT          11

/* DTE_ieee0Blk :: DTE_ieeeControl1 :: reserved1 [10:07] */
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED1_MASK               0x0780
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED1_ALIGN              0
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED1_BITS               4
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED1_SHIFT              7

/* DTE_ieee0Blk :: DTE_ieeeControl1 :: SpeedSelection1 [06:06] */
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION1_MASK         0x0040
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION1_ALIGN        0
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION1_BITS         1
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION1_SHIFT        6

/* DTE_ieee0Blk :: DTE_ieeeControl1 :: SpeedSelection2 [05:02] */
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION2_MASK         0x003c
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION2_ALIGN        0
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION2_BITS         4
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION2_SHIFT        2

/* DTE_ieee0Blk :: DTE_ieeeControl1 :: reserved2 [01:00] */
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED2_MASK               0x0003
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED2_ALIGN              0
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED2_BITS               2
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED2_SHIFT              0


/****************************************************************************
 * DTE_ieee0Blk :: DTE_ieeeStatus1
 ***************************************************************************/
/* DTE_ieee0Blk :: DTE_ieeeStatus1 :: reserved0 [15:08] */
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED0_MASK                0xff00
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED0_ALIGN               0
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED0_BITS                8
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED0_SHIFT               8

/* DTE_ieee0Blk :: DTE_ieeeStatus1 :: Fault [07:07] */
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_FAULT_MASK                    0x0080
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_FAULT_ALIGN                   0
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_FAULT_BITS                    1
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_FAULT_SHIFT                   7

/* DTE_ieee0Blk :: DTE_ieeeStatus1 :: reserved1 [06:03] */
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED1_MASK                0x0078
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED1_ALIGN               0
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED1_BITS                4
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED1_SHIFT               3

/* DTE_ieee0Blk :: DTE_ieeeStatus1 :: Rx_linkStatus [02:02] */
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RX_LINKSTATUS_MASK            0x0004
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RX_LINKSTATUS_ALIGN           0
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RX_LINKSTATUS_BITS            1
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RX_LINKSTATUS_SHIFT           2

/* DTE_ieee0Blk :: DTE_ieeeStatus1 :: lowPowerAbility [01:01] */
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_LOWPOWERABILITY_MASK          0x0002
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_LOWPOWERABILITY_ALIGN         0
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_LOWPOWERABILITY_BITS          1
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_LOWPOWERABILITY_SHIFT         1

/* DTE_ieee0Blk :: DTE_ieeeStatus1 :: reserved2 [00:00] */
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED2_MASK                0x0001
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED2_ALIGN               0
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED2_BITS                1
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED2_SHIFT               0


/****************************************************************************
 * DTE_ieee0Blk :: DTE_ieeeId1
 ***************************************************************************/
/* DTE_ieee0Blk :: DTE_ieeeId1 :: IEEEID1 [15:00] */
#define DTE_IEEE0BLK_DTE_IEEEID1_IEEEID1_MASK                      0xffff
#define DTE_IEEE0BLK_DTE_IEEEID1_IEEEID1_ALIGN                     0
#define DTE_IEEE0BLK_DTE_IEEEID1_IEEEID1_BITS                      16
#define DTE_IEEE0BLK_DTE_IEEEID1_IEEEID1_SHIFT                     0


/****************************************************************************
 * DTE_ieee0Blk :: DTE_ieeeId2
 ***************************************************************************/
/* DTE_ieee0Blk :: DTE_ieeeId2 :: IEEEID2 [15:00] */
#define DTE_IEEE0BLK_DTE_IEEEID2_IEEEID2_MASK                      0xffff
#define DTE_IEEE0BLK_DTE_IEEEID2_IEEEID2_ALIGN                     0
#define DTE_IEEE0BLK_DTE_IEEEID2_IEEEID2_BITS                      16
#define DTE_IEEE0BLK_DTE_IEEEID2_IEEEID2_SHIFT                     0


/****************************************************************************
 * DTE_ieee0Blk :: DTE_ieeeSpeedAbility
 ***************************************************************************/
/* DTE_ieee0Blk :: DTE_ieeeSpeedAbility :: reserved0 [15:01] */
#define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_RESERVED0_MASK           0xfffe
#define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_RESERVED0_ALIGN          0
#define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_RESERVED0_BITS           15
#define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_RESERVED0_SHIFT          1

/* DTE_ieee0Blk :: DTE_ieeeSpeedAbility :: speed10G [00:00] */
#define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_SPEED10G_MASK            0x0001
#define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_SPEED10G_ALIGN           0
#define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_SPEED10G_BITS            1
#define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_SPEED10G_SHIFT           0


/****************************************************************************
 * DTE_ieee0Blk :: DTE_ieeeDevInPkg2
 ***************************************************************************/
/* DTE_ieee0Blk :: DTE_ieeeDevInPkg2 :: Vendor2 [15:15] */
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR2_MASK                0x8000
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR2_ALIGN               0
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR2_BITS                1
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR2_SHIFT               15

/* DTE_ieee0Blk :: DTE_ieeeDevInPkg2 :: Vendor1 [14:14] */
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR1_MASK                0x4000
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR1_ALIGN               0
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR1_BITS                1
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR1_SHIFT               14

/* DTE_ieee0Blk :: DTE_ieeeDevInPkg2 :: CL22ext [13:13] */
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_CL22EXT_MASK                0x2000
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_CL22EXT_ALIGN               0
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_CL22EXT_BITS                1
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_CL22EXT_SHIFT               13

/* DTE_ieee0Blk :: DTE_ieeeDevInPkg2 :: reserved0 [12:00] */
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_RESERVED0_MASK              0x1fff
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_RESERVED0_ALIGN             0
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_RESERVED0_BITS              13
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_RESERVED0_SHIFT             0


/****************************************************************************
 * DTE_ieee0Blk :: DTE_ieeeDevInPkg1
 ***************************************************************************/
/* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: reserved0 [15:08] */
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_RESERVED0_MASK              0xff00
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_RESERVED0_ALIGN             0
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_RESERVED0_BITS              8
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_RESERVED0_SHIFT             8

/* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: AN [07:07] */
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_AN_MASK                     0x0080
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_AN_ALIGN                    0
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_AN_BITS                     1
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_AN_SHIFT                    7

/* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: TC [06:06] */
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_TC_MASK                     0x0040
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_TC_ALIGN                    0
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_TC_BITS                     1
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_TC_SHIFT                    6

/* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: DTE_XS [05:05] */
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_DTE_XS_MASK                 0x0020
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_DTE_XS_ALIGN                0
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_DTE_XS_BITS                 1
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_DTE_XS_SHIFT                5

/* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: PHY_XS [04:04] */
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PHY_XS_MASK                 0x0010
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PHY_XS_ALIGN                0
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PHY_XS_BITS                 1
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PHY_XS_SHIFT                4

/* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: PCS_XS [03:03] */
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PCS_XS_MASK                 0x0008
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PCS_XS_ALIGN                0
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PCS_XS_BITS                 1
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PCS_XS_SHIFT                3

/* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: WIS [02:02] */
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_WIS_MASK                    0x0004
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_WIS_ALIGN                   0
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_WIS_BITS                    1
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_WIS_SHIFT                   2

/* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: PMA_PMD [01:01] */
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PMA_PMD_MASK                0x0002
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PMA_PMD_ALIGN               0
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PMA_PMD_BITS                1
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PMA_PMD_SHIFT               1

/* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: Clause22 [00:00] */
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_CLAUSE22_MASK               0x0001
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_CLAUSE22_ALIGN              0
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_CLAUSE22_BITS               1
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_CLAUSE22_SHIFT              0


/****************************************************************************
 * DTE_ieee0Blk :: DTE_ieeeStatus2
 ***************************************************************************/
/* DTE_ieee0Blk :: DTE_ieeeStatus2 :: devPresent [15:14] */
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_DEVPRESENT_MASK               0xc000
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_DEVPRESENT_ALIGN              0
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_DEVPRESENT_BITS               2
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_DEVPRESENT_SHIFT              14

/* DTE_ieee0Blk :: DTE_ieeeStatus2 :: reserved0 [13:12] */
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED0_MASK                0x3000
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED0_ALIGN               0
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED0_BITS                2
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED0_SHIFT               12

/* DTE_ieee0Blk :: DTE_ieeeStatus2 :: txFault [11:11] */
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_TXFAULT_MASK                  0x0800
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_TXFAULT_ALIGN                 0
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_TXFAULT_BITS                  1
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_TXFAULT_SHIFT                 11

/* DTE_ieee0Blk :: DTE_ieeeStatus2 :: rxFault [10:10] */
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_RXFAULT_MASK                  0x0400
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_RXFAULT_ALIGN                 0
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_RXFAULT_BITS                  1
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_RXFAULT_SHIFT                 10

/* DTE_ieee0Blk :: DTE_ieeeStatus2 :: reserved1 [09:00] */
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED1_MASK                0x03ff
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED1_ALIGN               0
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED1_BITS                10
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED1_SHIFT               0


/****************************************************************************
 * Hypercore_IEEE_DTE_DTE_ieee1Blk
 ***************************************************************************/
/****************************************************************************
 * DTE_ieee1Blk :: DTE_laneStatus
 ***************************************************************************/
/* DTE_ieee1Blk :: DTE_laneStatus :: reserved0 [15:13] */
#define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED0_MASK                 0xe000
#define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED0_ALIGN                0
#define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED0_BITS                 3
#define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED0_SHIFT                13

/* DTE_ieee1Blk :: DTE_laneStatus :: DTE_alignStatus [12:12] */
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_ALIGNSTATUS_MASK           0x1000
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_ALIGNSTATUS_ALIGN          0
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_ALIGNSTATUS_BITS           1
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_ALIGNSTATUS_SHIFT          12

/* DTE_ieee1Blk :: DTE_laneStatus :: DTE_PatTestAbility [11:11] */
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_PATTESTABILITY_MASK        0x0800
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_PATTESTABILITY_ALIGN       0
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_PATTESTABILITY_BITS        1
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_PATTESTABILITY_SHIFT       11

/* DTE_ieee1Blk :: DTE_laneStatus :: reserved1 [10:04] */
#define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED1_MASK                 0x07f0
#define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED1_ALIGN                0
#define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED1_BITS                 7
#define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED1_SHIFT                4

/* DTE_ieee1Blk :: DTE_laneStatus :: DTE_lane3Sync [03:03] */
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE3SYNC_MASK             0x0008
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE3SYNC_ALIGN            0
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE3SYNC_BITS             1
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE3SYNC_SHIFT            3

/* DTE_ieee1Blk :: DTE_laneStatus :: DTE_lane2Sync [02:02] */
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE2SYNC_MASK             0x0004
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE2SYNC_ALIGN            0
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE2SYNC_BITS             1
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE2SYNC_SHIFT            2

/* DTE_ieee1Blk :: DTE_laneStatus :: DTE_lane1Sync [01:01] */
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE1SYNC_MASK             0x0002
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE1SYNC_ALIGN            0
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE1SYNC_BITS             1
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE1SYNC_SHIFT            1

/* DTE_ieee1Blk :: DTE_laneStatus :: DTE_lane0Sync [00:00] */
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE0SYNC_MASK             0x0001
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE0SYNC_ALIGN            0
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE0SYNC_BITS             1
#define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE0SYNC_SHIFT            0


/****************************************************************************
 * DTE_ieee1Blk :: DTE_ieeeTestControl
 ***************************************************************************/
/* DTE_ieee1Blk :: DTE_ieeeTestControl :: reserved0 [15:03] */
#define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_RESERVED0_MASK            0xfff8
#define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_RESERVED0_ALIGN           0
#define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_RESERVED0_BITS            13
#define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_RESERVED0_SHIFT           3

/* DTE_ieee1Blk :: DTE_ieeeTestControl :: DTE_txTestPatEn [02:02] */
#define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TXTESTPATEN_MASK      0x0004
#define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TXTESTPATEN_ALIGN     0
#define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TXTESTPATEN_BITS      1
#define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TXTESTPATEN_SHIFT     2

/* DTE_ieee1Blk :: DTE_ieeeTestControl :: DTE_testPatSel [01:00] */
#define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TESTPATSEL_MASK       0x0003
#define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TESTPATSEL_ALIGN      0
#define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TESTPATSEL_BITS       2
#define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TESTPATSEL_SHIFT      0


/****************************************************************************
 * Hypercore_IEEE_CL73_AN_ieee0Blk
 ***************************************************************************/
/****************************************************************************
 * AN_ieee0Blk :: AN_ieeeControl1
 ***************************************************************************/
/* AN_ieee0Blk :: AN_ieeeControl1 :: rst_sw [15:15] */
#define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_MASK                    0x8000
#define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_ALIGN                   0
#define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_BITS                    1
#define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_SHIFT                   15

/* AN_ieee0Blk :: AN_ieeeControl1 :: gloop10g [14:14] */
#define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_MASK                  0x4000
#define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_ALIGN                 0
#define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_BITS                  1
#define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_SHIFT                 14

/* AN_ieee0Blk :: AN_ieeeControl1 :: ExtendNPen [13:13] */
#define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_MASK                0x2000
#define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_ALIGN               0
#define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_BITS                1
#define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_SHIFT               13

/* AN_ieee0Blk :: AN_ieeeControl1 :: AN_enable [12:12] */
#define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_MASK                 0x1000
#define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_ALIGN                0
#define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_BITS                 1
#define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_SHIFT                12

/* AN_ieee0Blk :: AN_ieeeControl1 :: reserved0 [11:10] */
#define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_MASK                 0x0c00
#define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_ALIGN                0
#define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_BITS                 2
#define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_SHIFT                10

/* AN_ieee0Blk :: AN_ieeeControl1 :: restartAN [09:09] */
#define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_MASK                 0x0200
#define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_ALIGN                0
#define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_BITS                 1
#define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_SHIFT                9

/* AN_ieee0Blk :: AN_ieeeControl1 :: reserved1 [08:00] */
#define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_MASK                 0x01ff
#define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_ALIGN                0
#define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_BITS                 9
#define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_SHIFT                0


/****************************************************************************
 * AN_ieee0Blk :: AN_ieeeStatus1
 ***************************************************************************/
/* AN_ieee0Blk :: AN_ieeeStatus1 :: reserved0 [15:08] */
#define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_MASK                  0xff00
#define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_ALIGN                 0
#define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_BITS                  8
#define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_SHIFT                 8

/* AN_ieee0Blk :: AN_ieeeStatus1 :: ExtendedNP_able [07:07] */
#define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_MASK            0x0080
#define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_ALIGN           0
#define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_BITS            1
#define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_SHIFT           7

/* AN_ieee0Blk :: AN_ieeeStatus1 :: pageReceived [06:06] */
#define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_MASK               0x0040
#define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_ALIGN              0
#define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_BITS               1
#define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_SHIFT              6

/* AN_ieee0Blk :: AN_ieeeStatus1 :: ANcomplete [05:05] */
#define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_MASK                 0x0020
#define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_ALIGN                0
#define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_BITS                 1
#define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_SHIFT                5

/* AN_ieee0Blk :: AN_ieeeStatus1 :: remoteFault [04:04] */
#define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_MASK                0x0010
#define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_ALIGN               0
#define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_BITS                1
#define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_SHIFT               4

/* AN_ieee0Blk :: AN_ieeeStatus1 :: ANability [03:03] */
#define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_MASK                  0x0008
#define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_ALIGN                 0
#define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_BITS                  1
#define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_SHIFT                 3

/* AN_ieee0Blk :: AN_ieeeStatus1 :: linkStatus [02:02] */
#define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_MASK                 0x0004
#define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_ALIGN                0
#define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_BITS                 1
#define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_SHIFT                2

/* AN_ieee0Blk :: AN_ieeeStatus1 :: reserved1 [01:01] */
#define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_MASK                  0x0002
#define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_ALIGN                 0
#define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_BITS                  1
#define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_SHIFT                 1

/* AN_ieee0Blk :: AN_ieeeStatus1 :: LP_ANability [00:00] */
#define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_MASK               0x0001
#define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_ALIGN              0
#define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_BITS               1
#define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_SHIFT              0


/****************************************************************************
 * AN_ieee0Blk :: AN_ieeeId1
 ***************************************************************************/
/* AN_ieee0Blk :: AN_ieeeId1 :: IEEEID1 [15:00] */
#define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_MASK                        0xffff
#define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_ALIGN                       0
#define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_BITS                        16
#define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_SHIFT                       0


/****************************************************************************
 * AN_ieee0Blk :: AN_ieeeId2
 ***************************************************************************/
/* AN_ieee0Blk :: AN_ieeeId2 :: IEEEID2 [15:00] */
#define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_MASK                        0xffff
#define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_ALIGN                       0
#define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_BITS                        16
#define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_SHIFT                       0


/****************************************************************************
 * AN_ieee0Blk :: AN_ieeeDevInPkg2
 ***************************************************************************/
/* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: Vendor2 [15:15] */
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR2_MASK                  0x8000
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR2_ALIGN                 0
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR2_BITS                  1
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR2_SHIFT                 15

/* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: Vendor1 [14:14] */
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR1_MASK                  0x4000
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR1_ALIGN                 0
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR1_BITS                  1
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR1_SHIFT                 14

/* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: CL22ext [13:13] */
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CL22EXT_MASK                  0x2000
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CL22EXT_ALIGN                 0
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CL22EXT_BITS                  1
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CL22EXT_SHIFT                 13

/* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: reserved0 [12:00] */
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_MASK                0x1fff
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_ALIGN               0
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_BITS                13
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_SHIFT               0


/****************************************************************************
 * AN_ieee0Blk :: AN_ieeeDevInPkg1
 ***************************************************************************/
/* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: reserved0 [15:08] */
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_MASK                0xff00
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_ALIGN               0
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_BITS                8
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_SHIFT               8

/* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: AN [07:07] */
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_AN_MASK                       0x0080
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_AN_ALIGN                      0
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_AN_BITS                       1
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_AN_SHIFT                      7

/* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: TC [06:06] */
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_TC_MASK                       0x0040
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_TC_ALIGN                      0
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_TC_BITS                       1
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_TC_SHIFT                      6

/* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: DTE_XS [05:05] */
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_DTE_XS_MASK                   0x0020
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_DTE_XS_ALIGN                  0
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_DTE_XS_BITS                   1
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_DTE_XS_SHIFT                  5

/* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: PHY_XS [04:04] */
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PHY_XS_MASK                   0x0010
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PHY_XS_ALIGN                  0
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PHY_XS_BITS                   1
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PHY_XS_SHIFT                  4

/* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: PCS_XS [03:03] */
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PCS_XS_MASK                   0x0008
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PCS_XS_ALIGN                  0
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PCS_XS_BITS                   1
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PCS_XS_SHIFT                  3

/* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: WIS [02:02] */
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_WIS_MASK                      0x0004
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_WIS_ALIGN                     0
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_WIS_BITS                      1
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_WIS_SHIFT                     2

/* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: PMA_PMD [01:01] */
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PMA_PMD_MASK                  0x0002
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PMA_PMD_ALIGN                 0
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PMA_PMD_BITS                  1
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PMA_PMD_SHIFT                 1

/* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: Clause22 [00:00] */
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CLAUSE22_MASK                 0x0001
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CLAUSE22_ALIGN                0
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CLAUSE22_BITS                 1
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CLAUSE22_SHIFT                0


/****************************************************************************
 * Hypercore_IEEE_CL73_AN_ieee1Blk
 ***************************************************************************/
/****************************************************************************
 * AN_ieee1Blk :: AN_advertisement0
 ***************************************************************************/
/* AN_ieee1Blk :: AN_advertisement0 :: NP [15:15] */
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_MASK                      0x8000
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_ALIGN                     0
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_BITS                      1
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_SHIFT                     15

/* AN_ieee1Blk :: AN_advertisement0 :: Ack [14:14] */
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_MASK                     0x4000
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_ALIGN                    0
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_BITS                     1
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_SHIFT                    14

/* AN_ieee1Blk :: AN_advertisement0 :: RF [13:13] */
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_MASK                      0x2000
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_ALIGN                     0
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_BITS                      1
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_SHIFT                     13

/* AN_ieee1Blk :: AN_advertisement0 :: XNP_able [12:12] */
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_XNP_ABLE_MASK                0x1000
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_XNP_ABLE_ALIGN               0
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_XNP_ABLE_BITS                1
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_XNP_ABLE_SHIFT               12

/* AN_ieee1Blk :: AN_advertisement0 :: techAbility [11:05] */
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_TECHABILITY_MASK             0x0fe0
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_TECHABILITY_ALIGN            0
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_TECHABILITY_BITS             7
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_TECHABILITY_SHIFT            5

/* AN_ieee1Blk :: AN_advertisement0 :: selector [04:00] */
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_MASK                0x001f
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_ALIGN               0
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_BITS                5
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_SHIFT               0

#define CL73_AN_ADV_TECH_10G_KX4 (1 << 6)
#define CL73_AN_ADV_TECH_1G_KX   (1 << 5)
#define CL73_AN_ADV_TECH_SPEEDS_MASK  (0x7 << 5)
#define CL73_AN_ADV_PAUSE                                (1 << 10)
#define CL73_AN_ADV_ASYM_PAUSE                           (1 << 11)

/****************************************************************************
 * AN_ieee1Blk :: AN_LP_basePageAbility0
 ***************************************************************************/
/* AN_ieee1Blk :: AN_LP_basePageAbility0 :: NP [15:15] */
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_MASK                 0x8000
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_ALIGN                0
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_BITS                 1
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_SHIFT                15

/* AN_ieee1Blk :: AN_LP_basePageAbility0 :: Ack [14:14] */
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_MASK                0x4000
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_ALIGN               0
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_BITS                1
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_SHIFT               14

/* AN_ieee1Blk :: AN_LP_basePageAbility0 :: RF [13:13] */
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_MASK                 0x2000
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_ALIGN                0
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_BITS                 1
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_SHIFT                13

/* AN_ieee1Blk :: AN_LP_basePageAbility0 :: XNP_able [12:12] */
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_XNP_ABLE_MASK           0x1000
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_XNP_ABLE_ALIGN          0
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_XNP_ABLE_BITS           1
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_XNP_ABLE_SHIFT          12

/* AN_ieee1Blk :: AN_LP_basePageAbility0 :: techAbility [11:05] */
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_TECHABILITY_MASK        0x0fe0
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_TECHABILITY_ALIGN       0
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_TECHABILITY_BITS        7
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_TECHABILITY_SHIFT       5

/* AN_ieee1Blk :: AN_LP_basePageAbility0 :: selector [04:00] */
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_MASK           0x001f
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_ALIGN          0
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_BITS           5
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_SHIFT          0


/****************************************************************************
 * AN_ieee1Blk :: AN_XNP_transmit0
 ***************************************************************************/
/* AN_ieee1Blk :: AN_XNP_transmit0 :: NP [15:15] */
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_MASK                       0x8000
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_ALIGN                      0
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_BITS                       1
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_SHIFT                      15

/* AN_ieee1Blk :: AN_XNP_transmit0 :: reserved0 [14:14] */
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_MASK                0x4000
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_ALIGN               0
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_BITS                1
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_SHIFT               14

/* AN_ieee1Blk :: AN_XNP_transmit0 :: MP [13:13] */
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_MASK                       0x2000
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_ALIGN                      0
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_BITS                       1
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_SHIFT                      13

/* AN_ieee1Blk :: AN_XNP_transmit0 :: Ack2 [12:12] */
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_MASK                     0x1000
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_ALIGN                    0
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_BITS                     1
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_SHIFT                    12

/* AN_ieee1Blk :: AN_XNP_transmit0 :: Toggle [11:11] */
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_MASK                   0x0800
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_ALIGN                  0
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_BITS                   1
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_SHIFT                  11

/* AN_ieee1Blk :: AN_XNP_transmit0 :: MSG [10:00] */
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_MASK                      0x07ff
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_ALIGN                     0
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_BITS                      11
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_SHIFT                     0


/****************************************************************************
 * AN_ieee1Blk :: AN_XNP_transmit1
 ***************************************************************************/
/* AN_ieee1Blk :: AN_XNP_transmit1 :: UCF1 [15:00] */
#define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_MASK                     0xffff
#define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_ALIGN                    0
#define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_BITS                     16
#define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_SHIFT                    0


/****************************************************************************
 * AN_ieee1Blk :: AN_XNP_transmit2
 ***************************************************************************/
/* AN_ieee1Blk :: AN_XNP_transmit2 :: UCF2 [15:00] */
#define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_MASK                     0xffff
#define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_ALIGN                    0
#define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_BITS                     16
#define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_SHIFT                    0


/****************************************************************************
 * AN_ieee1Blk :: AN_LP_XNP_ability0
 ***************************************************************************/
/* AN_ieee1Blk :: AN_LP_XNP_ability0 :: NP [15:15] */
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_MASK                     0x8000
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_ALIGN                    0
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_BITS                     1
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_SHIFT                    15

/* AN_ieee1Blk :: AN_LP_XNP_ability0 :: reserved0 [14:14] */
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_MASK              0x4000
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_ALIGN             0
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_BITS              1
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_SHIFT             14

/* AN_ieee1Blk :: AN_LP_XNP_ability0 :: MP [13:13] */
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_MASK                     0x2000
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_ALIGN                    0
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_BITS                     1
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_SHIFT                    13

/* AN_ieee1Blk :: AN_LP_XNP_ability0 :: Ack2 [12:12] */
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_MASK                   0x1000
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_ALIGN                  0
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_BITS                   1
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_SHIFT                  12

/* AN_ieee1Blk :: AN_LP_XNP_ability0 :: Toggle [11:11] */
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_MASK                 0x0800
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_ALIGN                0
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_BITS                 1
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_SHIFT                11

/* AN_ieee1Blk :: AN_LP_XNP_ability0 :: MSG [10:00] */
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_MASK                    0x07ff
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_ALIGN                   0
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_BITS                    11
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_SHIFT                   0


/****************************************************************************
 * AN_ieee1Blk :: AN_LP_XNP_ability1
 ***************************************************************************/
/* AN_ieee1Blk :: AN_LP_XNP_ability1 :: UCF1 [15:00] */
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_MASK                   0xffff
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_ALIGN                  0
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_BITS                   16
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_SHIFT                  0


/****************************************************************************
 * AN_ieee1Blk :: AN_LP_XNP_ability2
 ***************************************************************************/
/* AN_ieee1Blk :: AN_LP_XNP_ability2 :: UCF2 [15:00] */
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_MASK                   0xffff
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_ALIGN                  0
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_BITS                   16
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_SHIFT                  0


/****************************************************************************
 * Hypercore_IEEE_CL73_AN_ieee3Blk
 ***************************************************************************/
/****************************************************************************
 * AN_ieee3Blk :: AN_BPstatus
 ***************************************************************************/
/* AN_ieee3Blk :: AN_BPstatus :: reserved0 [15:10] */
#define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_MASK                     0xfc00
#define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_ALIGN                    0
#define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_BITS                     6
#define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_SHIFT                    10

/* AN_ieee3Blk :: AN_BPstatus :: pdetFault [09:09] */
#define AN_IEEE3BLK_AN_BPSTATUS_PDETFAULT_MASK                     0x0200
#define AN_IEEE3BLK_AN_BPSTATUS_PDETFAULT_ALIGN                    0
#define AN_IEEE3BLK_AN_BPSTATUS_PDETFAULT_BITS                     1
#define AN_IEEE3BLK_AN_BPSTATUS_PDETFAULT_SHIFT                    9

/* AN_ieee3Blk :: AN_BPstatus :: reserved1 [08:08] */
#define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_MASK                     0x0100
#define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_ALIGN                    0
#define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_BITS                     1
#define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_SHIFT                    8

/* AN_ieee3Blk :: AN_BPstatus :: XNPstatus [07:07] */
#define AN_IEEE3BLK_AN_BPSTATUS_XNPSTATUS_MASK                     0x0080
#define AN_IEEE3BLK_AN_BPSTATUS_XNPSTATUS_ALIGN                    0
#define AN_IEEE3BLK_AN_BPSTATUS_XNPSTATUS_BITS                     1
#define AN_IEEE3BLK_AN_BPSTATUS_XNPSTATUS_SHIFT                    7

/* AN_ieee3Blk :: AN_BPstatus :: pageRcvd [06:06] */
#define AN_IEEE3BLK_AN_BPSTATUS_PAGERCVD_MASK                      0x0040
#define AN_IEEE3BLK_AN_BPSTATUS_PAGERCVD_ALIGN                     0
#define AN_IEEE3BLK_AN_BPSTATUS_PAGERCVD_BITS                      1
#define AN_IEEE3BLK_AN_BPSTATUS_PAGERCVD_SHIFT                     6

/* AN_ieee3Blk :: AN_BPstatus :: ANcomplete [05:05] */
#define AN_IEEE3BLK_AN_BPSTATUS_ANCOMPLETE_MASK                    0x0020
#define AN_IEEE3BLK_AN_BPSTATUS_ANCOMPLETE_ALIGN                   0
#define AN_IEEE3BLK_AN_BPSTATUS_ANCOMPLETE_BITS                    1
#define AN_IEEE3BLK_AN_BPSTATUS_ANCOMPLETE_SHIFT                   5

/* AN_ieee3Blk :: AN_BPstatus :: RF [04:04] */
#define AN_IEEE3BLK_AN_BPSTATUS_RF_MASK                            0x0010
#define AN_IEEE3BLK_AN_BPSTATUS_RF_ALIGN                           0
#define AN_IEEE3BLK_AN_BPSTATUS_RF_BITS                            1
#define AN_IEEE3BLK_AN_BPSTATUS_RF_SHIFT                           4

/* AN_ieee3Blk :: AN_BPstatus :: AN_able [03:03] */
#define AN_IEEE3BLK_AN_BPSTATUS_AN_ABLE_MASK                       0x0008
#define AN_IEEE3BLK_AN_BPSTATUS_AN_ABLE_ALIGN                      0
#define AN_IEEE3BLK_AN_BPSTATUS_AN_ABLE_BITS                       1
#define AN_IEEE3BLK_AN_BPSTATUS_AN_ABLE_SHIFT                      3

/* AN_ieee3Blk :: AN_BPstatus :: Link [02:02] */
#define AN_IEEE3BLK_AN_BPSTATUS_LINK_MASK                          0x0004
#define AN_IEEE3BLK_AN_BPSTATUS_LINK_ALIGN                         0
#define AN_IEEE3BLK_AN_BPSTATUS_LINK_BITS                          1
#define AN_IEEE3BLK_AN_BPSTATUS_LINK_SHIFT                         2

/* AN_ieee3Blk :: AN_BPstatus :: reserved2 [01:01] */
#define AN_IEEE3BLK_AN_BPSTATUS_RESERVED2_MASK                     0x0002
#define AN_IEEE3BLK_AN_BPSTATUS_RESERVED2_ALIGN                    0
#define AN_IEEE3BLK_AN_BPSTATUS_RESERVED2_BITS                     1
#define AN_IEEE3BLK_AN_BPSTATUS_RESERVED2_SHIFT                    1

/* AN_ieee3Blk :: AN_BPstatus :: LP_AN_able [00:00] */
#define AN_IEEE3BLK_AN_BPSTATUS_LP_AN_ABLE_MASK                    0x0001
#define AN_IEEE3BLK_AN_BPSTATUS_LP_AN_ABLE_ALIGN                   0
#define AN_IEEE3BLK_AN_BPSTATUS_LP_AN_ABLE_BITS                    1
#define AN_IEEE3BLK_AN_BPSTATUS_LP_AN_ABLE_SHIFT                   0


/****************************************************************************
 * Datatype Definitions.
 ***************************************************************************/
#endif /* #ifndef HC65_H__ */

/* End of File */
